Lines Matching +full:freq +full:- +full:table +full:- +full:hz
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
8 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <dt-bindings/clock/qcom,gcc-sc8180x.h>
10 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/interconnect/qcom,icc.h>
13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
14 #include <dt-bindings/interconnect/qcom,sc8180x.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/phy/phy-qcom-qmp.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
19 #include <dt-bindings/thermal/thermal.h>
22 interrupt-parent = <&intc>;
24 #address-cells = <2>;
25 #size-cells = <2>;
28 xo_board_clk: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
34 sleep_clk: sleep-clk {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32764>;
38 clock-output-names = "sleep_clk";
43 #address-cells = <2>;
44 #size-cells = <0>;
50 enable-method = "psci";
51 capacity-dmips-mhz = <602>;
52 next-level-cache = <&l2_0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
54 operating-points-v2 = <&cpu0_opp_table>;
57 power-domains = <&cpu_pd0>;
58 power-domain-names = "psci";
59 #cooling-cells = <2>;
62 l2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&l3_0>;
67 l3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
79 enable-method = "psci";
80 capacity-dmips-mhz = <602>;
81 next-level-cache = <&l2_100>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
83 operating-points-v2 = <&cpu0_opp_table>;
86 power-domains = <&cpu_pd1>;
87 power-domain-names = "psci";
88 #cooling-cells = <2>;
91 l2_100: l2-cache {
93 cache-level = <2>;
94 cache-unified;
95 next-level-cache = <&l3_0>;
104 enable-method = "psci";
105 capacity-dmips-mhz = <602>;
106 next-level-cache = <&l2_200>;
107 qcom,freq-domain = <&cpufreq_hw 0>;
108 operating-points-v2 = <&cpu0_opp_table>;
111 power-domains = <&cpu_pd2>;
112 power-domain-names = "psci";
113 #cooling-cells = <2>;
116 l2_200: l2-cache {
118 cache-level = <2>;
119 cache-unified;
120 next-level-cache = <&l3_0>;
128 enable-method = "psci";
129 capacity-dmips-mhz = <602>;
130 next-level-cache = <&l2_300>;
131 qcom,freq-domain = <&cpufreq_hw 0>;
132 operating-points-v2 = <&cpu0_opp_table>;
135 power-domains = <&cpu_pd3>;
136 power-domain-names = "psci";
137 #cooling-cells = <2>;
140 l2_300: l2-cache {
142 cache-unified;
143 cache-level = <2>;
144 next-level-cache = <&l3_0>;
152 enable-method = "psci";
153 capacity-dmips-mhz = <1024>;
154 next-level-cache = <&l2_400>;
155 qcom,freq-domain = <&cpufreq_hw 1>;
156 operating-points-v2 = <&cpu4_opp_table>;
159 power-domains = <&cpu_pd4>;
160 power-domain-names = "psci";
161 #cooling-cells = <2>;
164 l2_400: l2-cache {
166 cache-unified;
167 cache-level = <2>;
168 next-level-cache = <&l3_0>;
176 enable-method = "psci";
177 capacity-dmips-mhz = <1024>;
178 next-level-cache = <&l2_500>;
179 qcom,freq-domain = <&cpufreq_hw 1>;
180 operating-points-v2 = <&cpu4_opp_table>;
183 power-domains = <&cpu_pd5>;
184 power-domain-names = "psci";
185 #cooling-cells = <2>;
188 l2_500: l2-cache {
190 cache-unified;
191 cache-level = <2>;
192 next-level-cache = <&l3_0>;
200 enable-method = "psci";
201 capacity-dmips-mhz = <1024>;
202 next-level-cache = <&l2_600>;
203 qcom,freq-domain = <&cpufreq_hw 1>;
204 operating-points-v2 = <&cpu4_opp_table>;
207 power-domains = <&cpu_pd6>;
208 power-domain-names = "psci";
209 #cooling-cells = <2>;
212 l2_600: l2-cache {
214 cache-unified;
215 cache-level = <2>;
216 next-level-cache = <&l3_0>;
224 enable-method = "psci";
225 capacity-dmips-mhz = <1024>;
226 next-level-cache = <&l2_700>;
227 qcom,freq-domain = <&cpufreq_hw 1>;
228 operating-points-v2 = <&cpu4_opp_table>;
231 power-domains = <&cpu_pd7>;
232 power-domain-names = "psci";
233 #cooling-cells = <2>;
236 l2_700: l2-cache {
238 cache-unified;
239 cache-level = <2>;
240 next-level-cache = <&l3_0>;
244 cpu-map {
280 idle-states {
281 entry-method = "psci";
283 little_cpu_sleep_0: cpu-sleep-0-0 {
284 compatible = "arm,idle-state";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <355>;
287 exit-latency-us = <909>;
288 min-residency-us = <3934>;
289 local-timer-stop;
292 big_cpu_sleep_0: cpu-sleep-1-0 {
293 compatible = "arm,idle-state";
294 arm,psci-suspend-param = <0x40000004>;
295 entry-latency-us = <2411>;
296 exit-latency-us = <1461>;
297 min-residency-us = <4488>;
298 local-timer-stop;
302 domain-idle-states {
303 cluster_sleep_apss_off: cluster-sleep-0 {
304 compatible = "domain-idle-state";
305 arm,psci-suspend-param = <0x41000044>;
306 entry-latency-us = <3300>;
307 exit-latency-us = <3300>;
308 min-residency-us = <6000>;
311 cluster_sleep_aoss_sleep: cluster-sleep-1 {
312 compatible = "domain-idle-state";
313 arm,psci-suspend-param = <0x4100a344>;
314 entry-latency-us = <3263>;
315 exit-latency-us = <6562>;
316 min-residency-us = <9987>;
321 cpu0_opp_table: opp-table-cpu0 {
322 compatible = "operating-points-v2";
323 opp-shared;
325 opp-300000000 {
326 opp-hz = /bits/ 64 <300000000>;
327 opp-peak-kBps = <800000 9600000>;
330 opp-422400000 {
331 opp-hz = /bits/ 64 <422400000>;
332 opp-peak-kBps = <800000 9600000>;
335 opp-537600000 {
336 opp-hz = /bits/ 64 <537600000>;
337 opp-peak-kBps = <800000 12902400>;
340 opp-652800000 {
341 opp-hz = /bits/ 64 <652800000>;
342 opp-peak-kBps = <800000 12902400>;
345 opp-768000000 {
346 opp-hz = /bits/ 64 <768000000>;
347 opp-peak-kBps = <800000 15974400>;
350 opp-883200000 {
351 opp-hz = /bits/ 64 <883200000>;
352 opp-peak-kBps = <1804000 19660800>;
355 opp-998400000 {
356 opp-hz = /bits/ 64 <998400000>;
357 opp-peak-kBps = <1804000 19660800>;
360 opp-1113600000 {
361 opp-hz = /bits/ 64 <1113600000>;
362 opp-peak-kBps = <1804000 22732800>;
365 opp-1228800000 {
366 opp-hz = /bits/ 64 <1228800000>;
367 opp-peak-kBps = <1804000 22732800>;
370 opp-1363200000 {
371 opp-hz = /bits/ 64 <1363200000>;
372 opp-peak-kBps = <2188000 25804800>;
375 opp-1478400000 {
376 opp-hz = /bits/ 64 <1478400000>;
377 opp-peak-kBps = <2188000 31948800>;
380 opp-1574400000 {
381 opp-hz = /bits/ 64 <1574400000>;
382 opp-peak-kBps = <3072000 31948800>;
385 opp-1670400000 {
386 opp-hz = /bits/ 64 <1670400000>;
387 opp-peak-kBps = <3072000 31948800>;
390 opp-1766400000 {
391 opp-hz = /bits/ 64 <1766400000>;
392 opp-peak-kBps = <3072000 31948800>;
396 cpu4_opp_table: opp-table-cpu4 {
397 compatible = "operating-points-v2";
398 opp-shared;
400 opp-825600000 {
401 opp-hz = /bits/ 64 <825600000>;
402 opp-peak-kBps = <1804000 15974400>;
405 opp-940800000 {
406 opp-hz = /bits/ 64 <940800000>;
407 opp-peak-kBps = <2188000 19660800>;
410 opp-1056000000 {
411 opp-hz = /bits/ 64 <1056000000>;
412 opp-peak-kBps = <2188000 22732800>;
415 opp-1171200000 {
416 opp-hz = /bits/ 64 <1171200000>;
417 opp-peak-kBps = <3072000 25804800>;
420 opp-1286400000 {
421 opp-hz = /bits/ 64 <1286400000>;
422 opp-peak-kBps = <3072000 31948800>;
425 opp-1420800000 {
426 opp-hz = /bits/ 64 <1420800000>;
427 opp-peak-kBps = <4068000 31948800>;
430 opp-1536000000 {
431 opp-hz = /bits/ 64 <1536000000>;
432 opp-peak-kBps = <4068000 31948800>;
435 opp-1651200000 {
436 opp-hz = /bits/ 64 <1651200000>;
437 opp-peak-kBps = <4068000 40550400>;
440 opp-1766400000 {
441 opp-hz = /bits/ 64 <1766400000>;
442 opp-peak-kBps = <4068000 40550400>;
445 opp-1881600000 {
446 opp-hz = /bits/ 64 <1881600000>;
447 opp-peak-kBps = <4068000 43008000>;
450 opp-1996800000 {
451 opp-hz = /bits/ 64 <1996800000>;
452 opp-peak-kBps = <6220000 43008000>;
455 opp-2131200000 {
456 opp-hz = /bits/ 64 <2131200000>;
457 opp-peak-kBps = <6220000 49152000>;
460 opp-2246400000 {
461 opp-hz = /bits/ 64 <2246400000>;
462 opp-peak-kBps = <7216000 49152000>;
465 opp-2361600000 {
466 opp-hz = /bits/ 64 <2361600000>;
467 opp-peak-kBps = <8368000 49152000>;
470 opp-2457600000 {
471 opp-hz = /bits/ 64 <2457600000>;
472 opp-peak-kBps = <8368000 51609600>;
475 opp-2553600000 {
476 opp-hz = /bits/ 64 <2553600000>;
477 opp-peak-kBps = <8368000 51609600>;
480 opp-2649600000 {
481 opp-hz = /bits/ 64 <2649600000>;
482 opp-peak-kBps = <8368000 51609600>;
485 opp-2745600000 {
486 opp-hz = /bits/ 64 <2745600000>;
487 opp-peak-kBps = <8368000 51609600>;
490 opp-2841600000 {
491 opp-hz = /bits/ 64 <2841600000>;
492 opp-peak-kBps = <8368000 51609600>;
495 opp-2918400000 {
496 opp-hz = /bits/ 64 <2918400000>;
497 opp-peak-kBps = <8368000 51609600>;
500 opp-2995200000 {
501 opp-hz = /bits/ 64 <2995200000>;
502 opp-peak-kBps = <8368000 51609600>;
508 compatible = "qcom,scm-sc8180x", "qcom,scm";
512 camnoc_virt: interconnect-camnoc-virt {
513 compatible = "qcom,sc8180x-camnoc-virt";
514 #interconnect-cells = <2>;
515 qcom,bcm-voters = <&apps_bcm_voter>;
518 mc_virt: interconnect-mc-virt {
519 compatible = "qcom,sc8180x-mc-virt";
520 #interconnect-cells = <2>;
521 qcom,bcm-voters = <&apps_bcm_voter>;
524 qup_virt: interconnect-qup-virt {
525 compatible = "qcom,sc8180x-qup-virt";
526 #interconnect-cells = <2>;
527 qcom,bcm-voters = <&apps_bcm_voter>;
537 compatible = "arm,armv8-pmuv3";
542 compatible = "arm,psci-1.0";
545 cpu_pd0: power-domain-cpu0 {
546 #power-domain-cells = <0>;
547 power-domains = <&cluster_pd>;
548 domain-idle-states = <&little_cpu_sleep_0>;
551 cpu_pd1: power-domain-cpu1 {
552 #power-domain-cells = <0>;
553 power-domains = <&cluster_pd>;
554 domain-idle-states = <&little_cpu_sleep_0>;
557 cpu_pd2: power-domain-cpu2 {
558 #power-domain-cells = <0>;
559 power-domains = <&cluster_pd>;
560 domain-idle-states = <&little_cpu_sleep_0>;
563 cpu_pd3: power-domain-cpu3 {
564 #power-domain-cells = <0>;
565 power-domains = <&cluster_pd>;
566 domain-idle-states = <&little_cpu_sleep_0>;
569 cpu_pd4: power-domain-cpu4 {
570 #power-domain-cells = <0>;
571 power-domains = <&cluster_pd>;
572 domain-idle-states = <&big_cpu_sleep_0>;
575 cpu_pd5: power-domain-cpu5 {
576 #power-domain-cells = <0>;
577 power-domains = <&cluster_pd>;
578 domain-idle-states = <&big_cpu_sleep_0>;
581 cpu_pd6: power-domain-cpu6 {
582 #power-domain-cells = <0>;
583 power-domains = <&cluster_pd>;
584 domain-idle-states = <&big_cpu_sleep_0>;
587 cpu_pd7: power-domain-cpu7 {
588 #power-domain-cells = <0>;
589 power-domains = <&cluster_pd>;
590 domain-idle-states = <&big_cpu_sleep_0>;
593 cluster_pd: power-domain-cpu-cluster0 {
594 #power-domain-cells = <0>;
595 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>;
599 reserved-memory {
600 #address-cells = <2>;
601 #size-cells = <2>;
606 no-map;
611 no-map;
616 no-map;
619 aop_cmd_db: cmd-db@85f20000 {
620 compatible = "qcom,cmd-db";
622 no-map;
627 no-map;
633 no-map;
639 no-map;
644 no-map;
649 no-map;
654 no-map;
659 no-map;
663 smp2p-cdsp {
671 qcom,local-pid = <0>;
672 qcom,remote-pid = <5>;
674 cdsp_smp2p_out: master-kernel {
675 qcom,entry-name = "master-kernel";
676 #qcom,smem-state-cells = <1>;
679 cdsp_smp2p_in: slave-kernel {
680 qcom,entry-name = "slave-kernel";
682 interrupt-controller;
683 #interrupt-cells = <2>;
687 smp2p-lpass {
695 qcom,local-pid = <0>;
696 qcom,remote-pid = <2>;
698 adsp_smp2p_out: master-kernel {
699 qcom,entry-name = "master-kernel";
700 #qcom,smem-state-cells = <1>;
703 adsp_smp2p_in: slave-kernel {
704 qcom,entry-name = "slave-kernel";
706 interrupt-controller;
707 #interrupt-cells = <2>;
711 smp2p-mpss {
719 qcom,local-pid = <0>;
720 qcom,remote-pid = <1>;
722 modem_smp2p_out: master-kernel {
723 qcom,entry-name = "master-kernel";
724 #qcom,smem-state-cells = <1>;
727 modem_smp2p_in: slave-kernel {
728 qcom,entry-name = "slave-kernel";
730 interrupt-controller;
731 #interrupt-cells = <2>;
734 modem_smp2p_ipa_out: ipa-ap-to-modem {
735 qcom,entry-name = "ipa";
736 #qcom,smem-state-cells = <1>;
739 modem_smp2p_ipa_in: ipa-modem-to-ap {
740 qcom,entry-name = "ipa";
741 interrupt-controller;
742 #interrupt-cells = <2>;
745 modem_smp2p_wlan_in: wlan-wpss-to-ap {
746 qcom,entry-name = "wlan";
747 interrupt-controller;
748 #interrupt-cells = <2>;
752 smp2p-slpi {
760 qcom,local-pid = <0>;
761 qcom,remote-pid = <3>;
763 slpi_smp2p_out: master-kernel {
764 qcom,entry-name = "master-kernel";
765 #qcom,smem-state-cells = <1>;
768 slpi_smp2p_in: slave-kernel {
769 qcom,entry-name = "slave-kernel";
771 interrupt-controller;
772 #interrupt-cells = <2>;
777 compatible = "simple-bus";
778 #address-cells = <2>;
779 #size-cells = <2>;
781 dma-ranges = <0 0 0 0 0x10 0>;
783 gcc: clock-controller@100000 {
784 compatible = "qcom,gcc-sc8180x";
786 #clock-cells = <1>;
787 #reset-cells = <1>;
788 #power-domain-cells = <1>;
792 clock-names = "bi_tcxo",
795 power-domains = <&rpmhpd SC8180X_CX>;
799 compatible = "qcom,geni-se-qup";
803 clock-names = "m-ahb", "s-ahb";
804 #address-cells = <2>;
805 #size-cells = <2>;
811 compatible = "qcom,geni-i2c";
814 clock-names = "se";
819 interconnect-names = "qup-core", "qup-config", "qup-memory";
820 #address-cells = <1>;
821 #size-cells = <0>;
826 compatible = "qcom,geni-spi";
829 clock-names = "se";
833 interconnect-names = "qup-core", "qup-config";
834 #address-cells = <1>;
835 #size-cells = <0>;
840 compatible = "qcom,geni-uart";
843 clock-names = "se";
847 interconnect-names = "qup-core", "qup-config";
852 compatible = "qcom,geni-i2c";
855 clock-names = "se";
860 interconnect-names = "qup-core", "qup-config", "qup-memory";
861 #address-cells = <1>;
862 #size-cells = <0>;
867 compatible = "qcom,geni-spi";
870 clock-names = "se";
874 interconnect-names = "qup-core", "qup-config";
875 #address-cells = <1>;
876 #size-cells = <0>;
881 compatible = "qcom,geni-uart";
884 clock-names = "se";
888 interconnect-names = "qup-core", "qup-config";
893 compatible = "qcom,geni-i2c";
896 clock-names = "se";
901 interconnect-names = "qup-core", "qup-config", "qup-memory";
902 #address-cells = <1>;
903 #size-cells = <0>;
908 compatible = "qcom,geni-spi";
911 clock-names = "se";
915 interconnect-names = "qup-core", "qup-config";
916 #address-cells = <1>;
917 #size-cells = <0>;
922 compatible = "qcom,geni-uart";
925 clock-names = "se";
929 interconnect-names = "qup-core", "qup-config";
934 compatible = "qcom,geni-i2c";
937 clock-names = "se";
942 interconnect-names = "qup-core", "qup-config", "qup-memory";
943 #address-cells = <1>;
944 #size-cells = <0>;
949 compatible = "qcom,geni-spi";
952 clock-names = "se";
956 interconnect-names = "qup-core", "qup-config";
957 #address-cells = <1>;
958 #size-cells = <0>;
963 compatible = "qcom,geni-uart";
966 clock-names = "se";
970 interconnect-names = "qup-core", "qup-config";
975 compatible = "qcom,geni-i2c";
978 clock-names = "se";
983 interconnect-names = "qup-core", "qup-config", "qup-memory";
984 #address-cells = <1>;
985 #size-cells = <0>;
990 compatible = "qcom,geni-spi";
993 clock-names = "se";
997 interconnect-names = "qup-core", "qup-config";
998 #address-cells = <1>;
999 #size-cells = <0>;
1004 compatible = "qcom,geni-uart";
1007 clock-names = "se";
1011 interconnect-names = "qup-core", "qup-config";
1016 compatible = "qcom,geni-i2c";
1019 clock-names = "se";
1024 interconnect-names = "qup-core", "qup-config", "qup-memory";
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1031 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1038 interconnect-names = "qup-core", "qup-config";
1039 #address-cells = <1>;
1040 #size-cells = <0>;
1045 compatible = "qcom,geni-uart";
1048 clock-names = "se";
1052 interconnect-names = "qup-core", "qup-config";
1057 compatible = "qcom,geni-i2c";
1060 clock-names = "se";
1065 interconnect-names = "qup-core", "qup-config", "qup-memory";
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1072 compatible = "qcom,geni-spi";
1075 clock-names = "se";
1079 interconnect-names = "qup-core", "qup-config";
1080 #address-cells = <1>;
1081 #size-cells = <0>;
1086 compatible = "qcom,geni-uart";
1089 clock-names = "se";
1093 interconnect-names = "qup-core", "qup-config";
1098 compatible = "qcom,geni-i2c";
1101 clock-names = "se";
1106 interconnect-names = "qup-core", "qup-config", "qup-memory";
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-spi";
1116 clock-names = "se";
1120 interconnect-names = "qup-core", "qup-config";
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1127 compatible = "qcom,geni-uart";
1130 clock-names = "se";
1134 interconnect-names = "qup-core", "qup-config";
1140 compatible = "qcom,geni-se-qup";
1144 clock-names = "m-ahb", "s-ahb";
1145 #address-cells = <2>;
1146 #size-cells = <2>;
1152 compatible = "qcom,geni-i2c";
1155 clock-names = "se";
1160 interconnect-names = "qup-core", "qup-config", "qup-memory";
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1167 compatible = "qcom,geni-spi";
1170 clock-names = "se";
1174 interconnect-names = "qup-core", "qup-config";
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1181 compatible = "qcom,geni-uart";
1184 clock-names = "se";
1188 interconnect-names = "qup-core", "qup-config";
1193 compatible = "qcom,geni-i2c";
1196 clock-names = "se";
1201 interconnect-names = "qup-core", "qup-config", "qup-memory";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1208 compatible = "qcom,geni-spi";
1211 clock-names = "se";
1215 interconnect-names = "qup-core", "qup-config";
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1222 compatible = "qcom,geni-debug-uart";
1225 clock-names = "se";
1229 interconnect-names = "qup-core", "qup-config";
1234 compatible = "qcom,geni-i2c";
1237 clock-names = "se";
1242 interconnect-names = "qup-core", "qup-config", "qup-memory";
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1249 compatible = "qcom,geni-spi";
1252 clock-names = "se";
1256 interconnect-names = "qup-core", "qup-config";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1263 compatible = "qcom,geni-uart";
1266 clock-names = "se";
1270 interconnect-names = "qup-core", "qup-config";
1275 compatible = "qcom,geni-i2c";
1278 clock-names = "se";
1283 interconnect-names = "qup-core", "qup-config", "qup-memory";
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-spi";
1293 clock-names = "se";
1297 interconnect-names = "qup-core", "qup-config";
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-uart";
1307 clock-names = "se";
1311 interconnect-names = "qup-core", "qup-config";
1316 compatible = "qcom,geni-i2c";
1319 clock-names = "se";
1324 interconnect-names = "qup-core", "qup-config", "qup-memory";
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1331 compatible = "qcom,geni-spi";
1334 clock-names = "se";
1338 interconnect-names = "qup-core", "qup-config";
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1345 compatible = "qcom,geni-uart";
1348 clock-names = "se";
1352 interconnect-names = "qup-core", "qup-config";
1357 compatible = "qcom,geni-i2c";
1360 clock-names = "se";
1365 interconnect-names = "qup-core", "qup-config", "qup-memory";
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1372 compatible = "qcom,geni-spi";
1375 clock-names = "se";
1379 interconnect-names = "qup-core", "qup-config";
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1386 compatible = "qcom,geni-uart";
1389 clock-names = "se";
1393 interconnect-names = "qup-core", "qup-config";
1399 compatible = "qcom,geni-se-qup";
1403 clock-names = "m-ahb", "s-ahb";
1404 #address-cells = <2>;
1405 #size-cells = <2>;
1411 compatible = "qcom,geni-i2c";
1414 clock-names = "se";
1419 interconnect-names = "qup-core", "qup-config", "qup-memory";
1420 #address-cells = <1>;
1421 #size-cells = <0>;
1426 compatible = "qcom,geni-spi";
1429 clock-names = "se";
1433 interconnect-names = "qup-core", "qup-config";
1434 #address-cells = <1>;
1435 #size-cells = <0>;
1440 compatible = "qcom,geni-uart";
1443 clock-names = "se";
1447 interconnect-names = "qup-core", "qup-config";
1452 compatible = "qcom,geni-i2c";
1455 clock-names = "se";
1460 interconnect-names = "qup-core", "qup-config", "qup-memory";
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1467 compatible = "qcom,geni-spi";
1470 clock-names = "se";
1474 interconnect-names = "qup-core", "qup-config";
1475 #address-cells = <1>;
1476 #size-cells = <0>;
1481 compatible = "qcom,geni-uart";
1484 clock-names = "se";
1488 interconnect-names = "qup-core", "qup-config";
1493 compatible = "qcom,geni-i2c";
1496 clock-names = "se";
1501 interconnect-names = "qup-core", "qup-config", "qup-memory";
1502 #address-cells = <1>;
1503 #size-cells = <0>;
1508 compatible = "qcom,geni-spi";
1511 clock-names = "se";
1515 interconnect-names = "qup-core", "qup-config";
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1522 compatible = "qcom,geni-uart";
1525 clock-names = "se";
1529 interconnect-names = "qup-core", "qup-config";
1534 compatible = "qcom,geni-i2c";
1537 clock-names = "se";
1542 interconnect-names = "qup-core", "qup-config", "qup-memory";
1543 #address-cells = <1>;
1544 #size-cells = <0>;
1549 compatible = "qcom,geni-spi";
1552 clock-names = "se";
1556 interconnect-names = "qup-core", "qup-config";
1557 #address-cells = <1>;
1558 #size-cells = <0>;
1563 compatible = "qcom,geni-uart";
1566 clock-names = "se";
1570 interconnect-names = "qup-core", "qup-config";
1575 compatible = "qcom,geni-i2c";
1578 clock-names = "se";
1583 interconnect-names = "qup-core", "qup-config", "qup-memory";
1584 #address-cells = <1>;
1585 #size-cells = <0>;
1590 compatible = "qcom,geni-spi";
1593 clock-names = "se";
1597 interconnect-names = "qup-core", "qup-config";
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1604 compatible = "qcom,geni-uart";
1607 clock-names = "se";
1611 interconnect-names = "qup-core", "qup-config";
1616 compatible = "qcom,geni-i2c";
1619 clock-names = "se";
1624 interconnect-names = "qup-core", "qup-config", "qup-memory";
1625 #address-cells = <1>;
1626 #size-cells = <0>;
1631 compatible = "qcom,geni-spi";
1634 clock-names = "se";
1638 interconnect-names = "qup-core", "qup-config";
1639 #address-cells = <1>;
1640 #size-cells = <0>;
1645 compatible = "qcom,geni-uart";
1648 clock-names = "se";
1652 interconnect-names = "qup-core", "qup-config";
1658 compatible = "qcom,sc8180x-config-noc";
1660 #interconnect-cells = <2>;
1661 qcom,bcm-voters = <&apps_bcm_voter>;
1665 compatible = "qcom,sc8180x-system-noc";
1667 #interconnect-cells = <2>;
1668 qcom,bcm-voters = <&apps_bcm_voter>;
1672 compatible = "qcom,sc8180x-aggre1-noc";
1674 #interconnect-cells = <2>;
1675 qcom,bcm-voters = <&apps_bcm_voter>;
1679 compatible = "qcom,sc8180x-aggre2-noc";
1681 #interconnect-cells = <2>;
1682 qcom,bcm-voters = <&apps_bcm_voter>;
1686 compatible = "qcom,sc8180x-compute-noc";
1688 #interconnect-cells = <2>;
1689 qcom,bcm-voters = <&apps_bcm_voter>;
1693 compatible = "qcom,sc8180x-mmss-noc";
1695 #interconnect-cells = <2>;
1696 qcom,bcm-voters = <&apps_bcm_voter>;
1700 compatible = "qcom,pcie-sc8180x";
1706 reg-names = "parf",
1712 linux,pci-domain = <0>;
1713 bus-range = <0x00 0xff>;
1714 num-lanes = <2>;
1716 #address-cells = <3>;
1717 #size-cells = <2>;
1730 interrupt-names = "msi0",
1738 #interrupt-cells = <1>;
1739 interrupt-map-mask = <0 0 0 0x7>;
1740 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1753 clock-names = "pipe",
1762 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
1763 assigned-clock-rates = <19200000>;
1765 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
1769 reset-names = "pci";
1771 power-domains = <&gcc PCIE_0_GDSC>;
1775 interconnect-names = "pcie-mem", "cpu-pcie";
1778 phy-names = "pciephy";
1779 dma-coherent;
1786 bus-range = <0x01 0xff>;
1788 #address-cells = <3>;
1789 #size-cells = <2>;
1795 compatible = "qcom,sc8180x-qmp-pcie-phy";
1802 clock-names = "aux",
1807 #clock-cells = <0>;
1808 clock-output-names = "pcie_0_pipe_clk";
1809 #phy-cells = <0>;
1812 reset-names = "phy";
1814 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
1815 assigned-clock-rates = <100000000>;
1821 compatible = "qcom,pcie-sc8180x";
1827 reg-names = "parf",
1833 linux,pci-domain = <3>;
1834 bus-range = <0x00 0xff>;
1835 num-lanes = <2>;
1837 #address-cells = <3>;
1838 #size-cells = <2>;
1851 interrupt-names = "msi0",
1859 #interrupt-cells = <1>;
1860 interrupt-map-mask = <0 0 0 0x7>;
1861 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1874 clock-names = "pipe",
1883 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
1884 assigned-clock-rates = <19200000>;
1886 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
1890 reset-names = "pci";
1892 power-domains = <&gcc PCIE_3_GDSC>;
1896 interconnect-names = "pcie-mem", "cpu-pcie";
1899 phy-names = "pciephy";
1900 dma-coherent;
1907 bus-range = <0x01 0xff>;
1909 #address-cells = <3>;
1910 #size-cells = <2>;
1916 compatible = "qcom,sc8180x-qmp-pcie-phy";
1923 clock-names = "aux",
1928 #clock-cells = <0>;
1929 clock-output-names = "pcie_3_pipe_clk";
1931 #phy-cells = <0>;
1934 reset-names = "phy";
1936 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>;
1937 assigned-clock-rates = <100000000>;
1943 compatible = "qcom,pcie-sc8180x";
1949 reg-names = "parf",
1955 linux,pci-domain = <1>;
1956 bus-range = <0x00 0xff>;
1957 num-lanes = <2>;
1959 #address-cells = <3>;
1960 #size-cells = <2>;
1973 interrupt-names = "msi0",
1981 #interrupt-cells = <1>;
1982 interrupt-map-mask = <0 0 0 0x7>;
1983 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1996 clock-names = "pipe",
2005 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2006 assigned-clock-rates = <19200000>;
2008 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2012 reset-names = "pci";
2014 power-domains = <&gcc PCIE_1_GDSC>;
2018 interconnect-names = "pcie-mem", "cpu-pcie";
2021 phy-names = "pciephy";
2022 dma-coherent;
2029 bus-range = <0x01 0xff>;
2031 #address-cells = <3>;
2032 #size-cells = <2>;
2038 compatible = "qcom,sc8180x-qmp-pcie-phy";
2045 clock-names = "aux",
2050 #clock-cells = <0>;
2051 clock-output-names = "pcie_1_pipe_clk";
2053 #phy-cells = <0>;
2056 reset-names = "phy";
2058 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
2059 assigned-clock-rates = <100000000>;
2065 compatible = "qcom,pcie-sc8180x";
2071 reg-names = "parf",
2077 linux,pci-domain = <2>;
2078 bus-range = <0x00 0xff>;
2079 num-lanes = <4>;
2081 #address-cells = <3>;
2082 #size-cells = <2>;
2095 interrupt-names = "msi0",
2103 #interrupt-cells = <1>;
2104 interrupt-map-mask = <0 0 0 0x7>;
2105 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2118 clock-names = "pipe",
2127 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>;
2128 assigned-clock-rates = <19200000>;
2130 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
2134 reset-names = "pci";
2136 power-domains = <&gcc PCIE_2_GDSC>;
2140 interconnect-names = "pcie-mem", "cpu-pcie";
2143 phy-names = "pciephy";
2144 dma-coherent;
2151 bus-range = <0x01 0xff>;
2153 #address-cells = <3>;
2154 #size-cells = <2>;
2160 compatible = "qcom,sc8180x-qmp-pcie-phy";
2167 clock-names = "aux",
2172 #clock-cells = <0>;
2173 clock-output-names = "pcie_2_pipe_clk";
2175 #phy-cells = <0>;
2178 reset-names = "phy";
2180 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>;
2181 assigned-clock-rates = <100000000>;
2187 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc",
2188 "jedec,ufs-2.0";
2192 phy-names = "ufsphy";
2193 lanes-per-direction = <2>;
2194 #reset-cells = <1>;
2196 reset-names = "rst";
2208 clock-names = "core_clk",
2216 freq-table-hz = <37500000 300000000>,
2225 power-domains = <&gcc UFS_PHY_GDSC>;
2231 interconnect-names = "ufs-ddr", "cpu-ufs";
2236 ufs_mem_phy: phy-wrapper@1d87000 {
2237 compatible = "qcom,sc8180x-qmp-ufs-phy";
2243 clock-names = "ref",
2248 reset-names = "ufsphy";
2250 power-domains = <&gcc UFS_PHY_GDSC>;
2252 #phy-cells = <0>;
2258 compatible = "qcom,tcsr-mutex";
2260 #hwlock-cells = <1>;
2264 compatible = "qcom,adreno-680.1", "qcom,adreno";
2267 reg-names = "kgsl_3d0_reg_memory";
2273 operating-points-v2 = <&gpu_opp_table>;
2276 interconnect-names = "gfx-mem";
2279 #cooling-cells = <2>;
2283 gpu_opp_table: opp-table {
2284 compatible = "operating-points-v2";
2286 opp-514000000 {
2287 opp-hz = /bits/ 64 <514000000>;
2288 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2291 opp-500000000 {
2292 opp-hz = /bits/ 64 <500000000>;
2293 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2296 opp-461000000 {
2297 opp-hz = /bits/ 64 <461000000>;
2298 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2301 opp-405000000 {
2302 opp-hz = /bits/ 64 <405000000>;
2303 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2306 opp-315000000 {
2307 opp-hz = /bits/ 64 <315000000>;
2308 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2311 opp-256000000 {
2312 opp-hz = /bits/ 64 <256000000>;
2313 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2316 opp-177000000 {
2317 opp-hz = /bits/ 64 <177000000>;
2318 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2324 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2329 reg-names = "gmu",
2335 interrupt-names = "hfi", "gmu";
2342 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
2344 power-domains = <&gpucc GPU_CX_GDSC>,
2346 power-domain-names = "cx", "gx";
2350 operating-points-v2 = <&gmu_opp_table>;
2352 gmu_opp_table: opp-table {
2353 compatible = "operating-points-v2";
2355 opp-200000000 {
2356 opp-hz = /bits/ 64 <200000000>;
2357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2360 opp-500000000 {
2361 opp-hz = /bits/ 64 <500000000>;
2362 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2367 gpucc: clock-controller@2c90000 {
2368 compatible = "qcom,sc8180x-gpucc";
2373 clock-names = "bi_tcxo",
2376 #clock-cells = <1>;
2377 #reset-cells = <1>;
2378 #power-domain-cells = <1>;
2382 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu",
2383 "qcom,smmu-500", "arm,mmu-500";
2385 #iommu-cells = <2>;
2386 #global-interrupts = <1>;
2399 clock-names = "ahb", "bus", "iface";
2401 power-domains = <&gpucc GPU_CX_GDSC>;
2405 compatible = "qcom,sc8180x-tlmm";
2409 reg-names = "west", "east", "south";
2411 gpio-controller;
2412 #gpio-cells = <2>;
2413 interrupt-controller;
2414 #interrupt-cells = <2>;
2415 gpio-ranges = <&tlmm 0 0 191>;
2416 wakeup-parent = <&pdc>;
2420 compatible = "qcom,sc8180x-mpss-pas";
2423 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2429 interrupt-names = "wdog", "fatal", "ready", "handover",
2430 "stop-ack", "shutdown-ack";
2433 clock-names = "xo";
2435 power-domains = <&rpmhpd SC8180X_CX>,
2437 power-domain-names = "cx", "mss";
2441 qcom,smem-states = <&modem_smp2p_out 0>;
2442 qcom,smem-state-names = "stop";
2444 glink-edge {
2447 qcom,remote-pid = <1>;
2453 compatible = "qcom,sc8180x-cdsp-pas";
2456 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2461 interrupt-names = "wdog", "fatal", "ready",
2462 "handover", "stop-ack";
2465 clock-names = "xo";
2467 power-domains = <&rpmhpd SC8180X_CX>;
2468 power-domain-names = "cx";
2472 qcom,smem-states = <&cdsp_smp2p_out 0>;
2473 qcom,smem-state-names = "stop";
2477 glink-edge {
2480 qcom,remote-pid = <5>;
2486 compatible = "qcom,sc8180x-usb-hs-phy",
2487 "qcom,usb-snps-hs-7nm-phy";
2490 clock-names = "ref";
2493 #phy-cells = <0>;
2499 compatible = "qcom,sc8180x-usb-hs-phy",
2500 "qcom,usb-snps-hs-7nm-phy";
2503 clock-names = "ref";
2506 #phy-cells = <0>;
2512 compatible = "qcom,sc8180x-usb-hs-phy",
2513 "qcom,usb-snps-hs-7nm-phy";
2515 #phy-cells = <0>;
2518 clock-names = "ref";
2526 compatible = "qcom,sc8180x-usb-hs-phy",
2527 "qcom,usb-snps-hs-7nm-phy";
2529 #phy-cells = <0>;
2532 clock-names = "ref";
2540 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2547 clock-names = "aux",
2554 reset-names = "phy", "common";
2556 #clock-cells = <1>;
2557 #phy-cells = <1>;
2562 #address-cells = <1>;
2563 #size-cells = <0>;
2575 remote-endpoint = <&usb_prim_dwc3_ss>;
2588 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2595 clock-names = "aux",
2602 reset-names = "phy", "phy_phy";
2604 power-domains = <&gcc USB30_MP_GDSC>;
2606 #clock-cells = <0>;
2607 clock-output-names = "usb2_phy0_pipe_clk";
2609 #phy-cells = <0>;
2615 compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
2622 clock-names = "aux",
2629 reset-names = "phy", "phy_phy";
2631 power-domains = <&gcc USB30_MP_GDSC>;
2633 #clock-cells = <0>;
2634 clock-output-names = "usb2_phy1_pipe_clk";
2636 #phy-cells = <0>;
2642 compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
2649 clock-names = "aux",
2655 reset-names = "phy", "common";
2657 #clock-cells = <1>;
2658 #phy-cells = <1>;
2663 #address-cells = <1>;
2664 #size-cells = <0>;
2676 remote-endpoint = <&usb_sec_dwc3_ss>;
2688 system-cache-controller@9200000 {
2689 compatible = "qcom,sc8180x-llcc";
2695 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
2702 compatible = "qcom,sc8180x-gem-noc";
2704 #interconnect-cells = <2>;
2705 qcom,bcm-voters = <&apps_bcm_voter>;
2709 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
2711 #address-cells = <2>;
2712 #size-cells = <2>;
2714 dma-ranges;
2722 clock-names = "cfg_noc",
2731 interconnect-names = "usb-ddr", "apps-usb";
2733 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
2735 assigned-clock-rates = <19200000>, <200000000>;
2737 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
2747 interrupt-names = "pwr_event_1", "pwr_event_2",
2753 power-domains = <&gcc USB30_MP_GDSC>;
2766 snps,dis-u1-entry-quirk;
2767 snps,dis-u2-entry-quirk;
2772 phy-names = "usb2-0",
2773 "usb3-0",
2774 "usb2-1",
2775 "usb3-1";
2781 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2783 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2788 interrupt-names = "pwr_event",
2800 clock-names = "cfg_noc",
2807 power-domains = <&gcc USB30_PRIM_GDSC>;
2811 interconnect-names = "usb-ddr", "apps-usb";
2813 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2815 assigned-clock-rates = <19200000>, <200000000>;
2817 #address-cells = <2>;
2818 #size-cells = <2>;
2820 dma-ranges;
2831 snps,dis-u1-entry-quirk;
2832 snps,dis-u2-entry-quirk;
2834 phy-names = "usb2-phy", "usb3-phy";
2837 #address-cells = <1>;
2838 #size-cells = <0>;
2851 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>;
2859 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
2868 clock-names = "cfg_noc",
2875 power-domains = <&gcc USB30_SEC_GDSC>;
2877 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2882 interrupt-names = "pwr_event",
2888 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
2890 assigned-clock-rates = <19200000>, <200000000>;
2894 interconnect-names = "usb-ddr", "apps-usb";
2896 #address-cells = <2>;
2897 #size-cells = <2>;
2899 dma-ranges;
2910 snps,dis-u1-entry-quirk;
2911 snps,dis-u2-entry-quirk;
2913 phy-names = "usb2-phy", "usb3-phy";
2916 #address-cells = <1>;
2917 #size-cells = <0>;
2930 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>;
2938 compatible = "qcom,sc8180x-mdss";
2940 reg-names = "mdss";
2942 power-domains = <&dispcc MDSS_GDSC>;
2948 clock-names = "iface",
2956 interrupt-controller;
2957 #interrupt-cells = <1>;
2965 interconnect-names = "mdp0-mem",
2966 "mdp1-mem",
2967 "cpu-cfg";
2971 #address-cells = <2>;
2972 #size-cells = <2>;
2978 compatible = "qcom,sc8180x-dpu";
2981 reg-names = "mdp", "vbif";
2989 clock-names = "iface",
2996 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2997 assigned-clock-rates = <19200000>;
2999 operating-points-v2 = <&mdp_opp_table>;
3000 power-domains = <&rpmhpd SC8180X_MMCX>;
3002 interrupt-parent = <&mdss>;
3006 #address-cells = <1>;
3007 #size-cells = <0>;
3012 remote-endpoint = <&dp0_in>;
3019 remote-endpoint = <&mdss_dsi0_in>;
3026 remote-endpoint = <&mdss_dsi1_in>;
3033 remote-endpoint = <&dp1_in>;
3040 remote-endpoint = <&edp_in>;
3045 mdp_opp_table: opp-table {
3046 compatible = "operating-points-v2";
3048 opp-200000000 {
3049 opp-hz = /bits/ 64 <200000000>;
3050 required-opps = <&rpmhpd_opp_low_svs>;
3053 opp-300000000 {
3054 opp-hz = /bits/ 64 <300000000>;
3055 required-opps = <&rpmhpd_opp_svs>;
3058 opp-345000000 {
3059 opp-hz = /bits/ 64 <345000000>;
3060 required-opps = <&rpmhpd_opp_svs_l1>;
3063 opp-460000000 {
3064 opp-hz = /bits/ 64 <460000000>;
3065 required-opps = <&rpmhpd_opp_nom>;
3071 compatible = "qcom,mdss-dsi-ctrl";
3073 reg-names = "dsi_ctrl";
3075 interrupt-parent = <&mdss>;
3084 clock-names = "byte",
3091 operating-points-v2 = <&dsi_opp_table>;
3092 power-domains = <&rpmhpd SC8180X_MMCX>;
3095 phy-names = "dsi";
3100 #address-cells = <1>;
3101 #size-cells = <0>;
3106 remote-endpoint = <&dpu_intf1_out>;
3117 dsi_opp_table: opp-table {
3118 compatible = "operating-points-v2";
3120 opp-187500000 {
3121 opp-hz = /bits/ 64 <187500000>;
3122 required-opps = <&rpmhpd_opp_low_svs>;
3125 opp-300000000 {
3126 opp-hz = /bits/ 64 <300000000>;
3127 required-opps = <&rpmhpd_opp_svs>;
3130 opp-358000000 {
3131 opp-hz = /bits/ 64 <358000000>;
3132 required-opps = <&rpmhpd_opp_svs_l1>;
3137 mdss_dsi0_phy: dsi-phy@ae94400 {
3138 compatible = "qcom,dsi-phy-7nm";
3142 reg-names = "dsi_phy",
3146 #clock-cells = <1>;
3147 #phy-cells = <0>;
3151 clock-names = "iface", "ref";
3157 compatible = "qcom,mdss-dsi-ctrl";
3159 reg-names = "dsi_ctrl";
3161 interrupt-parent = <&mdss>;
3170 clock-names = "byte",
3177 operating-points-v2 = <&dsi_opp_table>;
3178 power-domains = <&rpmhpd SC8180X_MMCX>;
3181 phy-names = "dsi";
3186 #address-cells = <1>;
3187 #size-cells = <0>;
3192 remote-endpoint = <&dpu_intf2_out>;
3204 mdss_dsi1_phy: dsi-phy@ae96400 {
3205 compatible = "qcom,dsi-phy-7nm";
3209 reg-names = "dsi_phy",
3213 #clock-cells = <1>;
3214 #phy-cells = <0>;
3218 clock-names = "iface", "ref";
3223 mdss_dp0: displayport-controller@ae90000 {
3224 compatible = "qcom,sc8180x-dp";
3230 interrupt-parent = <&mdss>;
3237 clock-names = "core_iface",
3243 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3245 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3249 phy-names = "dp";
3251 #sound-dai-cells = <0>;
3253 operating-points-v2 = <&dp0_opp_table>;
3254 power-domains = <&rpmhpd SC8180X_MMCX>;
3259 #address-cells = <1>;
3260 #size-cells = <0>;
3265 remote-endpoint = <&dpu_intf0_out>;
3276 dp0_opp_table: opp-table {
3277 compatible = "operating-points-v2";
3279 opp-160000000 {
3280 opp-hz = /bits/ 64 <160000000>;
3281 required-opps = <&rpmhpd_opp_low_svs>;
3284 opp-270000000 {
3285 opp-hz = /bits/ 64 <270000000>;
3286 required-opps = <&rpmhpd_opp_svs>;
3289 opp-540000000 {
3290 opp-hz = /bits/ 64 <540000000>;
3291 required-opps = <&rpmhpd_opp_svs_l1>;
3294 opp-810000000 {
3295 opp-hz = /bits/ 64 <810000000>;
3296 required-opps = <&rpmhpd_opp_nom>;
3301 mdss_dp1: displayport-controller@ae98000 {
3302 compatible = "qcom,sc8180x-dp";
3308 interrupt-parent = <&mdss>;
3315 clock-names = "core_iface",
3321 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
3323 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3327 phy-names = "dp";
3329 #sound-dai-cells = <0>;
3331 operating-points-v2 = <&dp0_opp_table>;
3332 power-domains = <&rpmhpd SC8180X_MMCX>;
3337 #address-cells = <1>;
3338 #size-cells = <0>;
3343 remote-endpoint = <&dpu_intf4_out>;
3354 dp1_opp_table: opp-table {
3355 compatible = "operating-points-v2";
3357 opp-160000000 {
3358 opp-hz = /bits/ 64 <160000000>;
3359 required-opps = <&rpmhpd_opp_low_svs>;
3362 opp-270000000 {
3363 opp-hz = /bits/ 64 <270000000>;
3364 required-opps = <&rpmhpd_opp_svs>;
3367 opp-540000000 {
3368 opp-hz = /bits/ 64 <540000000>;
3369 required-opps = <&rpmhpd_opp_svs_l1>;
3372 opp-810000000 {
3373 opp-hz = /bits/ 64 <810000000>;
3374 required-opps = <&rpmhpd_opp_nom>;
3379 mdss_edp: displayport-controller@ae9a000 {
3380 compatible = "qcom,sc8180x-edp";
3385 interrupt-parent = <&mdss>;
3392 clock-names = "core_iface",
3398 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
3400 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
3403 phy-names = "dp";
3405 operating-points-v2 = <&edp_opp_table>;
3406 power-domains = <&rpmhpd SC8180X_MMCX>;
3411 #address-cells = <1>;
3412 #size-cells = <0>;
3417 remote-endpoint = <&dpu_intf5_out>;
3422 edp_opp_table: opp-table {
3423 compatible = "operating-points-v2";
3425 opp-160000000 {
3426 opp-hz = /bits/ 64 <160000000>;
3427 required-opps = <&rpmhpd_opp_low_svs>;
3430 opp-270000000 {
3431 opp-hz = /bits/ 64 <270000000>;
3432 required-opps = <&rpmhpd_opp_svs>;
3435 opp-540000000 {
3436 opp-hz = /bits/ 64 <540000000>;
3437 required-opps = <&rpmhpd_opp_svs_l1>;
3440 opp-810000000 {
3441 opp-hz = /bits/ 64 <810000000>;
3442 required-opps = <&rpmhpd_opp_nom>;
3449 compatible = "qcom,sc8180x-edp-phy";
3457 clock-names = "aux", "cfg_ahb";
3459 power-domains = <&rpmhpd SC8180X_MX>;
3461 #clock-cells = <1>;
3462 #phy-cells = <0>;
3465 dispcc: clock-controller@af00000 {
3466 compatible = "qcom,sc8180x-dispcc";
3479 clock-names = "bi_tcxo",
3490 power-domains = <&rpmhpd SC8180X_MMCX>;
3491 required-opps = <&rpmhpd_opp_low_svs>;
3492 #clock-cells = <1>;
3493 #reset-cells = <1>;
3494 #power-domain-cells = <1>;
3497 pdc: interrupt-controller@b220000 {
3498 compatible = "qcom,sc8180x-pdc", "qcom,pdc";
3500 qcom,pdc-ranges = <0 480 94>, <94 609 31>;
3501 #interrupt-cells = <2>;
3502 interrupt-parent = <&intc>;
3503 interrupt-controller;
3506 tsens0: thermal-sensor@c263000 {
3507 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3513 interrupt-names = "uplow", "critical";
3514 #thermal-sensor-cells = <1>;
3517 tsens1: thermal-sensor@c265000 {
3518 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2";
3524 interrupt-names = "uplow", "critical";
3525 #thermal-sensor-cells = <1>;
3528 aoss_qmp: power-management@c300000 {
3529 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp";
3534 #clock-cells = <0>;
3538 compatible = "qcom,rpmh-stats";
3543 compatible = "qcom,spmi-pmic-arb";
3549 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3550 interrupt-names = "periph_irq";
3554 #address-cells = <2>;
3555 #size-cells = <0>;
3556 interrupt-controller;
3557 #interrupt-cells = <4>;
3561 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
3563 #iommu-cells = <2>;
3564 #global-interrupts = <1>;
3672 dma-coherent;
3676 compatible = "qcom,sc8180x-adsp-pas";
3679 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3684 interrupt-names = "wdog", "fatal", "ready",
3685 "handover", "stop-ack";
3688 clock-names = "xo";
3690 power-domains = <&rpmhpd SC8180X_CX>;
3691 power-domain-names = "cx";
3695 qcom,smem-states = <&adsp_smp2p_out 0>;
3696 qcom,smem-state-names = "stop";
3700 remoteproc_adsp_glink: glink-edge {
3703 qcom,remote-pid = <2>;
3708 intc: interrupt-controller@17a00000 {
3709 compatible = "arm,gic-v3";
3710 interrupt-controller;
3711 #interrupt-cells = <3>;
3715 #redistributor-regions = <1>;
3716 redistributor-stride = <0 0x20000>;
3720 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared";
3722 #mbox-cells = <1>;
3726 compatible = "arm,armv7-timer-mem";
3729 #address-cells = <1>;
3730 #size-cells = <1>;
3736 frame-number = <0>;
3743 frame-number = <1>;
3750 frame-number = <2>;
3757 frame-number = <3>;
3764 frame-number = <4>;
3771 frame-number = <5>;
3778 frame-number = <6>;
3785 compatible = "qcom,rpmh-rsc";
3789 reg-names = "drv-0", "drv-1", "drv-2";
3793 qcom,tcs-offset = <0xd00>;
3794 qcom,drv-id = <2>;
3795 qcom,tcs-config = <ACTIVE_TCS 2>,
3800 power-domains = <&cluster_pd>;
3802 apps_bcm_voter: bcm-voter {
3803 compatible = "qcom,bcm-voter";
3806 rpmhcc: clock-controller {
3807 compatible = "qcom,sc8180x-rpmh-clk";
3808 #clock-cells = <1>;
3809 clock-names = "xo";
3813 rpmhpd: power-controller {
3814 compatible = "qcom,sc8180x-rpmhpd";
3815 #power-domain-cells = <1>;
3816 operating-points-v2 = <&rpmhpd_opp_table>;
3818 rpmhpd_opp_table: opp-table {
3819 compatible = "operating-points-v2";
3822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3834 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3842 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3850 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3854 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3858 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3865 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
3869 clock-names = "xo", "alternate";
3871 #interconnect-cells = <1>;
3875 compatible = "qcom,sc8180x-lmh";
3879 qcom,lmh-temp-arm-millicelsius = <65000>;
3880 qcom,lmh-temp-low-millicelsius = <94500>;
3881 qcom,lmh-temp-high-millicelsius = <95000>;
3882 interrupt-controller;
3883 #interrupt-cells = <1>;
3887 compatible = "qcom,sc8180x-lmh";
3891 qcom,lmh-temp-arm-millicelsius = <65000>;
3892 qcom,lmh-temp-low-millicelsius = <94500>;
3893 qcom,lmh-temp-high-millicelsius = <95000>;
3894 interrupt-controller;
3895 #interrupt-cells = <1>;
3899 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw";
3901 reg-names = "freq-domain0", "freq-domain1";
3904 clock-names = "xo", "alternate";
3906 #freq-domain-cells = <1>;
3907 #clock-cells = <1>;
3911 compatible = "qcom,wcn3990-wifi";
3913 reg-names = "membase";
3914 clock-names = "cxo_ref_clk_pin";
3929 qcom,msa-fixed-perm;
3934 thermal-zones {
3935 cpu0-thermal {
3936 polling-delay-passive = <250>;
3938 thermal-sensors = <&tsens0 1>;
3941 cpu-crit {
3949 cpu1-thermal {
3950 polling-delay-passive = <250>;
3952 thermal-sensors = <&tsens0 2>;
3955 cpu-crit {
3963 cpu2-thermal {
3964 polling-delay-passive = <250>;
3966 thermal-sensors = <&tsens0 3>;
3969 cpu-crit {
3977 cpu3-thermal {
3978 polling-delay-passive = <250>;
3980 thermal-sensors = <&tsens0 4>;
3983 cpu-crit {
3991 cpu4-top-thermal {
3992 polling-delay-passive = <250>;
3994 thermal-sensors = <&tsens0 7>;
3997 cpu-crit {
4005 cpu5-top-thermal {
4006 polling-delay-passive = <250>;
4008 thermal-sensors = <&tsens0 8>;
4011 cpu-crit {
4019 cpu6-top-thermal {
4020 polling-delay-passive = <250>;
4022 thermal-sensors = <&tsens0 9>;
4025 cpu-crit {
4033 cpu7-top-thermal {
4034 polling-delay-passive = <250>;
4036 thermal-sensors = <&tsens0 10>;
4039 cpu-crit {
4047 cpu4-bottom-thermal {
4048 polling-delay-passive = <250>;
4050 thermal-sensors = <&tsens0 11>;
4053 cpu-crit {
4061 cpu5-bottom-thermal {
4062 polling-delay-passive = <250>;
4064 thermal-sensors = <&tsens0 12>;
4067 cpu-crit {
4075 cpu6-bottom-thermal {
4076 polling-delay-passive = <250>;
4078 thermal-sensors = <&tsens0 13>;
4081 cpu-crit {
4089 cpu7-bottom-thermal {
4090 polling-delay-passive = <250>;
4092 thermal-sensors = <&tsens0 14>;
4095 cpu-crit {
4103 aoss0-thermal {
4104 polling-delay-passive = <250>;
4106 thermal-sensors = <&tsens0 0>;
4109 trip-point0 {
4117 cluster0-thermal {
4118 polling-delay-passive = <250>;
4120 thermal-sensors = <&tsens0 5>;
4123 cluster-crit {
4131 cluster1-thermal {
4132 polling-delay-passive = <250>;
4134 thermal-sensors = <&tsens0 6>;
4137 cluster-crit {
4145 gpu-top-thermal {
4146 polling-delay-passive = <250>;
4148 thermal-sensors = <&tsens0 15>;
4150 cooling-maps {
4153 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4158 gpu_top_alert0: trip-point0 {
4164 trip-point1 {
4170 trip-point2 {
4178 aoss1-thermal {
4179 polling-delay-passive = <250>;
4181 thermal-sensors = <&tsens1 0>;
4184 trip-point0 {
4192 wlan-thermal {
4193 polling-delay-passive = <250>;
4195 thermal-sensors = <&tsens1 1>;
4198 trip-point0 {
4206 video-thermal {
4207 polling-delay-passive = <250>;
4209 thermal-sensors = <&tsens1 2>;
4212 trip-point0 {
4220 mem-thermal {
4221 polling-delay-passive = <250>;
4223 thermal-sensors = <&tsens1 3>;
4226 trip-point0 {
4234 q6-hvx-thermal {
4235 polling-delay-passive = <250>;
4237 thermal-sensors = <&tsens1 4>;
4240 trip-point0 {
4248 camera-thermal {
4249 polling-delay-passive = <250>;
4251 thermal-sensors = <&tsens1 5>;
4254 trip-point0 {
4262 compute-thermal {
4263 polling-delay-passive = <250>;
4265 thermal-sensors = <&tsens1 6>;
4268 trip-point0 {
4276 mdm-dsp-thermal {
4277 polling-delay-passive = <250>;
4279 thermal-sensors = <&tsens1 7>;
4282 trip-point0 {
4290 npu-thermal {
4291 polling-delay-passive = <250>;
4293 thermal-sensors = <&tsens1 8>;
4296 trip-point0 {
4304 gpu-bottom-thermal {
4305 polling-delay-passive = <250>;
4307 thermal-sensors = <&tsens1 11>;
4309 cooling-maps {
4312 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4317 gpu_bottom_alert0: trip-point0 {
4323 trip-point1 {
4329 trip-point2 {
4339 compatible = "arm,armv8-timer";