Lines Matching +full:freq +full:- +full:table +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
21 #include <dt-bindings/power/qcom-rpmpd.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
25 interrupt-parent = <&intc>;
27 #address-cells = <2>;
28 #size-cells = <2>;
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
41 xo_board: xo-board {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <38400000>;
49 #address-cells = <2>;
50 #size-cells = <0>;
56 enable-method = "psci";
57 capacity-dmips-mhz = <610>;
58 dynamic-power-coefficient = <203>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 operating-points-v2 = <&cpu0_opp_table>;
63 power-domains = <&cpu_pd0>;
64 power-domain-names = "psci";
65 next-level-cache = <&l2_0>;
66 l2_0: l2-cache {
68 next-level-cache = <&l3_0>;
69 cache-level = <2>;
70 cache-unified;
71 l3_0: l3-cache {
73 cache-level = <3>;
74 cache-unified;
83 enable-method = "psci";
84 capacity-dmips-mhz = <610>;
85 dynamic-power-coefficient = <203>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 power-domains = <&cpu_pd1>;
91 power-domain-names = "psci";
92 next-level-cache = <&l2_100>;
93 l2_100: l2-cache {
95 cache-level = <2>;
96 cache-unified;
97 next-level-cache = <&l3_0>;
105 enable-method = "psci";
106 capacity-dmips-mhz = <610>;
107 dynamic-power-coefficient = <203>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
109 operating-points-v2 = <&cpu0_opp_table>;
112 power-domains = <&cpu_pd2>;
113 power-domain-names = "psci";
114 next-level-cache = <&l2_200>;
115 l2_200: l2-cache {
117 cache-level = <2>;
118 cache-unified;
119 next-level-cache = <&l3_0>;
127 enable-method = "psci";
128 capacity-dmips-mhz = <610>;
129 dynamic-power-coefficient = <203>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
131 operating-points-v2 = <&cpu0_opp_table>;
134 power-domains = <&cpu_pd3>;
135 power-domain-names = "psci";
136 next-level-cache = <&l2_300>;
137 l2_300: l2-cache {
139 cache-level = <2>;
140 cache-unified;
141 next-level-cache = <&l3_0>;
149 enable-method = "psci";
150 capacity-dmips-mhz = <610>;
151 dynamic-power-coefficient = <203>;
152 qcom,freq-domain = <&cpufreq_hw 0>;
153 operating-points-v2 = <&cpu0_opp_table>;
156 power-domains = <&cpu_pd4>;
157 power-domain-names = "psci";
158 next-level-cache = <&l2_400>;
159 l2_400: l2-cache {
161 cache-level = <2>;
162 cache-unified;
163 next-level-cache = <&l3_0>;
171 enable-method = "psci";
172 capacity-dmips-mhz = <610>;
173 dynamic-power-coefficient = <203>;
174 qcom,freq-domain = <&cpufreq_hw 0>;
175 operating-points-v2 = <&cpu0_opp_table>;
178 power-domains = <&cpu_pd5>;
179 power-domain-names = "psci";
180 next-level-cache = <&l2_500>;
181 l2_500: l2-cache {
183 cache-level = <2>;
184 cache-unified;
185 next-level-cache = <&l3_0>;
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
195 dynamic-power-coefficient = <393>;
196 qcom,freq-domain = <&cpufreq_hw 1>;
197 operating-points-v2 = <&cpu6_opp_table>;
200 power-domains = <&cpu_pd6>;
201 power-domain-names = "psci";
202 next-level-cache = <&l2_600>;
203 l2_600: l2-cache {
205 cache-level = <2>;
206 cache-unified;
207 next-level-cache = <&l3_0>;
215 enable-method = "psci";
216 capacity-dmips-mhz = <1024>;
217 dynamic-power-coefficient = <393>;
218 qcom,freq-domain = <&cpufreq_hw 1>;
219 operating-points-v2 = <&cpu6_opp_table>;
222 power-domains = <&cpu_pd7>;
223 power-domain-names = "psci";
224 next-level-cache = <&l2_700>;
225 l2_700: l2-cache {
227 cache-level = <2>;
228 cache-unified;
229 next-level-cache = <&l3_0>;
233 cpu-map {
269 idle-states {
270 entry-method = "psci";
272 little_cpu_sleep_0: cpu-sleep-0-0 {
273 compatible = "arm,idle-state";
274 idle-state-name = "little-rail-power-collapse";
275 arm,psci-suspend-param = <0x40000004>;
276 entry-latency-us = <702>;
277 exit-latency-us = <915>;
278 min-residency-us = <1617>;
279 local-timer-stop;
282 big_cpu_sleep_0: cpu-sleep-1-0 {
283 compatible = "arm,idle-state";
284 idle-state-name = "big-rail-power-collapse";
285 arm,psci-suspend-param = <0x40000004>;
286 entry-latency-us = <526>;
287 exit-latency-us = <1854>;
288 min-residency-us = <2380>;
289 local-timer-stop;
293 domain-idle-states {
294 cluster_sleep_0: cluster-sleep-0 {
295 compatible = "domain-idle-state";
296 arm,psci-suspend-param = <0x4100c244>;
297 entry-latency-us = <3263>;
298 exit-latency-us = <6562>;
299 min-residency-us = <9825>;
306 compatible = "qcom,scm-sdm670", "qcom,scm";
316 cpu0_opp_table: opp-table-cpu0 {
317 compatible = "operating-points-v2";
318 opp-shared;
320 cpu0_opp1: opp-300000000 {
321 opp-hz = /bits/ 64 <300000000>;
322 opp-peak-kBps = <400000 4800000>;
325 cpu0_opp2: opp-576000000 {
326 opp-hz = /bits/ 64 <576000000>;
327 opp-peak-kBps = <400000 4800000>;
330 cpu0_opp3: opp-748800000 {
331 opp-hz = /bits/ 64 <748800000>;
332 opp-peak-kBps = <1200000 4800000>;
335 cpu0_opp4: opp-998400000 {
336 opp-hz = /bits/ 64 <998400000>;
337 opp-peak-kBps = <1804000 8908800>;
340 cpu0_opp5: opp-1209600000 {
341 opp-hz = /bits/ 64 <1209600000>;
342 opp-peak-kBps = <2188000 8908800>;
345 cpu0_opp6: opp-1324800000 {
346 opp-hz = /bits/ 64 <1324800000>;
347 opp-peak-kBps = <2188000 13516800>;
350 cpu0_opp7: opp-1516800000 {
351 opp-hz = /bits/ 64 <1516800000>;
352 opp-peak-kBps = <3072000 15052800>;
355 cpu0_opp8: opp-1612800000 {
356 opp-hz = /bits/ 64 <1612800000>;
357 opp-peak-kBps = <3072000 22118400>;
360 cpu0_opp9: opp-1708800000 {
361 opp-hz = /bits/ 64 <1708800000>;
362 opp-peak-kBps = <4068000 23040000>;
366 cpu6_opp_table: opp-table-cpu6 {
367 compatible = "operating-points-v2";
368 opp-shared;
370 cpu6_opp1: opp-300000000 {
371 opp-hz = /bits/ 64 <300000000>;
372 opp-peak-kBps = <400000 4800000>;
375 cpu6_opp2: opp-652800000 {
376 opp-hz = /bits/ 64 <652800000>;
377 opp-peak-kBps = <400000 4800000>;
380 cpu6_opp3: opp-825600000 {
381 opp-hz = /bits/ 64 <825600000>;
382 opp-peak-kBps = <1200000 4800000>;
385 cpu6_opp4: opp-979200000 {
386 opp-hz = /bits/ 64 <979200000>;
387 opp-peak-kBps = <1200000 4800000>;
390 cpu6_opp5: opp-1132800000 {
391 opp-hz = /bits/ 64 <1132800000>;
392 opp-peak-kBps = <2188000 8908800>;
395 cpu6_opp6: opp-1363200000 {
396 opp-hz = /bits/ 64 <1363200000>;
397 opp-peak-kBps = <4068000 12902400>;
400 cpu6_opp7: opp-1536000000 {
401 opp-hz = /bits/ 64 <1536000000>;
402 opp-peak-kBps = <4068000 12902400>;
405 cpu6_opp8: opp-1747200000 {
406 opp-hz = /bits/ 64 <1747200000>;
407 opp-peak-kBps = <4068000 15052800>;
410 cpu6_opp9: opp-1843200000 {
411 opp-hz = /bits/ 64 <1843200000>;
412 opp-peak-kBps = <4068000 15052800>;
415 cpu6_opp10: opp-1996800000 {
416 opp-hz = /bits/ 64 <1996800000>;
417 opp-peak-kBps = <6220000 19046400>;
421 dsi_opp_table: opp-table-dsi {
422 compatible = "operating-points-v2";
424 opp-19200000 {
425 opp-hz = /bits/ 64 <19200000>;
426 required-opps = <&rpmhpd_opp_min_svs>;
429 opp-180000000 {
430 opp-hz = /bits/ 64 <180000000>;
431 required-opps = <&rpmhpd_opp_low_svs>;
434 opp-275000000 {
435 opp-hz = /bits/ 64 <275000000>;
436 required-opps = <&rpmhpd_opp_svs>;
439 opp-358000000 {
440 opp-hz = /bits/ 64 <358000000>;
441 required-opps = <&rpmhpd_opp_svs_l1>;
446 compatible = "arm,psci-1.0";
449 cpu_pd0: power-domain-cpu0 {
450 #power-domain-cells = <0>;
451 power-domains = <&cluster_pd>;
452 domain-idle-states = <&little_cpu_sleep_0>;
455 cpu_pd1: power-domain-cpu1 {
456 #power-domain-cells = <0>;
457 power-domains = <&cluster_pd>;
458 domain-idle-states = <&little_cpu_sleep_0>;
461 cpu_pd2: power-domain-cpu2 {
462 #power-domain-cells = <0>;
463 power-domains = <&cluster_pd>;
464 domain-idle-states = <&little_cpu_sleep_0>;
467 cpu_pd3: power-domain-cpu3 {
468 #power-domain-cells = <0>;
469 power-domains = <&cluster_pd>;
470 domain-idle-states = <&little_cpu_sleep_0>;
473 cpu_pd4: power-domain-cpu4 {
474 #power-domain-cells = <0>;
475 power-domains = <&cluster_pd>;
476 domain-idle-states = <&little_cpu_sleep_0>;
479 cpu_pd5: power-domain-cpu5 {
480 #power-domain-cells = <0>;
481 power-domains = <&cluster_pd>;
482 domain-idle-states = <&little_cpu_sleep_0>;
485 cpu_pd6: power-domain-cpu6 {
486 #power-domain-cells = <0>;
487 power-domains = <&cluster_pd>;
488 domain-idle-states = <&big_cpu_sleep_0>;
491 cpu_pd7: power-domain-cpu7 {
492 #power-domain-cells = <0>;
493 power-domains = <&cluster_pd>;
494 domain-idle-states = <&big_cpu_sleep_0>;
497 cluster_pd: power-domain-cluster {
498 #power-domain-cells = <0>;
499 domain-idle-states = <&cluster_sleep_0>;
503 reserved-memory {
504 #address-cells = <2>;
505 #size-cells = <2>;
508 hyp_mem: hyp-mem@85700000 {
510 no-map;
513 xbl_mem: xbl-mem@85e00000 {
515 no-map;
518 aop_mem: aop-mem@85fc0000 {
520 no-map;
523 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
524 compatible = "qcom,cmd-db";
526 no-map;
532 no-map;
538 no-map;
541 camera_mem: camera-mem@8ab00000 {
543 no-map;
548 no-map;
553 no-map;
556 wlan_msa_mem: wlan-msa@93300000 {
558 no-map;
563 no-map;
568 no-map;
573 no-map;
576 ipa_fw_mem: ipa-fw@95c00000 {
578 no-map;
581 ipa_gsi_mem: ipa-gsi@95c10000 {
583 no-map;
588 no-map;
593 no-map;
598 no-map;
603 compatible = "arm,armv8-timer";
611 #address-cells = <2>;
612 #size-cells = <2>;
614 dma-ranges = <0 0 0 0 0x10 0>;
615 compatible = "simple-bus";
617 gcc: clock-controller@100000 {
618 compatible = "qcom,gcc-sdm670";
623 clock-names = "bi_tcxo",
626 #clock-cells = <1>;
627 #reset-cells = <1>;
628 #power-domain-cells = <1>;
632 compatible = "qcom,sdm670-qfprom", "qcom,qfprom";
634 #address-cells = <1>;
635 #size-cells = <1>;
642 qusb2_hstx_trim: hstx-trim@1eb {
649 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5";
653 reg-names = "hc", "cqhci", "ice";
657 interrupt-names = "hc_irq", "pwr_irq";
664 clock-names = "iface", "core", "xo", "ice", "bus";
667 interconnect-names = "sdhc-ddr", "cpu-sdhc";
668 operating-points-v2 = <&sdhc1_opp_table>;
672 pinctrl-names = "default", "sleep";
673 pinctrl-0 = <&sdc1_state_on>;
674 pinctrl-1 = <&sdc1_state_off>;
675 power-domains = <&rpmhpd SDM670_CX>;
677 bus-width = <8>;
678 non-removable;
682 sdhc1_opp_table: opp-table {
683 compatible = "operating-points-v2";
685 opp-20000000 {
686 opp-hz = /bits/ 64 <20000000>;
687 required-opps = <&rpmhpd_opp_min_svs>;
688 opp-peak-kBps = <80000 80000>;
689 opp-avg-kBps = <52286 80000>;
692 opp-50000000 {
693 opp-hz = /bits/ 64 <50000000>;
694 required-opps = <&rpmhpd_opp_low_svs>;
695 opp-peak-kBps = <200000 100000>;
696 opp-avg-kBps = <130718 100000>;
699 opp-100000000 {
700 opp-hz = /bits/ 64 <100000000>;
701 required-opps = <&rpmhpd_opp_svs>;
702 opp-peak-kBps = <200000 130000>;
703 opp-avg-kBps = <130718 130000>;
706 opp-384000000 {
707 opp-hz = /bits/ 64 <384000000>;
708 required-opps = <&rpmhpd_opp_nom>;
709 opp-peak-kBps = <4096000 4096000>;
710 opp-avg-kBps = <1338562 1338562>;
715 gpi_dma0: dma-controller@800000 {
716 #dma-cells = <3>;
717 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
732 dma-channels = <13>;
733 dma-channel-mask = <0xfa>;
739 compatible = "qcom,geni-se-qup";
741 clock-names = "m-ahb", "s-ahb";
745 #address-cells = <2>;
746 #size-cells = <2>;
749 interconnect-names = "qup-core";
753 compatible = "qcom,geni-i2c";
755 clock-names = "se";
757 pinctrl-names = "default";
758 pinctrl-0 = <&qup_i2c0_default>;
760 #address-cells = <1>;
761 #size-cells = <0>;
762 power-domains = <&rpmhpd SDM670_CX>;
766 interconnect-names = "qup-core", "qup-config", "qup-memory";
769 dma-names = "tx", "rx";
774 compatible = "qcom,geni-i2c";
776 clock-names = "se";
778 pinctrl-names = "default";
779 pinctrl-0 = <&qup_i2c1_default>;
781 #address-cells = <1>;
782 #size-cells = <0>;
783 power-domains = <&rpmhpd SDM670_CX>;
787 interconnect-names = "qup-core", "qup-config", "qup-memory";
790 dma-names = "tx", "rx";
795 compatible = "qcom,geni-i2c";
797 clock-names = "se";
799 pinctrl-names = "default";
800 pinctrl-0 = <&qup_i2c2_default>;
802 #address-cells = <1>;
803 #size-cells = <0>;
804 power-domains = <&rpmhpd SDM670_CX>;
808 interconnect-names = "qup-core", "qup-config", "qup-memory";
811 dma-names = "tx", "rx";
816 compatible = "qcom,geni-i2c";
818 clock-names = "se";
820 pinctrl-names = "default";
821 pinctrl-0 = <&qup_i2c3_default>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 power-domains = <&rpmhpd SDM670_CX>;
829 interconnect-names = "qup-core", "qup-config", "qup-memory";
832 dma-names = "tx", "rx";
837 compatible = "qcom,geni-i2c";
839 clock-names = "se";
841 pinctrl-names = "default";
842 pinctrl-0 = <&qup_i2c4_default>;
844 #address-cells = <1>;
845 #size-cells = <0>;
846 power-domains = <&rpmhpd SDM670_CX>;
850 interconnect-names = "qup-core", "qup-config", "qup-memory";
853 dma-names = "tx", "rx";
858 compatible = "qcom,geni-i2c";
860 clock-names = "se";
862 pinctrl-names = "default";
863 pinctrl-0 = <&qup_i2c5_default>;
865 #address-cells = <1>;
866 #size-cells = <0>;
867 power-domains = <&rpmhpd SDM670_CX>;
871 interconnect-names = "qup-core", "qup-config", "qup-memory";
874 dma-names = "tx", "rx";
879 compatible = "qcom,geni-i2c";
881 clock-names = "se";
883 pinctrl-names = "default";
884 pinctrl-0 = <&qup_i2c6_default>;
886 #address-cells = <1>;
887 #size-cells = <0>;
888 power-domains = <&rpmhpd SDM670_CX>;
892 interconnect-names = "qup-core", "qup-config", "qup-memory";
895 dma-names = "tx", "rx";
900 compatible = "qcom,geni-i2c";
902 clock-names = "se";
904 pinctrl-names = "default";
905 pinctrl-0 = <&qup_i2c7_default>;
907 #address-cells = <1>;
908 #size-cells = <0>;
909 power-domains = <&rpmhpd SDM670_CX>;
913 interconnect-names = "qup-core", "qup-config", "qup-memory";
916 dma-names = "tx", "rx";
921 gpi_dma1: dma-controller@a00000 {
922 #dma-cells = <3>;
923 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma";
938 dma-channels = <13>;
939 dma-channel-mask = <0xfa>;
945 compatible = "qcom,geni-se-qup";
947 clock-names = "m-ahb", "s-ahb";
951 #address-cells = <2>;
952 #size-cells = <2>;
955 interconnect-names = "qup-core";
959 compatible = "qcom,geni-i2c";
961 clock-names = "se";
963 pinctrl-names = "default";
964 pinctrl-0 = <&qup_i2c8_default>;
966 #address-cells = <1>;
967 #size-cells = <0>;
968 power-domains = <&rpmhpd SDM670_CX>;
972 interconnect-names = "qup-core", "qup-config", "qup-memory";
975 dma-names = "tx", "rx";
980 compatible = "qcom,geni-i2c";
982 clock-names = "se";
984 pinctrl-names = "default";
985 pinctrl-0 = <&qup_i2c9_default>;
987 #address-cells = <1>;
988 #size-cells = <0>;
989 power-domains = <&rpmhpd SDM670_CX>;
993 interconnect-names = "qup-core", "qup-config", "qup-memory";
996 dma-names = "tx", "rx";
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c10_default>;
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1010 power-domains = <&rpmhpd SDM670_CX>;
1014 interconnect-names = "qup-core", "qup-config", "qup-memory";
1017 dma-names = "tx", "rx";
1022 compatible = "qcom,geni-i2c";
1024 clock-names = "se";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&qup_i2c11_default>;
1029 #address-cells = <1>;
1030 #size-cells = <0>;
1031 power-domains = <&rpmhpd SDM670_CX>;
1035 interconnect-names = "qup-core", "qup-config", "qup-memory";
1038 dma-names = "tx", "rx";
1043 compatible = "qcom,geni-i2c";
1045 clock-names = "se";
1047 pinctrl-names = "default";
1048 pinctrl-0 = <&qup_i2c12_default>;
1050 #address-cells = <1>;
1051 #size-cells = <0>;
1052 power-domains = <&rpmhpd SDM670_CX>;
1056 interconnect-names = "qup-core", "qup-config", "qup-memory";
1059 dma-names = "tx", "rx";
1064 compatible = "qcom,geni-i2c";
1066 clock-names = "se";
1068 pinctrl-names = "default";
1069 pinctrl-0 = <&qup_i2c13_default>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 power-domains = <&rpmhpd SDM670_CX>;
1077 interconnect-names = "qup-core", "qup-config", "qup-memory";
1080 dma-names = "tx", "rx";
1085 compatible = "qcom,geni-i2c";
1087 clock-names = "se";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&qup_i2c14_default>;
1092 #address-cells = <1>;
1093 #size-cells = <0>;
1094 power-domains = <&rpmhpd SDM670_CX>;
1098 interconnect-names = "qup-core", "qup-config", "qup-memory";
1101 dma-names = "tx", "rx";
1106 compatible = "qcom,geni-i2c";
1108 clock-names = "se";
1110 pinctrl-names = "default";
1111 pinctrl-0 = <&qup_i2c15_default>;
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1115 power-domains = <&rpmhpd SDM670_CX>;
1119 interconnect-names = "qup-core", "qup-config", "qup-memory";
1122 dma-names = "tx", "rx";
1128 compatible = "qcom,sdm670-mem-noc";
1130 #interconnect-cells = <2>;
1131 qcom,bcm-voters = <&apps_bcm_voter>;
1135 compatible = "qcom,sdm670-dc-noc";
1137 #interconnect-cells = <2>;
1138 qcom,bcm-voters = <&apps_bcm_voter>;
1142 compatible = "qcom,sdm670-config-noc";
1144 #interconnect-cells = <2>;
1145 qcom,bcm-voters = <&apps_bcm_voter>;
1149 compatible = "qcom,sdm670-system-noc";
1151 #interconnect-cells = <2>;
1152 qcom,bcm-voters = <&apps_bcm_voter>;
1156 compatible = "qcom,sdm670-aggre1-noc";
1158 #interconnect-cells = <2>;
1159 qcom,bcm-voters = <&apps_bcm_voter>;
1163 compatible = "qcom,sdm670-aggre2-noc";
1165 #interconnect-cells = <2>;
1166 qcom,bcm-voters = <&apps_bcm_voter>;
1170 compatible = "qcom,sdm670-mmss-noc";
1172 #interconnect-cells = <2>;
1173 qcom,bcm-voters = <&apps_bcm_voter>;
1177 compatible = "qcom,tcsr-mutex";
1179 #hwlock-cells = <1>;
1183 compatible = "qcom,sdm670-tlmm";
1186 gpio-controller;
1187 #gpio-cells = <2>;
1188 interrupt-controller;
1189 #interrupt-cells = <2>;
1190 gpio-ranges = <&tlmm 0 0 151>;
1191 wakeup-parent = <&pdc>;
1193 cci0_default: cci0-default-state {
1196 drive-strength = <2>;
1197 bias-pull-up;
1200 cci0_sleep: cci0-sleep-state {
1203 drive-strength = <2>;
1204 bias-pull-down;
1207 cci1_default: cci1-default-state {
1210 drive-strength = <2>;
1211 bias-pull-up;
1214 cci1_sleep: cci1-sleep-state {
1217 drive-strength = <2>;
1218 bias-pull-down;
1221 qup_i2c0_default: qup-i2c0-default-state {
1226 qup_i2c1_default: qup-i2c1-default-state {
1231 qup_i2c2_default: qup-i2c2-default-state {
1236 qup_i2c3_default: qup-i2c3-default-state {
1241 qup_i2c4_default: qup-i2c4-default-state {
1246 qup_i2c5_default: qup-i2c5-default-state {
1251 qup_i2c6_default: qup-i2c6-default-state {
1256 qup_i2c7_default: qup-i2c7-default-state {
1261 qup_i2c8_default: qup-i2c8-default-state {
1266 qup_i2c9_default: qup-i2c9-default-state {
1271 qup_i2c10_default: qup-i2c10-default-state {
1276 qup_i2c11_default: qup-i2c11-default-state {
1281 qup_i2c12_default: qup-i2c12-default-state {
1286 qup_i2c13_default: qup-i2c13-default-state {
1291 qup_i2c14_default: qup-i2c14-default-state {
1296 qup_i2c15_default: qup-i2c15-default-state {
1301 sdc1_state_on: sdc1-on-state {
1302 clk-pins {
1304 bias-disable;
1305 drive-strength = <16>;
1308 cmd-pins {
1310 bias-pull-up;
1311 drive-strength = <10>;
1314 data-pins {
1316 bias-pull-up;
1317 drive-strength = <10>;
1320 rclk-pins {
1322 bias-pull-down;
1326 sdc1_state_off: sdc1-off-state {
1327 clk-pins {
1329 bias-disable;
1330 drive-strength = <2>;
1333 cmd-pins {
1335 bias-pull-up;
1336 drive-strength = <2>;
1339 data-pins {
1341 bias-pull-up;
1342 drive-strength = <2>;
1345 rclk-pins {
1347 bias-pull-down;
1353 compatible = "qcom,adreno-615.0", "qcom,adreno";
1356 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
1367 operating-points-v2 = <&gpu_opp_table>;
1372 interconnect-names = "gfx-mem";
1374 nvmem-cells = <&gpu_speed_bin>;
1375 nvmem-cell-names = "speed_bin";
1379 gpu_opp_table: opp-table {
1380 compatible = "operating-points-v2";
1382 opp-780000000 {
1383 opp-hz = /bits/ 64 <780000000>;
1384 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1385 opp-peak-kBps = <7216000>;
1386 opp-supported-hw = <0x8>;
1389 opp-750000000 {
1390 opp-hz = /bits/ 64 <750000000>;
1391 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1392 opp-peak-kBps = <7216000>;
1393 opp-supported-hw = <0x8>;
1396 opp-700000000 {
1397 opp-hz = /bits/ 64 <700000000>;
1398 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1399 opp-peak-kBps = <7216000>;
1400 opp-supported-hw = <0x4>;
1403 opp-650000000 {
1404 opp-hz = /bits/ 64 <650000000>;
1405 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1406 opp-peak-kBps = <7216000>;
1407 opp-supported-hw = <0xc>;
1410 opp-565000000 {
1411 opp-hz = /bits/ 64 <565000000>;
1412 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1413 opp-peak-kBps = <7216000>;
1414 opp-supported-hw = <0xc>;
1417 opp-504000000 {
1418 opp-hz = /bits/ 64 <504000000>;
1419 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1420 opp-peak-kBps = <7216000>;
1421 opp-supported-hw = <0x2>;
1424 opp-430000000 {
1425 opp-hz = /bits/ 64 <430000000>;
1426 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1427 opp-peak-kBps = <7216000>;
1428 opp-supported-hw = <0xf>;
1431 opp-355000000 {
1432 opp-hz = /bits/ 64 <355000000>;
1433 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1434 opp-peak-kBps = <6220000>;
1435 opp-supported-hw = <0xf>;
1438 opp-267000000 {
1439 opp-hz = /bits/ 64 <267000000>;
1440 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1441 opp-peak-kBps = <4068000>;
1442 opp-supported-hw = <0xf>;
1445 opp-180000000 {
1446 opp-hz = /bits/ 64 <180000000>;
1447 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1448 opp-peak-kBps = <1804000>;
1449 opp-supported-hw = <0xf>;
1455 compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
1457 #iommu-cells = <1>;
1458 #global-interrupts = <2>;
1471 clock-names = "bus", "iface";
1473 power-domains = <&gpucc GPU_CX_GDSC>;
1477 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu";
1482 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1486 interrupt-names = "hfi", "gmu";
1492 clock-names = "gmu", "cxo", "axi", "memnoc";
1494 power-domains = <&gpucc GPU_CX_GDSC>,
1496 power-domain-names = "cx", "gx";
1500 operating-points-v2 = <&gmu_opp_table>;
1502 gmu_opp_table: opp-table {
1503 compatible = "operating-points-v2";
1505 opp-200000000 {
1506 opp-hz = /bits/ 64 <200000000>;
1507 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1512 gpucc: clock-controller@5090000 {
1513 compatible = "qcom,sdm845-gpucc";
1515 #clock-cells = <1>;
1516 #reset-cells = <1>;
1517 #power-domain-cells = <1>;
1521 clock-names = "bi_tcxo",
1527 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy";
1529 #phy-cells = <0>;
1533 clock-names = "cfg_ahb", "ref";
1537 nvmem-cells = <&qusb2_hstx_trim>;
1543 compatible = "qcom,sdm670-dwc3", "qcom,dwc3";
1545 #address-cells = <2>;
1546 #size-cells = <2>;
1548 dma-ranges;
1555 clock-names = "cfg_noc",
1561 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1563 assigned-clock-rates = <19200000>, <150000000>;
1565 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1570 interrupt-names = "pwr_event",
1576 power-domains = <&gcc USB30_PRIM_GDSC>;
1582 interconnect-names = "usb-ddr", "apps-usb";
1594 phy-names = "usb2-phy";
1598 pdc: interrupt-controller@b220000 {
1599 compatible = "qcom,sdm670-pdc", "qcom,pdc";
1601 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1604 #interrupt-cells = <2>;
1605 interrupt-parent = <&intc>;
1606 interrupt-controller;
1610 compatible = "qcom,spmi-pmic-arb";
1616 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1617 interrupt-names = "periph_irq";
1621 #address-cells = <2>;
1622 #size-cells = <0>;
1623 interrupt-controller;
1624 #interrupt-cells = <4>;
1628 compatible = "qcom,sdm670-cci", "qcom,msm8996-cci";
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1634 power-domains = <&camcc TITAN_TOP_GDSC>;
1640 clock-names = "camnoc_axi",
1645 pinctrl-names = "default", "sleep";
1646 pinctrl-0 = <&cci0_default &cci1_default>;
1647 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
1651 cci_i2c0: i2c-bus@0 {
1653 clock-frequency = <1000000>;
1654 #address-cells = <1>;
1655 #size-cells = <0>;
1658 cci_i2c1: i2c-bus@1 {
1660 clock-frequency = <1000000>;
1661 #address-cells = <1>;
1662 #size-cells = <0>;
1667 compatible = "qcom,sdm670-camss";
1677 reg-names = "csid0",
1696 interrupt-names = "csid0",
1728 clock-names = "camnoc_axi",
1756 power-domains = <&camcc IFE_0_GDSC>,
1759 power-domain-names = "ife0",
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1795 camcc: clock-controller@ad00000 {
1796 compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc";
1799 clock-names = "bi_tcxo";
1800 #clock-cells = <1>;
1801 #reset-cells = <1>;
1802 #power-domain-cells = <1>;
1805 mdss: display-subsystem@ae00000 {
1806 compatible = "qcom,sdm670-mdss";
1808 reg-names = "mdss";
1810 power-domains = <&dispcc MDSS_GDSC>;
1814 clock-names = "iface", "core";
1817 interrupt-controller;
1818 #interrupt-cells = <1>;
1822 interconnect-names = "mdp0-mem", "mdp1-mem";
1827 #address-cells = <2>;
1828 #size-cells = <2>;
1833 mdss_mdp: display-controller@ae01000 {
1834 compatible = "qcom,sdm670-dpu";
1837 reg-names = "mdp", "vbif";
1844 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
1846 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1847 assigned-clock-rates = <19200000>;
1848 operating-points-v2 = <&mdp_opp_table>;
1849 power-domains = <&rpmhpd SDM670_CX>;
1851 interrupt-parent = <&mdss>;
1855 #address-cells = <1>;
1856 #size-cells = <0>;
1861 remote-endpoint = <&mdss_dsi0_in>;
1868 remote-endpoint = <&mdss_dsi1_in>;
1873 mdp_opp_table: opp-table {
1874 compatible = "operating-points-v2";
1876 opp-19200000 {
1877 opp-hz = /bits/ 64 <19200000>;
1878 required-opps = <&rpmhpd_opp_min_svs>;
1881 opp-171428571 {
1882 opp-hz = /bits/ 64 <171428571>;
1883 required-opps = <&rpmhpd_opp_low_svs>;
1886 opp-358000000 {
1887 opp-hz = /bits/ 64 <358000000>;
1888 required-opps = <&rpmhpd_opp_svs_l1>;
1891 opp-430000000 {
1892 opp-hz = /bits/ 64 <430000000>;
1893 required-opps = <&rpmhpd_opp_nom>;
1899 compatible = "qcom,sdm670-dsi-ctrl",
1900 "qcom,mdss-dsi-ctrl";
1902 reg-names = "dsi_ctrl";
1904 interrupt-parent = <&mdss>;
1913 clock-names = "byte",
1919 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1921 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1924 operating-points-v2 = <&dsi_opp_table>;
1925 power-domains = <&rpmhpd SDM670_CX>;
1929 #address-cells = <1>;
1930 #size-cells = <0>;
1935 #address-cells = <1>;
1936 #size-cells = <0>;
1941 remote-endpoint = <&dpu_intf0_out>;
1954 compatible = "qcom,dsi-phy-10nm";
1958 reg-names = "dsi_phy",
1962 #clock-cells = <1>;
1963 #phy-cells = <0>;
1967 clock-names = "iface", "ref";
1973 compatible = "qcom,sdm670-dsi-ctrl",
1974 "qcom,mdss-dsi-ctrl";
1976 reg-names = "dsi_ctrl";
1978 interrupt-parent = <&mdss>;
1987 clock-names = "byte",
1993 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
1995 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
1998 operating-points-v2 = <&dsi_opp_table>;
1999 power-domains = <&rpmhpd SDM670_CX>;
2003 #address-cells = <1>;
2004 #size-cells = <0>;
2009 #address-cells = <1>;
2010 #size-cells = <0>;
2015 remote-endpoint = <&dpu_intf1_out>;
2028 compatible = "qcom,dsi-phy-10nm";
2032 reg-names = "dsi_phy",
2036 #clock-cells = <1>;
2037 #phy-cells = <0>;
2041 clock-names = "iface", "ref";
2047 dispcc: clock-controller@af00000 {
2048 compatible = "qcom,sdm845-dispcc";
2059 clock-names = "bi_tcxo",
2068 #clock-cells = <1>;
2069 #reset-cells = <1>;
2070 #power-domain-cells = <1>;
2074 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2076 #iommu-cells = <2>;
2077 #global-interrupts = <1>;
2143 dma-coherent;
2147 compatible = "qcom,sdm670-gladiator-noc";
2149 #interconnect-cells = <2>;
2150 qcom,bcm-voters = <&apps_bcm_voter>;
2154 compatible = "qcom,rpmh-rsc";
2158 reg-names = "drv-0", "drv-1", "drv-2";
2163 qcom,tcs-offset = <0xd00>;
2164 qcom,drv-id = <2>;
2165 qcom,tcs-config = <ACTIVE_TCS 2>,
2169 power-domains = <&cluster_pd>;
2171 apps_bcm_voter: bcm-voter {
2172 compatible = "qcom,bcm-voter";
2175 rpmhcc: clock-controller {
2176 compatible = "qcom,sdm670-rpmh-clk";
2177 #clock-cells = <1>;
2178 clock-names = "xo";
2182 rpmhpd: power-controller {
2183 compatible = "qcom,sdm670-rpmhpd";
2184 #power-domain-cells = <1>;
2185 operating-points-v2 = <&rpmhpd_opp_table>;
2187 rpmhpd_opp_table: opp-table {
2188 compatible = "operating-points-v2";
2191 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
2195 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2199 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2203 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2207 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2211 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
2223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2233 intc: interrupt-controller@17a00000 {
2234 compatible = "arm,gic-v3";
2237 interrupt-controller;
2239 #interrupt-cells = <3>;
2243 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3";
2247 clock-names = "xo", "alternate";
2249 #interconnect-cells = <1>;
2253 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw";
2255 reg-names = "freq-domain0", "freq-domain1";
2258 clock-names = "xo", "alternate";
2260 #freq-domain-cells = <1>;