/linux/Documentation/devicetree/bindings/fpga/ |
H A D | fpga-region.yaml | 4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml# 7 title: FPGA Region 17 - FPGA Region 25 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in 26 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree 29 The documentation hits some of the high points of FPGA usage and 30 attempts to include terminology used by both major FPGA manufacturers. This 31 document isn't a replacement for any manufacturers specifications for FPGA 39 * The entire FPGA is programmed. 42 * A section of an FPGA is reprogrammed while the rest of the FPGA is not [all …]
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H A D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager 10 - reg: spi chip select of the FPGA 12 Example for full FPGA configuration: 14 fpga-region0 { 15 compatible = "fpga-region"; 16 fpga-mgr = <&fpga_mgr_spi>; 24 fpga_mgr_spi: fpga-mgr@0 {
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H A D | xlnx,versal-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml# 7 title: Xilinx Versal FPGA driver. 13 Device Tree Versal FPGA bindings for the Versal SoC, controlled 20 - xlnx,versal-fpga 29 versal_fpga: versal-fpga { 30 compatible = "xlnx,versal-fpga";
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H A D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager 4 - compatible : should contain "altr,socfpga-fpga-mgr" 6 - The first index is for FPGA manager register access. 7 - The second index is for writing FPGA configuration data. 8 - interrupts : interrupt for the FPGA Manager device. 13 compatible = "altr,socfpga-fpga-mgr";
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H A D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager 4 - compatible : should contain "altr,socfpga-a10-fpga-mgr" 6 - The first index is for FPGA manager register access. 7 - The second index is for writing FPGA configuration data. 13 fpga_mgr: fpga-mgr@ffd03000 { 14 compatible = "altr,socfpga-a10-fpga-mgr";
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/linux/Documentation/driver-api/fpga/ |
H A D | fpga-programming.rst | 1 In-kernel API for FPGA Programming 7 The in-kernel API for FPGA programming is a combination of APIs from 8 FPGA manager, bridge, and regions. The actual function used to 9 trigger FPGA programming is fpga_region_program_fpga(). 12 the FPGA manager and bridges. It will: 15 * lock the mutex of the region's FPGA manager 16 * build a list of FPGA bridges if a method has been specified to do so 18 * program the FPGA using info passed in :c:expr:`fpga_region->info`. 22 The struct fpga_image_info specifies what FPGA image to program. It is 26 How to program an FPGA using a region [all …]
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H A D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under 5 Linux. Some of the core intentions of the FPGA subsystems are: 7 * The FPGA subsystem is vendor agnostic. 9 * The FPGA subsystem separates upper layers (userspace interfaces and 11 FPGA. 16 other users. Write the linux-fpga mailing list and maintainers and 23 FPGA Manager 26 If you are adding a new FPGA or a new method of programming an FPGA, 27 this is the subsystem for you. Low level FPGA manager drivers contain 29 includes the framework in fpga-mgr.c and the low level drivers that [all …]
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-class-fpga-manager | 1 What: /sys/class/fpga_manager/<fpga>/name 5 Description: Name of low level fpga manager driver. 7 What: /sys/class/fpga_manager/<fpga>/state 11 Description: Read fpga manager state as a string. 13 wrong during FPGA programming (something that the driver can't 18 This is a superset of FPGA states and fpga manager driver 19 states. The fpga manager driver is walking through these steps 20 to get the FPGA into a known operating state. It's a sequence, 21 though some steps may get skipped. Valid FPGA states will vary 25 * power off = FPGA power is off [all …]
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/linux/Documentation/devicetree/bindings/board/ |
H A D | fsl,fpga-qixis.yaml | 4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml# 7 title: Freescale on-board FPGA/CPLD 16 - const: fsl,p1022ds-fpga 17 - const: fsl,fpga-ngpixis 20 - fsl,ls1088aqds-fpga 21 - fsl,ls1088ardb-fpga 22 - fsl,ls2080aqds-fpga 23 - fsl,ls2080ardb-fpga 24 - const: fsl,fpga-qixis 27 - fsl,ls1043aqds-fpga [all …]
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H A D | fsl,fpga-qixis-i2c.yaml | 4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml# 7 title: Freescale on-board FPGA connected on I2C bus 17 - fsl,bsc9132qds-fpga 18 - const: fsl,fpga-qixis-i2c 21 - fsl,ls1028aqds-fpga 22 - fsl,lx2160aqds-fpga 23 - const: fsl,fpga-qixis-i2c 48 compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c"; 59 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
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/linux/Documentation/driver-api/ |
H A D | xillybus.rst | 2 Xillybus driver for generic FPGA interface 22 -- Host never reads from the FPGA 37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which 48 level, even lower than assembly language. In order to allow FPGA designers to 51 FPGA parallels of library functions. IP cores may implement certain 57 One of the daunting tasks in FPGA design is communicating with a fullblown 60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's 62 make sense to design the FPGA's interface logic specifically for the project. 63 A special driver is then written to present the FPGA as a well-known interface 65 FPGA differently than any device on the bus. [all …]
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/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/ |
H A D | sdk.h | 42 * This header defines the in-kernel API for Innova FPGA client drivers. 51 * @MLX5_FPGA_ACCESS_TYPE_I2C: Use the slow CX-FPGA I2C bus 87 * @conn: FPGA Connection this packet was sent to 88 * @fdev: FPGA device this packet was sent to 98 * struct mlx5_fpga_conn_attr - FPGA connection attributes 122 * mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection 123 * @fdev: The FPGA device 126 * Sets up a new FPGA SBU connection with the specified attributes. 140 * mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection 141 * @conn: The FPGA SBU connection to destroy [all …]
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H A D | core.c | 39 #include "fpga/core.h" 40 #include "fpga/conn.h" 124 /* for FPGA lookaside projects FPGA load status is not important */ in mlx5_fpga_device_load_check() 179 struct mlx5_fpga_device *fdev = mdev->fpga; in mlx5_fpga_device_start() 197 mlx5_fpga_info(fdev, "FPGA card %s:%u\n", mlx5_fpga_name(fpga_id), fpga_id); in mlx5_fpga_device_start() 199 /* No QPs if FPGA does not participate in net processing */ in mlx5_fpga_device_start() 213 mlx5_fpga_err(fdev, "FPGA reports 0 QPs in SHELL_CAPS\n"); in mlx5_fpga_device_start() 257 if (!MLX5_CAP_GEN(mdev, fpga)) { in mlx5_fpga_init() 258 mlx5_core_dbg(mdev, "FPGA capability not present\n"); in mlx5_fpga_init() 262 mlx5_core_dbg(mdev, "Initializing FPGA\n"); in mlx5_fpga_init() [all …]
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/linux/drivers/watchdog/ |
H A D | pika_wdt.c | 3 * PIKA FPGA based Watchdog Timer 50 void __iomem *fpga; member 71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset() 80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset() 83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset() 228 void __iomem *fpga; in pikawdt_init() local 232 np = of_find_compatible_node(NULL, NULL, "pika,fpga"); in pikawdt_init() 234 pr_err("Unable to find fpga\n"); in pikawdt_init() 238 pikawdt_private.fpga = of_iomap(np, 0); in pikawdt_init() 240 if (pikawdt_private.fpga == NULL) { in pikawdt_init() [all …]
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/linux/drivers/hwmon/ |
H A D | intel-m10-bmc-hwmon.c | 40 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Die Temperature" }, 52 { 0x13c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" }, 61 { 0x140, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" }, 104 { 0x110, 0x114, 0x118, 0x0, 0x0, 500, "FPGA Core Temperature" }, 106 { 0x12c, 0x130, 0x134, 0x0, 0x0, 500, "FPGA Transceiver Temperature" }, 125 { 0x198, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Voltage" }, 136 { 0x19c, 0x0, 0x0, 0x0, 0x0, 1, "FPGA Core Current" }, 233 { 0x108, 0x0, 0x10c, 0x0, 0x0, 1000, "FPGA 1 Temperature" }, 234 { 0x110, 0x0, 0x114, 0x0, 0x0, 1000, "FPGA 2 Temperature" }, 237 { 0x128, 0x0, 0x0, 0x0, 0x0, 1000, "FPGA 1.2V Temperature" }, [all …]
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/linux/Documentation/fpga/ |
H A D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview 12 The Device Feature List (DFL) FPGA framework (and drivers according to 15 configure, enumerate, open and access FPGA accelerators on platforms which 17 enables system level management functions such as FPGA reconfiguration. 24 walk through these predefined data structures to enumerate FPGA features: 25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features, 56 FPGA Interface Unit (FIU) represents a standalone functional unit for the 57 interface to FPGA, e.g. the FPGA Management Engine (FME) and Port (more 60 Accelerated Function Unit (AFU) represents an FPGA programmable region and 75 and can be implemented in register regions of any FPGA device. [all …]
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/linux/drivers/fpga/tests/ |
H A D | fpga-region-test.c | 3 * KUnit test for the FPGA Region 12 #include <linux/fpga/fpga-bridge.h> 13 #include <linux/fpga/fpga-mgr.h> 14 #include <linux/fpga/fpga-region.h> 61 * Fake FPGA manager that implements only the write op to count the number 83 * Fake FPGA bridge that implements only enable_set op to count the number 114 * FPGA Region programming test. The Region must call get_bridges() to get 166 ctx->mgr_dev = kunit_device_register(test, "fpga-manager-test-dev"); in fpga_region_test_init() 169 ctx->mgr = devm_fpga_mgr_register(ctx->mgr_dev, "Fake FPGA Manager", in fpga_region_test_init() 173 ctx->bridge_dev = kunit_device_register(test, "fpga-bridge-test-dev"); in fpga_region_test_init() [all …]
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/linux/drivers/misc/ |
H A D | lattice-ecp3-config.c | 19 * The JTAG ID's of the supported FPGA's. The ID is 32bit wide 25 /* FPGA commands */ 41 #define FPGA_CLEAR_TIMEOUT 5000 /* max. 5000ms for FPGA clear */ 92 /* Trying to speak with the FPGA via SPI... */ in firmware_load() 96 dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id); in firmware_load() 104 "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n", in firmware_load() 109 dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name); in firmware_load() 114 dev_dbg(&spi->dev, "FPGA Status=%08x\n", status); in firmware_load() 141 * Wait for FPGA memory to become cleared in firmware_load() 155 "Error: Timeout waiting for FPGA to clear (status=%08x)!\n", in firmware_load() [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | gef_ppc9a.dts | 35 4 0 0xfc000000 0x00008000 // FPGA 36 5 0 0xfc008000 0x00008000 // AFIX FPGA 37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit) 38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit) 80 fpga@4,0 { 81 compatible = "gef,ppc9a-fpga-regs"; 86 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", 87 "gef,fpga-wdt"; 94 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00", 95 "gef,fpga-wdt"; [all …]
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/linux/Documentation/devicetree/bindings/bus/ |
H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM. 10 - pwms : The PWM bound to the FPGA 11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA 12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA 13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA 14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA 15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA 16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
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/linux/arch/powerpc/boot/ |
H A D | ebony.c | 30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga" 38 u8 *fpga; in ebony_flashsel_fixup() local 43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup() 45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup() 49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup() 60 /* Invert address bit 14 (IBM-endian) if FLASH_SEL fpga bit is set */ in ebony_flashsel_fixup() 69 // FIXME: sysclk should be derived by reading the FPGA registers in ebony_fixups()
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/linux/arch/sh/boards/mach-highlander/ |
H A D | irq-r7785rp.c | 17 /* FPGA specific interrupt sources */ 71 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ in highlander_plat_irq_setup() 73 /* Setup the FPGA IRL */ in highlander_plat_irq_setup() 74 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ in highlander_plat_irq_setup() 75 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */ in highlander_plat_irq_setup() 76 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */ in highlander_plat_irq_setup() 77 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */ in highlander_plat_irq_setup() 78 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */ in highlander_plat_irq_setup() 79 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */ in highlander_plat_irq_setup()
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/linux/drivers/fpga/ |
H A D | dfl-fme-pr.c | 3 * Driver for FPGA Management Engine (FME) Partial Reconfiguration 23 #include <linux/fpga/fpga-mgr.h> 24 #include <linux/fpga/fpga-bridge.h> 25 #include <linux/fpga/fpga-region.h> 26 #include <linux/fpga-dfl.h> 165 * dfl_fme_create_mgr - create fpga mgr platform device as child device 185 * Each FME has only one fpga in dfl_fme_create_mgr() [all...] |
H A D | ts73xx-fpga.c | 3 * Technologic Systems TS-73xx SBC FPGA loader 7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on 17 #include <linux/fpga/fpga-mgr.h> 41 /* Reset the FPGA */ in ts73xx_fpga_write_init() 117 mgr = devm_fpga_mgr_register(kdev, "TS-73xx FPGA Manager", in ts73xx_fpga_probe() 124 .name = "ts73xx-fpga-mgr", 131 MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
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/linux/Documentation/devicetree/bindings/interrupt-controller/ |
H A D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller 3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board 9 - compatible: "arm,versatile-fpga-irq" 12 as the FPGA IRQ controller has no configuration options for interrupt 14 - reg: The register bank for the FPGA interrupt controller. 27 compatible = "arm,versatile-fpga-irq"; 36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
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