1afb79e99SAlan TullWhat: /sys/class/fpga_manager/<fpga>/name 2afb79e99SAlan TullDate: August 2015 3afb79e99SAlan TullKernelVersion: 4.3 4afb79e99SAlan TullContact: Alan Tull <atull@opensource.altera.com> 5afb79e99SAlan TullDescription: Name of low level fpga manager driver. 6afb79e99SAlan Tull 7afb79e99SAlan TullWhat: /sys/class/fpga_manager/<fpga>/state 8afb79e99SAlan TullDate: August 2015 9afb79e99SAlan TullKernelVersion: 4.3 10afb79e99SAlan TullContact: Alan Tull <atull@opensource.altera.com> 11afb79e99SAlan TullDescription: Read fpga manager state as a string. 12afb79e99SAlan Tull The intent is to provide enough detail that if something goes 13afb79e99SAlan Tull wrong during FPGA programming (something that the driver can't 14afb79e99SAlan Tull fix) then userspace can know, i.e. if the firmware request 15afb79e99SAlan Tull fails, that could be due to not being able to find the firmware 16afb79e99SAlan Tull file. 17afb79e99SAlan Tull 18afb79e99SAlan Tull This is a superset of FPGA states and fpga manager driver 19afb79e99SAlan Tull states. The fpga manager driver is walking through these steps 20afb79e99SAlan Tull to get the FPGA into a known operating state. It's a sequence, 21afb79e99SAlan Tull though some steps may get skipped. Valid FPGA states will vary 22afb79e99SAlan Tull by manufacturer; this is a superset. 23afb79e99SAlan Tull 24afb79e99SAlan Tull * unknown = can't determine state 25afb79e99SAlan Tull * power off = FPGA power is off 26afb79e99SAlan Tull * power up = FPGA reports power is up 27afb79e99SAlan Tull * reset = FPGA held in reset state 28afb79e99SAlan Tull * firmware request = firmware class request in progress 29afb79e99SAlan Tull * firmware request error = firmware request failed 30afb79e99SAlan Tull * write init = preparing FPGA for programming 31*54a19b4dSMauro Carvalho Chehab * write init error = Error while preparing FPGA for programming 32afb79e99SAlan Tull * write = FPGA ready to receive image data 33afb79e99SAlan Tull * write error = Error while programming 34afb79e99SAlan Tull * write complete = Doing post programming steps 35afb79e99SAlan Tull * write complete error = Error while doing post programming 36afb79e99SAlan Tull * operating = FPGA is programmed and operating 37ecb5fbe2SWu Hao 38ecb5fbe2SWu HaoWhat: /sys/class/fpga_manager/<fpga>/status 39ecb5fbe2SWu HaoDate: June 2018 40ecb5fbe2SWu HaoKernelVersion: 4.19 41ecb5fbe2SWu HaoContact: Wu Hao <hao.wu@intel.com> 42ecb5fbe2SWu HaoDescription: Read fpga manager status as a string. 43ecb5fbe2SWu Hao If FPGA programming operation fails, it could be caused by crc 44ecb5fbe2SWu Hao error or incompatible bitstream image. The intent of this 45ecb5fbe2SWu Hao interface is to provide more detailed information for FPGA 46ecb5fbe2SWu Hao programming errors to userspace. This is a list of strings for 47ecb5fbe2SWu Hao the supported status. 48ecb5fbe2SWu Hao 49ecb5fbe2SWu Hao * reconfig operation error - invalid operations detected by 50ecb5fbe2SWu Hao reconfiguration hardware. 51ecb5fbe2SWu Hao e.g. start reconfiguration 52ecb5fbe2SWu Hao with errors not cleared 53ecb5fbe2SWu Hao * reconfig CRC error - CRC error detected by 54ecb5fbe2SWu Hao reconfiguration hardware. 55ecb5fbe2SWu Hao * reconfig incompatible image - reconfiguration image is 56ecb5fbe2SWu Hao incompatible with hardware 57ecb5fbe2SWu Hao * reconfig IP protocol error - protocol errors detected by 58ecb5fbe2SWu Hao reconfiguration hardware 59ecb5fbe2SWu Hao * reconfig fifo overflow error - FIFO overflow detected by 60ecb5fbe2SWu Hao reconfiguration hardware 61