| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
9 - FPGA Region
18 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
19 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
22 This device tree binding document hits some of the high points of FPGA usage and
23 attempts to include terminology used by both major FPGA manufacturers. This
24 document isn't a replacement for any manufacturers specifications for FPGA
32 * The entire FPGA i
[all...] |
| H A D | xilinx-slave-serial.txt | 1 Xilinx Slave Serial SPI FPGA Manager
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
14 - compatible: should contain "xlnx,fpga-slave-serial"
15 - reg: spi chip select of the FPGA
23 Example for full FPGA configuration:
25 fpga-region0 {
26 compatible = "fpga-region";
27 fpga-mgr = <&fpga_mgr_spi>;
42 fpga_mgr_spi: fpga-mgr@0 {
43 compatible = "xlnx,fpga-slave-serial";
|
| H A D | xlnx,zynqmp-pcap-fpga.txt | 1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
8 Example for full FPGA configuration:
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
22 compatible = "xlnx,zynqmp-pcap-fpga";
|
| H A D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
24 fpga_mgr_spi: fpga-mgr@0 {
|
| H A D | altera-passive-serial.txt | 1 Altera Passive Serial SPI FPGA Manager
12 "altr,fpga-passive-serial",
13 "altr,fpga-arria10-passive-serial"
14 - reg: SPI chip select of the FPGA
22 fpga: fpga@0 {
23 compatible = "altr,fpga-passive-serial";
|
| H A D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
4 - compatible : should contain "altr,socfpga-fpga-mgr"
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
13 compatible = "altr,socfpga-fpga-mgr";
|
| H A D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
|
| H A D | lattice-ice40-fpga-mgr.txt | 1 Lattice iCE40 FPGA Manager
4 - compatible: Should contain "lattice,ice40-fpga-mgr"
10 FPGA will enter Master SPI mode and drive SCK with a
15 fpga: fpga@0 {
16 compatible = "lattice,ice40-fpga-mgr";
|
| H A D | xlnx,versal-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
30 compatible = "xlnx,versal-fpga";
|
| H A D | xilinx-pr-decoupler.txt | 4 decouplers / fpga bridges.
32 See Documentation/devicetree/bindings/fpga/fpga-region.txt and
33 Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
37 fpga-bridge@100000450 {
47 fpga-bridge@100000450 {
|
| H A D | xlnx,zynqmp-pcap-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
20 const: xlnx,zynqmp-pcap-fpga
32 compatible = "xlnx,zynqmp-pcap-fpga";
|
| H A D | microchip,mpf-spi-fpga-mgr.yaml | 4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
41 compatible = "microchip,mpf-spi-fpga-mgr";
|
| H A D | altera-hps2fpga-bridge.txt | 1 Altera FPGA/HPS Bridge Driver
12 See Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
15 fpga_bridge0: fpga-bridge@ff400000 {
23 fpga_bridge1: fpga-bridge@ff500000 {
31 fpga_bridge2: fpga-bridge@ff600000 {
|
| H A D | xlnx,fpga-slave-serial.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
7 title: Xilinx Slave Serial SPI FPGA
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
29 - xlnx,fpga-slave-serial
70 fpga_mgr_spi: fpga-mgr@0 {
71 compatible = "xlnx,fpga-slave-serial";
|
| H A D | intel-stratix10-soc-fpga-mgr.txt | 1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
8 "intel,agilex-soc-fpga-mgr"
14 fpga_mgr: fpga-mgr {
15 compatible = "intel,stratix10-soc-fpga-mgr";
|
| H A D | lattice,sysconfig.yaml | 4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
37 Indicates that the FPGA is ready to be configured.
73 fpga-mgr@0 {
|
| /freebsd/sys/contrib/device-tree/Bindings/board/ |
| H A D | fsl-board.txt | 20 * Freescale on-board FPGA
22 This is the memory-mapped registers for on board FPGA.
26 indicating the type of FPGA. Example:
27 "fsl,<board>-fpga", "fsl,fpga-pixis", or
28 "fsl,<board>-fpga", "fsl,fpga-qixis"
29 - reg: should contain the address and the length of the FPGA register set.
37 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
46 compatible = "fsl,ls2080ardb-fpga", "fsl,fpga-qixis";
50 * Freescale on-board FPGA connected on I2C bus
52 Some Freescale boards like BSC9132QDS have on board FPGA connected on
[all …]
|
| /freebsd/sys/dev/mlx5/mlx5_fpga/ |
| H A D | sdk.h | 46 * This header defines the in-kernel API for Innova FPGA client drivers.
62 * @fdev: The FPGA device
67 * @fdev: The FPGA device
77 * @fdev: The FPGA device
84 * @fdev: The FPGA device
119 * @conn: FPGA Connection this packet was sent to
120 * @fdev: FPGA device this packet was sent to
130 * struct mlx5_fpga_conn_attr - FPGA connection attributes
172 * mlx5_fpga_device_reload() - Force the FPGA to reload its synthesis from flash
173 * @fdev: The FPGA device
[all …]
|
| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | gef_ppc9a.dts | 35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
80 fpga@4,0 {
81 compatible = "gef,ppc9a-fpga-regs";
86 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
87 "gef,fpga-wdt";
94 compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
95 "gef,fpga-wdt";
[all …]
|
| H A D | gef_sbc310.dts | 35 4 0 0xfc000000 0x00010000>; // FPGA
77 fpga@4,0 {
78 compatible = "gef,fpga-regs";
83 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
84 "gef,fpga-wdt";
91 compatible = "gef,sbc310-fpga-wdt", "gef,fpga-wdt-1.00",
92 "gef,fpga-wdt";
101 compatible = "gef,sbc310-fpga-pic", "gef,fpga-pic";
|
| H A D | ge_imp3a.dts | 76 fpga@4,0 {
77 compatible = "ge,imp3a-fpga-regs";
85 compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
98 compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
99 "gef,fpga-wdt";
107 compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
108 "gef,fpga-wdt";
|
| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
9 - compatible: "arm,versatile-fpga-irq"
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
27 compatible = "arm,versatile-fpga-irq";
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
|
| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-mmioreg.txt | 4 like an FPGA, is used to control which child bus is connected. The mdio-mux
23 The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
28 /* The FPGA node */
29 fpga: board-control@3,0 {
32 compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | cirrus,lochnagar.yaml | 81 enum: [ fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4,
82 fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2,
116 enum: [ aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4,
117 fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2,
|