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/linux/Documentation/devicetree/bindings/rtc/
H A Dqcom-pm8xxx-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/qcom-pm8xxx-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya <quic_c_skakit@quicinc.com>
15 - enum:
16 - qcom,pm8058-rtc
17 - qcom,pm8921-rtc
18 - qcom,pm8941-rtc
19 - qcom,pmk8350-rtc
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
32 local-mac-address = [ 00 0f b7 10 63 54 ];
33 phy-handle = <&phy1>;
/linux/Documentation/devicetree/bindings/clock/
H A Dstericsson,u8500-clks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Linus Walleij <linus.walleij@linaro.org>
14 DB8500 digital baseband system-on-chip and its siblings such as
16 itself, not off-chip clocks. There are four different on-chip
17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
[all …]
H A Dmicrochip,mpfs-ccc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Conor Dooley <conor.dooley@microchip.com>
14 these blocks contains two PLLs and 2 DLLs & are located in the four corners of
16 https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
20 const: microchip,mpfs-ccc
24 - description: PLL0's control registers
25 - description: PLL1's control registers
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dcirrus,madera.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
21 include/dt-bindings/sound/madera.h
26 - $ref: dai-common.yaml#
29 '#sound-dai-cells':
31 The first cell indicating the audio interface.
37 of 24 cells, with four cells per input in the order INnAL,
38 INnAR INnBL INnBR. For non-muxed inputs the first two cells
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,rzn1-dmamux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: dma-router.yaml#
17 const: renesas,rzn1-dmamux
23 '#dma-cells':
26 The first four cells are dedicated to the master DMA controller. The fifth
27 cell gives the DMA mux bit index that must be set starting from 0. The
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8qm-lvds-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 It converts two groups of four 7/10 bits of CMOS data into two
15 groups of four data lanes of LVDS data streams. A phase-locked
30 - fsl,imx8qm-lvds-phy
31 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
33 "#phy-cells":
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
14 second cell is used to specify optional parameters (currently unused).
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
[all …]
/linux/Documentation/filesystems/spufs/
H A Dspufs.rst1 .. SPDX-License-Identifier: GPL-2.0
10 spufs - the SPU file system
16 The SPU file system is used on PowerPC machines that implement the Cell
26 logical SPU. Users can change permissions on those files, but not actu-
43 The files in spufs mostly follow the standard behavior for regular sys-
55 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
81 The first SPU to CPU communication mailbox. This file is read-only and
82 can be read in units of 32 bits. The file can only be used in non-
87 If a count smaller than four is requested, read returns -1 and
89 box, the return value is set to -1 and errno becomes EAGAIN.
[all …]
/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dusb-device.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 http://www.devicetree.org/open-firmware/bindings/usb/usb-1_0.ps
17 Four types of device-tree nodes are defined: "host-controller nodes"
32 pattern: "^usb[0-9a-f]{1,4},[0-9a-f]{1,4}$"
42 description: the number of the USB hub port or the USB host-controller
45 - minimum: 1
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
22 These four pixel formats are packed raw sRGB / Bayer formats with 10
23 bits per sample. Every four consecutive samples are packed into 5
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
29 with alternating green-red and green-blue rows. They are conventionally
[all …]
H A Dpixfmt-m420.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-M420:
10 YUV 4:2:0. Hybrid plane line-interleaved layout.
22 directions. Each CbCr pair belongs to four pixels. For example,
30 Each cell is one byte.
33 .. flat-table::
34 :header-rows: 0
35 :stub-columns: 0
37 * - start + 0:
38 - Y'\ :sub:`00`
[all …]
H A Dpixfmt-srggb8.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB8:
4 .. _v4l2-pix-fmt-sbggr8:
5 .. _v4l2-pix-fmt-sgbrg8:
6 .. _v4l2-pix-fmt-sgrbg8:
14 8-bit Bayer formats
20 These four pixel formats are raw sRGB / Bayer formats with 8 bits per
21 sample. Each sample is stored in a byte. Each n-pixel row contains n/2
27 Each cell is one byte.
32 .. flat-table::
[all …]
H A Dpixfmt-srggb10.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10:
4 .. _v4l2-pix-fmt-sbggr10:
5 .. _v4l2-pix-fmt-sgbrg10:
6 .. _v4l2-pix-fmt-sgrbg10:
16 10-bit Bayer formats expanded to 16 bits
22 These four pixel formats are raw sRGB / Bayer formats with 10 bits per
23 sample. Each sample is stored in a 16-bit word, with 6 unused
24 high bits filled with zeros. Each n-pixel row contains n/2 green samples and
31 Each cell is one byte, the 6 most significant bits in the high bytes
[all …]
H A Dpixfmt-srggb16.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB16:
4 .. _v4l2-pix-fmt-sbggr16:
5 .. _v4l2-pix-fmt-sgbrg16:
6 .. _v4l2-pix-fmt-sgrbg16:
15 16-bit Bayer formats
22 These four pixel formats are raw sRGB / Bayer formats with 16 bits per
23 sample. Each sample is stored in a 16-bit word. Each n-pixel row contains
30 Each cell is one byte.
32 .. flat-table::
[all …]
H A Dpixfmt-srggb12.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12:
4 .. _v4l2-pix-fmt-sbggr12:
5 .. _v4l2-pix-fmt-sgbrg12:
6 .. _v4l2-pix-fmt-sgrbg12:
17 12-bit Bayer formats expanded to 16 bits
23 These four pixel formats are raw sRGB / Bayer formats with 12 bits per
24 colour. Each colour component is stored in a 16-bit word, with 4 unused
25 high bits filled with zeros. Each n-pixel row contains n/2 green samples
32 Each cell is one byte, the 4 most significant bits in the high bytes are
[all …]
H A Dpixfmt-srggb14.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14:
4 .. _v4l2-pix-fmt-sbggr14:
5 .. _v4l2-pix-fmt-sgbrg14:
6 .. _v4l2-pix-fmt-sgrbg14:
15 14-bit Bayer formats expanded to 16 bits
22 These four pixel formats are raw sRGB / Bayer formats with 14 bits per
23 colour. Each sample is stored in a 16-bit word, with two unused high
24 bits filled with zeros. Each n-pixel row contains n/2 green samples
31 Each cell is one byte, the two most significant bits in the high bytes are
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
8 * None of the four SerDes lanes are used by the module, instead they are
15 /dts-v1/;
16 #include "fsl-ls1028a-kontron-sl28.dts"
17 #include <dt-bindings/net/qca-ar803x.h>
20 model = "Kontron SMARC-sAL28 (4 Lanes)";
21 compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
26 /delete-node/ ethernet-phy@5;
28 phy0: ethernet-phy@4 {
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dallwinner,sun6i-a31-msgbox.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Samuel Holland <samuel@sholland.org>
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
17 hold four 32-bit messages; when a FIFO is full, clients must wait before
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
26 - items:
27 - enum:
[all …]
/linux/drivers/thermal/mediatek/
H A Dauxadc_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
119 #define MT8173_TEMP_MIN -20000
472 * The MT8173 thermal controller has four banks. Each bank can read up to
473 * four temperature sensors simultaneously. The MT8173 has a total of 5
547 * four temperature sensors simultaneously. The MT8365 has a total of 3
581 * four temperature sensors simultaneously. The MT2712 has a total of 4
704 * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
719 tmp /= mt->conf->cali_val + mt->o_slope; in raw_to_mcelsius_v1()
720 tmp /= 10000 + mt->adc_ge; in raw_to_mcelsius_v1()
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dmipi-dsi-bus.txt5 communication between a host and up to four peripherals. This document will
8 This document describes DSI bus-specific properties only or defines existing
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
29 - #size-cells: Should be 0. There are cases where it makes sense to use a
33 - clock-master: boolean. Should be enabled if the host is being used in
43 ------------------------------------------------------
49 device-specific properties.
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
57 - The reg property can take multiple entries, one for each virtual channel
[all …]
/linux/Documentation/admin-guide/
H A Dunicode.rst4 Last update: 2005-01-17, version 1.4
12 ------------
15 characters to fonts. By downloading a single Unicode-to-font table,
16 both the eight-bit character sets and UTF-8 mode are changed to use
19 This changes the semantics of the eight-bit character tables subtly.
20 The four character tables are now:
25 LAT1_MAP Latin-1 (ISO 8859-1) ESC ( B
33 permits for example the use of block graphics even with a Latin-1 font
37 codes nor their uses match ISO 2022; Linux has two 8-bit codes (G0 and
38 G1), whereas ISO 2022 has four 7-bit codes (G0-G3).
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
[all …]
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_pic.c23 * -----------------
29 * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
33 * -----
61 * -------------------
63 * driver defines four separate 'irq_chip' structures, one for the main
73 * for this is that the four external interrupts are all managed with the same
83 * --------------------
85 * organization of irqs in the device. #interrupt-cells = <3> where the
86 * first cell is the group number [0..3], the second cell is the irq
87 * number in the group, and the third cell is the sense type (level/edge).
[all …]

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