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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sck-kv-g-revB.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
15 /dts-v1/;
18 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 compatible = "xlnx,zynqmp-sk-kv260-rev2",
21 "xlnx,zynqmp-sk-kv260-rev1",
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H A Dzynqmp-sck-kv-g-revA.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
8 * "A" – A01 board un-modified (NXP)
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/net/ti-dp83867.h>
17 #include <dt-bindings/phy/phy.h>
18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 /dts-v1/;
23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
24 #address-cells = <1>;
[all …]
H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
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/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl_subr.c1 /*-
7 * Asus RT-N16 firmware source code release.
21 * $Id: siutils.c,v 1.821.2.48 2011-02-11 20:59:28 Exp $
74 * or 0 if a fixed clock speed should be used.
78 * @param[out] fixed_hz If 0 is returned, will be set to the fixed clock
108 uint32_t rate; in bhnd_pwrctl_si_clock_rate() local
111 ("can't compute clock rate on fixed clock")); in bhnd_pwrctl_si_clock_rate()
113 rate = bhnd_pwrctl_clock_rate(pll_type, n, m); in bhnd_pwrctl_si_clock_rate()
115 rate /= 2; in bhnd_pwrctl_si_clock_rate()
117 return (rate); in bhnd_pwrctl_si_clock_rate()
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/freebsd/share/man/man4/man4.i386/
H A Dsbni.437 .Bl -bullet -compact
39 SBNI12-02, SBNI12D-02
41 SBNI12-04, SBNI12D-04
43 SBNI12-05, SBNI12D-05, ISA and PCI
45 SBNI12-10, SBNI12D-10, ISA and PCI
49 .Bl -bullet
51 SBNI12-11, SBNI12D-11, ISA and PCI.
58 which can set baud rate, receive level, and low three bytes of Ethernet
59 MAC-address (high three are always
62 presented to the system as Ethernet-like network cards.
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dfixed-mmio-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-mmio-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple memory mapped IO fixed-rate clock sources
10 This binding describes a fixed-rate clock for which the frequency can
11 be read from a single 32-bit memory mapped I/O register.
17 - Jan Kotas <jank@cadence.com>
21 const: fixed-mmio-clock
26 "#clock-cells":
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H A Dfixed-mmio-clock.txt1 Binding for simple memory mapped io fixed-rate clock sources.
2 The driver reads a clock frequency value from a single 32-bit memory mapped
3 I/O register and registers it as a fixed rate clock.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "fixed-mmio-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - reg : Address and length of the clock value register set.
17 - clock-output-names : From common clock binding.
21 #clock-cells = <0>;
22 compatible = "fixed-mmio-clock";
H A Dnvidia,tegra124-car.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
19 (for Tegra124-specific clocks).
20 - #reset-cells : Should be 1.
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
[all …]
/freebsd/sys/dev/ath/ath_rate/onoe/
H A Donoe.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
34 * Atsushi Onoe's rate control algorithm.
73 * Default parameters for the rate control algorithm. These are
74 * all tunable with sysctls. The rate controller runs periodically
78 * it gives a "raise rate credit". If transmits look to not be working
80 * the transmit rate is raised. Various error conditions force the
81 * the transmit rate to be dropped.
87 * the transmit rate is increased.
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-maste
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H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
42 - const: rx
[all …]
H A Dnvidia,tegra20-spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
38 clock-names:
40 - const: out
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/freebsd/share/man/man4/
H A Dpcm.42 .\" Copyright (c) 2009-2011 Joel Dahl <joel@FreeBSD.org>
39 .Bd -ragged -offset indent
60 driver are: multichannel audio, per-application
62 duplex operation, bit perfect audio, rate conversion and low latency
74 .Bl -bullet -compact
118 .Xr snd_uaudio 4 (auto-loaded on device plug)
145 .Bl -tag -width ".Va snd_driver_load" -offset indent
177 re-routing of channels.
198 Commonly used for ear-candy or frequency compensation due to the vast
232 .Bl -tag -width indent
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H A Dmouse.43 .\" Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
54 Movement and button states are usually encoded in fixed-length data packets.
58 The mouse drivers may have ``non-blocking'' attribute which will make
74 .Bl -tag -width Byte_1 -compact
76 .Bl -tag -width bit_7 -compact
92 -128 through 127.
95 -128 through 127.
98 -128 through 127.
103 -128 through 127.
109 Z axis movement count in two's complement; -64 through 63.
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/freebsd/sys/dev/ath/ath_rate/sample/
H A Dsample.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the names of the above-listed copyright holders nor the names
45 /* per-device state */
53 int min_switch; /* min time between rate changes */
54 int min_good_pct; /* min good percentage for a rate to be considered */
56 #define ATH_SOFTC_SAMPLE(sc) ((struct sample_softc *)sc->sc_rc)
70 uint8_t t0, r0; /* series 0: tries, rate code */
71 uint8_t t1, r1; /* series 1: tries, rate code */
72 uint8_t t2, r2; /* series 2: tries, rate code */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
16 regulator-alway
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
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/freebsd/sys/net/
H A Dsff8472.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013 George V. Neville-Neil
30 * The following set of constants are from Document SFF-8472
40 * 0-95 Serial ID Defined by SFP MSA
41 * 96-127 Vendor Specific Data
42 * 128-255 Reserved
45 * 0-55 Alarm and Warning Thresholds
46 * 56-95 Cal Constants
47 * 96-119 Real Time Diagnostic Interface
[all …]
/freebsd/share/man/man9/
H A Dieee80211_amrr.931 .Nd 802.11 network driver transmit rate control support
78 is an implementation of the AMRR transmit rate control algorithm
82 A rate control algorithm is responsible for choosing the transmit
83 rate for each frame.
84 To maximize throughput algorithms try to use the highest rate that
86 The rate will vary as conditions change; the distance between two stations
94 limits it's effectiveness--do not expect it to function well in
98 requires per-vap state and per-node state for each station it is to
100 The API's are designed for drivers to pre-allocate state in the
101 driver-private extension areas of each vap and node.
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