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/linux/drivers/clk/
H A Dclk-fixed-rate_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for clk fixed rate basic type
6 #include <linux/clk-provider.h>
17 #include "clk-fixed-rate_test.h"
20 * struct clk_hw_fixed_rate_kunit_params - Parameters to pass to __clk_hw_register_fixed_rate()
24 * @parent_name: parent name of clk
25 * @parent_hw: clk_hw pointer to parent of clk
26 * @parent_data: parent_data describing parent of clk
30 * @clk_fixed_flags: fixed rate specific clk flags
51 hw = __clk_hw_register_fixed_rate(params->dev, params->np, in clk_hw_register_fixed_rate_kunit_init()
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H A Dclk-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 - 2014 Texas Instruments Incorporated - https://www.ti.com
12 #include <linux/clk-provider.h>
26 * prepare - clk_(un)prepare are functional and control a gpio that can sleep
27 * enable - clk_enable and clk_disable are functional & control
28 * non-sleeping gpio
29 * rate - inherits rate from parent. No clk_set_rate support
30 * parent - fixed parent. No clk_set_parent support
34 * struct clk_gpio - gpio gated clock
36 * @hw: handle between common and hardware-specific interfaces
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H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
13 * DOC: basic fixed multiplier and divider clock that cannot gate
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
26 unsigned long long int rate; in clk_factor_recalc_rate() local
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
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H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
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/linux/drivers/clk/tegra/
H A Dclk-periph-fixed.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
19 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_is_enabled() local
20 u32 mask = 1 << (fixed->num % 32), value; in tegra_clk_periph_fixed_is_enabled()
22 value = readl(fixed->base + fixed->regs->enb_reg); in tegra_clk_periph_fixed_is_enabled()
24 value = readl(fixed->base + fixed->regs->rst_reg); in tegra_clk_periph_fixed_is_enabled()
34 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_enable() local
35 u32 mask = 1 << (fixed->num % 32); in tegra_clk_periph_fixed_enable()
37 writel(mask, fixed->base + fixed->regs->enb_set_reg); in tegra_clk_periph_fixed_enable()
44 struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw); in tegra_clk_periph_fixed_disable() local
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H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
77 * @max_rate: max rate allowed
81 unsigned long rate; member
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
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/linux/drivers/clk/renesas/
H A Drcar-gen2-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen2 Clock Pulse Generator
10 #include <linux/clk-provider.h>
18 #include "renesas-cpg-mssr.h"
19 #include "rcar-gen2-cpg.h"
39 * prepare - clk_prepare only ensures that parents are prepared
40 * enable - clk_enable only ensures that parents are enabled
41 * rate - rate is adjustable. clk->rate = parent->rate * mult / 32
42 * parent - fixed parent. No clk_set_parent support
60 val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT; in cpg_z_clk_recalc_rate()
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H A Drcar-gen3-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
16 #include <linux/clk-provider.h>
25 #include "renesas-cpg-mssr.h"
26 #include "rcar-cpg-lib.h"
27 #include "rcar-gen3-cpg.h"
59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; in cpg_pll_clk_recalc_rate()
62 return parent_rate * mult * pll_clk->fixed_mult; in cpg_pll_clk_recalc_rate()
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H A Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
67 #define CPG_SD0CKCR1 0x8a4 /* SD-IF0 Clock Freq. Control Reg. 1 */
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Dfixed-factor-clock.txt1 Binding for TI fixed factor rate clock sources.
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible : shall be "ti,fixed-factor-clock".
11 - #clock-cells : from common clock binding; shall be set to 0.
12 - ti,clock-div: fixed divider.
13 - ti,clock-mult: fixed multiplier.
14 - clocks: parent clock.
17 - clock-output-names : from common clock binding.
18 - ti,autoidle-shift: bit shift of the autoidle enable bit for the clock,
20 - reg: offset for the autoidle register of this clock, see [2]
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/linux/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
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/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
28 * PLL1 rate is calculated as follows
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
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H A Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
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/linux/drivers/clk/at91/
H A Dclk-audio-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Quentin Schulz <quentin.schulz@free-electrons.com>
9 * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
15 * enable - clk_enable writes nd, fracr parameters and enables PLL
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
18 * parent - fixed parent. No clk_set_parent support
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/linux/drivers/clk/st/
H A Dclkgen-fsyn.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk-provider.h>
129 { .name = "clk-s-c0-fs0-ch0", },
130 { .name = "clk-s-c0-fs0-ch1", },
131 { .name = "clk-s-c0-fs0-ch2", },
132 { .name = "clk-s-c0-fs0-ch3", },
186 { .name = "clk-s-d0-fs0-ch0", },
187 { .name = "clk-s-d0-fs0-ch1", },
188 { .name = "clk-s-d0-fs0-ch2", },
189 { .name = "clk-s-d0-fs0-ch3", },
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra20-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@nvidia.com>
16 - Jon Hunter <jonathanh@nvidia.com>
20 const: nvidia,tegra20-i2s
28 reset-names:
40 dma-names:
42 - const: rx
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H A Dnvidia,tegra20-spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Thierry Reding <treding@nvidia.com>
17 - Jon Hunter <jonathanh@nvidia.com>
20 - $ref: dai-common.yaml#
24 const: nvidia,tegra20-spdif
38 clock-names:
40 - const: out
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/linux/Documentation/networking/devlink/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
16 * - Name
17 - Mode
18 - Notes
19 * - ``enable_roce``
20 - runtime
21 - mutually exclusive with ``enable_iwarp``
22 * - ``enable_iwarp``
23 - runtime
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/linux/drivers/clk/davinci/
H A Dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/clk-provider.h>
20 #define PLL_PREDIV_FIXED_DIV BIT(3) /* fixed divider value */
23 #define PLL_POSTDIV_FIXED_DIV BIT(6) /* fixed divider value */
28 /** davinci_pll_clk_info - controller-specific PLL info
35 * @pllout_min_rate: Minimum allowable rate for PLLOUT
36 * @pllout_max_rate: Maximum allowable rate for PLLOUT
51 #define SYSCLK_ARM_RATE BIT(0) /* Controls ARM rate */
53 #define SYSCLK_FIXED_DIV BIT(2) /* Fixed divider */
55 /** davinci_pll_sysclk_info - SYSCLKn-specific info
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/linux/Documentation/devicetree/bindings/ufs/
H A Dufs-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alim Akhtar <alim.akhtar@samsung.com>
11 - Avri Altman <avri.altman@wdc.com>
16 clock-names: true
18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,s5pv210-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,s5pv210-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/s5pv210-audss.h header.
21 const: samsung,s5pv210-audss-clock
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/linux/drivers/clk/mvebu/
H A Ddove-divider.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
15 #include "dove-divider.h"
56 val = readl_relaxed(dc->base + DIV_CTRL0); in dove_get_divider()
57 val >>= dc->div_bit_start; in dove_get_divider()
59 divider = val & ~(~0 << dc->div_bit_size); in dove_get_divider()
61 if (dc->divider_table) in dove_get_divider()
62 divider = dc->divider_table[divider]; in dove_get_divider()
67 static int dove_calc_divider(const struct dove_clk *dc, unsigned long rate, in dove_calc_divider() argument
72 divider = DIV_ROUND_CLOSEST(parent_rate, rate); in dove_calc_divider()
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
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/linux/drivers/clk/zynqmp/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/sh2a/clock-sh7269.c
25 /* Fixed 32 KHz root clock for RTC */
27 .rate = 32768,
31 * Default rate for the root input clock, reset this with clk_set_rate()
35 .rate = 13340000,
40 return clk->parent->rate * PLL_RATE; in pll_recalc()
49 .parent = &extal_clk,
55 return clk->parent->rate / 8; in peripheral0_recalc()
64 .parent = &pll_clk,
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