1 // SPDX-License-Identifier: GPL-2.0+
11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
13 #include <linux/clk-provider.h>
150 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_recalc_rate()
151 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_recalc_rate()
152 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);  in ap_cpu_clk_recalc_rate()
153 	cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;  in ap_cpu_clk_recalc_rate()
154 	cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;  in ap_cpu_clk_recalc_rate()
159 static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,  in ap_cpu_clk_set_rate()  argument
163 	int ret, reg, divider = parent_rate / rate;  in ap_cpu_clk_set_rate()
166 	cpu_clkdiv_reg = clk->pll_regs->divider_reg +  in ap_cpu_clk_set_rate()
167 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
168 	cpu_force_reg = clk->pll_regs->force_reg +  in ap_cpu_clk_set_rate()
169 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
170 	cpu_ratio_reg = clk->pll_regs->ratio_reg +  in ap_cpu_clk_set_rate()
171 		(clk->cluster * clk->pll_regs->cluster_offset);  in ap_cpu_clk_set_rate()
173 	regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);  in ap_cpu_clk_set_rate()
174 	reg &= ~(clk->pll_regs->divider_mask);  in ap_cpu_clk_set_rate()
175 	reg |= (divider << clk->pll_regs->divider_offset);  in ap_cpu_clk_set_rate()
181 	if (clk->pll_regs->divider_ratio) {  in ap_cpu_clk_set_rate()
183 		reg |= ((divider * clk->pll_regs->divider_ratio) <<  in ap_cpu_clk_set_rate()
186 	regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);  in ap_cpu_clk_set_rate()
189 	regmap_update_bits(clk->pll_cr_base, cpu_force_reg,  in ap_cpu_clk_set_rate()
190 			   clk->pll_regs->force_mask,  in ap_cpu_clk_set_rate()
191 			   clk->pll_regs->force_mask);  in ap_cpu_clk_set_rate()
193 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,  in ap_cpu_clk_set_rate()
194 			   BIT(clk->pll_regs->ratio_offset),  in ap_cpu_clk_set_rate()
195 			   BIT(clk->pll_regs->ratio_offset));  in ap_cpu_clk_set_rate()
197 	stable_bit = BIT(clk->pll_regs->ratio_state_offset +  in ap_cpu_clk_set_rate()
198 			 clk->cluster *  in ap_cpu_clk_set_rate()
199 			 clk->pll_regs->ratio_state_cluster_offset);  in ap_cpu_clk_set_rate()
200 	ret = regmap_read_poll_timeout(clk->pll_cr_base,  in ap_cpu_clk_set_rate()
201 				       clk->pll_regs->ratio_state_reg, reg,  in ap_cpu_clk_set_rate()
207 	regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,  in ap_cpu_clk_set_rate()
208 			   BIT(clk->pll_regs->ratio_offset), 0);  in ap_cpu_clk_set_rate()
213 static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,  in ap_cpu_clk_round_rate()  argument
216 	int divider = *parent_rate / rate;  in ap_cpu_clk_round_rate()
232 	struct device *dev = &pdev->dev;  in ap_cpu_clock_probe()
233 	struct device_node *dn, *np = dev->of_node;  in ap_cpu_clock_probe()
238 	regmap = syscon_node_to_regmap(np->parent);  in ap_cpu_clock_probe()
246 	 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to  in ap_cpu_clock_probe()
247 	 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether  in ap_cpu_clock_probe()
260 			return -EINVAL;  in ap_cpu_clock_probe()
277 		return -ENOMEM;  in ap_cpu_clock_probe()
283 		return -ENOMEM;  in ap_cpu_clock_probe()
286 		char *clk_name = "cpu-cluster-0";  in ap_cpu_clock_probe()
289 		struct clk *parent;  in ap_cpu_clock_probe()  local
295 			return -EINVAL;  in ap_cpu_clock_probe()
302 		if (ap_cpu_data->hws[cluster_index])  in ap_cpu_clock_probe()
305 		parent = of_clk_get(np, cluster_index);  in ap_cpu_clock_probe()
306 		if (IS_ERR(parent)) {  in ap_cpu_clock_probe()
307 			dev_err(dev, "Could not get the clock parent\n");  in ap_cpu_clock_probe()
309 			return -EINVAL;  in ap_cpu_clock_probe()
311 		parent_name =  __clk_get_name(parent);  in ap_cpu_clock_probe()
314 			ap_cp_unique_name(dev, np->parent, clk_name);  in ap_cpu_clock_probe()
319 		ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);  in ap_cpu_clock_probe()
331 		ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;  in ap_cpu_clock_probe()
334 	ap_cpu_data->num = cluster_index + 1;  in ap_cpu_clock_probe()
345 		.compatible = "marvell,ap806-cpu-clock",
349 		.compatible = "marvell,ap807-cpu-clock",
358 		.name	= "marvell-ap-cpu-clock",