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/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amstrad E3 FIQ handling
10 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
24 #include <linux/soc/ti/omap1-io.h>
27 #include "ams-delta-fiq.h"
28 #include "board-ams-delta.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
[all …]
H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
30 #include <linux/platform_data/gpio-omap.h>
31 #include <linux/soc/ti/omap1-mux.h>
34 #include <asm/mach-types.h>
38 #include <linux/platform_data/keypad-omap.h>
42 #include "ams-delta-fiq.h"
43 #include "board-ams-delta.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
74 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
87 timer provides more intra-tick resolution than the 32KHz timer,
91 bool "Enable wake-up events for serial ports"
109 device drivers work properly.
149 have such a device.
154 select FIQ
161 if you have such a device.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux/drivers/irqchip/
H A Dirq-st.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This is a re-write of Christophe Kerello's PMU driver.
10 #include <dt-bindings/interrupt-controller/irq-st.h>
45 .compatible = "st,stih407-irq-syscfg",
52 int device, int channel, bool irq) in st_irq_xlate() argument
54 struct st_irq_syscfg *ddata = dev_get_drvdata(&pdev->dev); in st_irq_xlate()
56 /* Set the device enable bit. */ in st_irq_xlate()
57 switch (device) { in st_irq_xlate()
59 ddata->config |= ST_A9_IRQ_EN_EXT_0; in st_irq_xlate()
62 ddata->config |= ST_A9_IRQ_EN_EXT_1; in st_irq_xlate()
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H A Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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H A Dirq-omap-intc.c2 * linux/arch/arm/mach-omap2/irq.c
26 #include <linux/irqchip/irq-omap-intc.h>
134 /* Re-enable autoidle */ in omap3_intc_resume_idle()
139 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
205 gc->reg_base = base; in omap_alloc_gc_of()
206 ct = gc->chip_types; in omap_alloc_gc_of()
208 ct->type = IRQ_TYPE_LEVEL_MASK; in omap_alloc_gc_of()
210 ct->chip.irq_ack = omap_mask_ack_irq; in omap_alloc_gc_of()
211 ct->chip.irq_mask = irq_gc_mask_disable_reg; in omap_alloc_gc_of()
212 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in omap_alloc_gc_of()
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H A Dirq-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 1999 - 2003 ARM Limited
21 #include <linux/device.h>
23 #include <linux/irqchip/arm-vic.h>
31 #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
49 * struct vic_device - VIC PM device
82 * vic_init2 - common initialisation code
103 void __iomem *base = vic->base; in resume_one_vic()
107 /* re-initialise static settings */ in resume_one_vic()
110 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
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/linux/fs/fuse/
H A Ddev.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
45 return time_is_before_jiffies(req->create_time + fc->timeout.req_timeout); in fuse_request_expired()
62 * - check the fiq pending list
63 * - check the bg queue
64 * - check the fpq io and processing lists
69 * between lists, re-sent requests at the head of the pending list having a
78 struct fuse_iqueue *fiq = &fc->iq; in fuse_check_timeout() local
83 if (!atomic_read(&fc->num_waiting)) in fuse_check_timeout()
86 spin_lock(&fiq->lock); in fuse_check_timeout()
87 expired = fuse_request_expired(fc, &fiq->pending); in fuse_check_timeout()
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H A Dvirtio_fs.c1 // SPDX-License-Identifier: GPL-2.0
3 * virtio-fs: Virtio Filesystem
31 /* List of virtio-fs device instances and a lock for the list. Also provides
32 * mutual exclusion in device removal and mounting path
47 /* Per-virtqueue state */
50 struct virtqueue *vq; /* protected by ->lock */
63 /* A virtio-fs device instance */
125 struct fuse_fs_context *ctx = fsc->fs_private; in virtio_fs_parse_param()
134 ctx->dax_mode = FUSE_DAX_ALWAYS; in virtio_fs_parse_param()
137 ctx->dax_mode = result.uint_32; in virtio_fs_parse_param()
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H A Dfuse_i.h3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
23 #include <linux/backing-dev.h>
38 /** Bias for fi->writectr, meaning new writepages must not be sent */
46 #define FUSE_NAME_MAX (PATH_MAX - 1)
130 /** The sticky bit in inode->i_mode may have been removed, so
146 /* Files usable in writepage. Protected by fi->lock */
162 /* waitq for direct-io completion */
215 * The underlying inode->i_blkbits value will not be modified,
280 /** RB node to be linked on fuse_conn->polled_files */
286 /** Does file hold a fi->iocachectr refcount? */
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H A Dinode.c3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
87 sl->forget = fuse_alloc_forget(); in fuse_alloc_submount_lookup()
88 if (!sl->forget) in fuse_alloc_submount_lookup()
106 /* Initialize private data (i.e. everything except fi->inode) */ in fuse_alloc_inode()
108 memset((void *) fi + sizeof(fi->inode), 0, sizeof(*fi) - sizeof(fi->inode)); in fuse_alloc_inode()
110 fi->inval_mask = ~0; in fuse_alloc_inode()
111 mutex_init(&fi->mutex); in fuse_alloc_inode()
112 spin_lock_init(&fi->lock); in fuse_alloc_inode()
113 fi->forget = fuse_alloc_forget(); in fuse_alloc_inode()
114 if (!fi->forget) in fuse_alloc_inode()
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H A Ddev_uring.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2023-2024 DataDirect Networks.
18 "Enable userspace communication through io-uring");
40 pdu->ent = ring_ent; in uring_cmd_set_ring_ent()
48 return pdu->ent; in uring_cmd_to_ring_ent()
53 struct fuse_ring *ring = queue->ring; in fuse_uring_flush_bg()
54 struct fuse_conn *fc = ring->fc; in fuse_uring_flush_bg()
56 lockdep_assert_held(&queue->lock); in fuse_uring_flush_bg()
57 lockdep_assert_held(&fc->bg_lock); in fuse_uring_flush_bg()
62 * eliminates the need for remote queue wake-ups when global in fuse_uring_flush_bg()
[all …]
/linux/arch/arm/mach-rpc/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-rpc/dma.c
12 #include <linux/dma-mapping.h>
17 #include <asm/fiq.h>
48 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
49 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
50 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
51 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
52 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
58 if (idma->dma.sg) { in iomd_get_next_sg()
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/linux/arch/arm64/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
30 #include <asm/asm-uaccess.h>
64 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
66 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
67 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * after panic() re-enables interrupts.
93 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
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H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
106 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
116 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
134 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
135 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
148 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
149 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
152 fs[3] - (bits[2] + bits[1] + bits[0]); in smp_build_mpidr_hash()
185 "Error: invalid device tree blob: PA=%pa, VA=%px, size=%d bytes\n" in setup_machine_fdt()
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/linux/sound/soc/fsl/
H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
34 #include <linux/device.h>
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
21 The device tree nodes for the DMA channels that are referenced by
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
[all …]
/linux/arch/arm/mach-imx/
H A Dtzic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/device.h>
20 #include "irq-common.h"
58 return -EINVAL; in tzic_set_irq_fiq()
76 int idx = d->hwirq >> 5; in tzic_irq_suspend()
78 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); in tzic_irq_suspend()
83 int idx = d->hwirq >> 5; in tzic_irq_resume()
107 gc->private = &tzic_extra_irq; in tzic_init_gc()
108 gc->wake_enabled = IRQ_MSK(32); in tzic_init_gc()
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/linux/Documentation/arch/arm64/
H A Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
27 2. Setup the device tree
33 ---------------------------
48 2. Setup the device tree
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
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/linux/Documentation/arch/arm/
H A Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
60 - Other operations which implies shutting off or reconfiguring
66 - Define the physical address and size of ITCM and DTCM.
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/linux/arch/arm/mach-bcm/
H A Dbcm_kona_smc.c1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
37 /* Read buffer addr and size from the device tree node */ in bcm_kona_smc_init()
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
96 r5 = 0x3; /* Keep IRQ and FIQ off in SM */ in bcm_kona_do_smc()
117 /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
[all …]
/linux/arch/arm64/include/asm/
H A Dkvm_arm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
96 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
153 * We configure the Stage-2 page tables to always restrict the IPA space to be
172 * -----------------------------------------
174 * ------------------------------------------
175 * | Level: 0 | 2 | - |
176 * ------------------------------------------
178 * ------------------------------------------
180 * ------------------------------------------
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