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/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Amstrad E3 FIQ handling
10 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
24 #include <linux/soc/ti/omap1-io.h>
27 #include "ams-delta-fiq.h"
28 #include "board-ams-delta.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
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H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 #include <linux/soc/ti/omap1-mux.h>
33 #include <asm/mach-types.h>
37 #include <linux/platform_data/keypad-omap.h>
41 #include "ams-delta-fiq.h"
42 #include "board-ams-delta.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
73 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
86 timer provides more intra-tick resolution than the 32KHz timer,
90 bool "Enable wake-up events for serial ports"
108 device drivers work properly.
148 have such a device.
153 select FIQ
160 if you have such a device.
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
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H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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H A Dst,stih407-irq-syscfg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,stih407-irq-syscfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
15 Configuration registers. This device is used to unmask them prior to use.
19 const: st,stih407-irq-syscfg
22 description: Phandle to Cortex-A9 IRQ system config registers
25 st,irq-device:
27 $ref: /schemas/types.yaml#/definitions/uint32-array
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/linux/drivers/irqchip/
H A Dirq-st.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * This is a re-write of Christophe Kerello's PMU driver.
10 #include <dt-bindings/interrupt-controller/irq-st.h>
45 .compatible = "st,stih407-irq-syscfg",
52 int device, int channel, bool irq) in st_irq_xlate() argument
54 struct st_irq_syscfg *ddata = dev_get_drvdata(&pdev->dev); in st_irq_xlate()
56 /* Set the device enable bit. */ in st_irq_xlate()
57 switch (device) { in st_irq_xlate()
59 ddata->config |= ST_A9_IRQ_EN_EXT_0; in st_irq_xlate()
62 ddata->config |= ST_A9_IRQ_EN_EXT_1; in st_irq_xlate()
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H A Dirq-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on arch/arm/mach-ixp4xx/common.c
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
35 /* IXP43x and IXP46x-only */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
44 * struct ixp4xx_irq - state container for the Faraday IRQ controller
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H A Dirq-apple-aic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on irq-lpc32xx:
6 * Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
7 * Based on irq-bcm2836:
14 * - 896 level-triggered hardware IRQs
15 * - Single mask bit per IRQ
16 * - Per-IRQ affinity setting
17 * - Automatic masking on event delivery (auto-ack)
18 * - Software triggering (ORed with hw line)
19 * - 2 per-CPU IPIs (meant as "self" and "other", but they are
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H A Dirq-omap-intc.c2 * linux/arch/arm/mach-omap2/irq.c
26 #include <linux/irqchip/irq-omap-intc.h>
134 /* Re-enable autoidle */ in omap3_intc_resume_idle()
139 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
205 gc->reg_base = base; in omap_alloc_gc_of()
206 ct = gc->chip_types; in omap_alloc_gc_of()
208 ct->type = IRQ_TYPE_LEVEL_MASK; in omap_alloc_gc_of()
210 ct->chip.irq_ack = omap_mask_ack_irq; in omap_alloc_gc_of()
211 ct->chip.irq_mask = irq_gc_mask_disable_reg; in omap_alloc_gc_of()
212 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; in omap_alloc_gc_of()
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H A Dirq-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 1999 - 2003 ARM Limited
21 #include <linux/device.h>
23 #include <linux/irqchip/arm-vic.h>
31 #define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
49 * struct vic_device - VIC PM device
82 * vic_init2 - common initialisation code
103 void __iomem *base = vic->base; in resume_one_vic()
107 /* re-initialise static settings */ in resume_one_vic()
110 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
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/linux/arch/arm/include/asm/
H A Decard.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * 11-12-1996 RMK Further minor improvements
11 * 12-09-1997 RMK Added interrupt enable/disable for card level
104 unsigned char fiqmask; /* FIQ mask */
106 unsigned long fiqoff; /* FIQ offset */
130 #define ecard_resource_start(ec,nr) ((ec)->resource[nr].start)
131 #define ecard_resource_end(ec,nr) ((ec)->resource[nr].end)
132 #define ecard_resource_len(ec,nr) ((ec)->resource[nr].end - \
133 (ec)->resource[nr].start + 1)
134 #define ecard_resource_flags(ec,nr) ((ec)->resource[nr].flags)
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/linux/arch/arm/mach-rpc/
H A Ddma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-rpc/dma.c
12 #include <linux/dma-mapping.h>
17 #include <asm/fiq.h>
48 #define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
49 #define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
50 #define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
51 #define CR (IOMD_IO0CR - IOMD_IO0CURA)
52 #define ST (IOMD_IO0ST - IOMD_IO0CURA)
58 if (idma->dma.sg) { in iomd_get_next_sg()
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H A Decard.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 1995-2001 Russell King
11 * 08-Dec-1996 RMK Added code for the 9'th expansion card - the ether
13 * 06-May-1997 RMK Added blacklist for cards whose loader doesn't work.
14 * 12-Sep-1997 RMK Created new handling of interrupt enables/disables
15 * - cards can now register their own routine to control
17 * 29-Sep-1997 RMK Expansion card interrupt hardware not being re-enabled
20 * 15-Feb-1998 RMK Added DMA support
21 * 12-Sep-1998 RMK Added EASI support
22 * 10-Jan-1999 RMK Run loaders in a simulated RISC OS environment.
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/linux/sound/soc/fsl/
H A Dimx-pcm-fiq.c1 // SPDX-License-Identifier: GPL-2.0+
2 // imx-pcm-fiq.c -- ALSA Soc Audio Layer
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
26 #include <asm/fiq.h>
28 #include <linux/platform_data/asoc-imx-ssi.h>
30 #include "imx-ssi.h"
31 #include "imx-pcm.h"
48 struct snd_pcm_substream *substream = iprtd->substream; in snd_hrtimer_callback()
51 if (!atomic_read(&iprtd->playing) && !atomic_read(&iprtd->capturing)) in snd_hrtimer_callback()
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H A Dfsl_ssi.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // Some notes why imx-pcm-fiq is used instead of DMA on some boards:
16 // we receive in our (PCM-) data stream. The only chance we have is to
17 // manually skip this data in the FIQ handler. With sampling rates different
19 // between pcm data and GPIO status data changes. Our FIQ handler is not
34 #include <linux/device.h>
43 #include <linux/dma/imx-dma.h>
53 #include "imx-pcm.h"
55 /* Define RX and TX to index ssi->regvals array; Can be 0 or 1 only */
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
21 The device tree nodes for the DMA channels that are referenced by
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
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/linux/arch/arm/mach-imx/
H A Dtzic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 #include <linux/device.h>
20 #include "irq-common.h"
58 return -EINVAL; in tzic_set_irq_fiq()
76 int idx = d->hwirq >> 5; in tzic_irq_suspend()
78 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); in tzic_irq_suspend()
83 int idx = d->hwirq >> 5; in tzic_irq_resume()
107 gc->private = &tzic_extra_irq; in tzic_init_gc()
108 gc->wake_enabled = IRQ_MSK(32); in tzic_init_gc()
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/linux/arch/arm/mach-bcm/
H A Dbcm_kona_smc.c1 // SPDX-License-Identifier: GPL-2.0-only
25 {.compatible = "brcm,kona-smc"},
26 {.compatible = "bcm,kona-smc"}, /* deprecated name */
37 /* Read buffer addr and size from the device tree node */ in bcm_kona_smc_init()
40 return -ENODEV; in bcm_kona_smc_init()
45 return -EINVAL; in bcm_kona_smc_init()
49 return -ENOMEM; in bcm_kona_smc_init()
69 * Parameters to the "smc" request are passed in r4-r6 as follows:
96 r5 = 0x3; /* Keep IRQ and FIQ off in SM */ in bcm_kona_do_smc()
117 /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
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/linux/Documentation/arch/arm/
H A Dtcm.rst2 ARM TCM (Tightly-Coupled Memory) handling in Linux
7 Some ARM SoCs have a so-called TCM (Tightly-Coupled Memory).
8 This is usually just a few (4-64) KiB of RAM inside the ARM
12 Harvard-architecture, so there is an ITCM (instruction TCM)
24 determine if ITCM (bits 1-0) and/or DTCM (bit 17-16) is present
52 - FIQ and other interrupt handlers that need deterministic
55 - Idle loops where all external RAM is set to self-refresh
56 retention mode, so only on-chip RAM is accessible by
60 - Other operations which implies shutting off or reconfiguring
66 - Define the physical address and size of ITCM and DTCM.
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/linux/drivers/clocksource/
H A Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
84 struct device *dev;
95 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
100 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
105 return readl_relaxed(wdt->regs + offset); in wdt_readl()
114 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
116 return ERR_PTR(-ENOMEM); in tegra186_tmr_create()
118 tmr->parent = tegra; in tegra186_tmr_create()
119 tmr->regs = tegra->regs + offset; in tegra186_tmr_create()
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/linux/arch/arm64/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
106 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
116 * Pre-scan the list of MPIDRS and filter out bits that do in smp_build_mpidr_hash()
134 fs[i] = affinity ? ffs(affinity) - 1 : 0; in smp_build_mpidr_hash()
135 bits[i] = ls - fs[i]; in smp_build_mpidr_hash()
148 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0]; in smp_build_mpidr_hash()
149 mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] - in smp_build_mpidr_hash()
152 fs[3] - (bits[2] + bits[1] + bits[0]); in smp_build_mpidr_hash()
185 "Error: invalid device tree blob at physical address %pa (virtual address 0x%px)\n" in setup_machine_fdt()
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/linux/arch/arm64/kvm/vgic/
H A Dvgic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
24 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
26 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
37 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
38 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
39 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
44 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
46 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
47 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
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/linux/arch/arm/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1995-2001 Russell King
46 #include <asm/mach-types.h>
140 u32 fiq[4]; member
300 /* I-cache aliases will be handled by D-cache aliasing code */ in cpu_has_aliasing_icache()
353 * These functions re-use the assembly code in head.S, which
527 * cpu_init - initialise one CPU.
529 * cpu_init sets up the per-CPU stacks.
552 * In Thumb-2, msr with an immediate value is not allowed. in cpu_init()
563 * setup stacks for re-entrant exception handlers in cpu_init()
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/linux/arch/arm/boot/dts/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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