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/linux/Documentation/devicetree/bindings/interconnect/
H A Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos SoC has many buses for data transfer between DRAM and
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-bus.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC Memory interface and AMBA bus device tree source
11 compatible = "samsung,exynos-bus";
13 clock-names = "bus";
14 operating-points-v2 = <&bus_g2d_400_opp_table>;
19 compatible = "samsung,exynos-bus";
21 clock-names = "bus";
22 operating-points-v2 = <&bus_g2d_266_opp_table>;
27 compatible = "samsung,exynos-bus";
29 clock-names = "bus";
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5420.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 bus_disp1: bus-disp1 {
38 compatible = "samsung,exynos-bus";
40 clock-names = "bus";
44 bus_disp1_fimd: bus-disp1-fimd {
45 compatible = "samsung,exynos-bus";
47 clock-names = "bus";
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H A Dexynos4210.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
20 #include "exynos4-cpu-thermal.dtsi"
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos4x12.dtsi1 // SPDX-License-Identifier: GPL-2.0
19 #include "exynos4-cpu-thermal.dtsi"
27 fimc-lite0 = &fimc_lite_0;
28 fimc-lite1 = &fimc_lite_1;
31 bus_acp: bus-acp {
32 compatible = "samsung,exynos-bus";
34 clock-names = "bus";
35 operating-points-v2 = <&bus_acp_opp_table>;
38 bus_acp_opp_table: opp-table {
39 compatible = "operating-points-v2";
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H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
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H A Dexynos4.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2010-2011 Linaro Ltd.
19 #include <dt-bindings/clock/exynos4.h>
20 #include <dt-bindings/clock/exynos-audss-clk.h>
21 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 #include <dt-bindings/interrupt-controller/irq.h>
25 interrupt-parent = <&gic>;
26 #address-cells = <1>;
27 #size-cells = <1>;
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/linux/drivers/devfreq/
H A Dexynos-bus.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Generic Exynos Bus frequency driver with DEVFREQ Framework
8 * This driver support Exynos Bus frequency feature by using
9 * DEVFREQ framework and is based on drivers/devfreq/exynos/exynos4_bus.c.
14 #include <linux/devfreq-event.h>
42 * Control the devfreq-event device to get the current state of bus
45 static int exynos_bus_##ops(struct exynos_bus *bus) \
49 for (i = 0; i < bus->edev_count; i++) { \
50 if (!bus->edev[i]) \
52 ret = devfreq_event_##ops(bus->edev[i]); \
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 to a device by 1-to-1. The device registering devfreq takes the
39 Simple-Ondemand should be able to provide busy/total counter
79 tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
86 This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
87 Memory bus has one more group of memory bus (e.g, MIF and INT block).
88 Each memory bus group could contain many memoby bus block. It reads
89 PPMU counters of memory controllers by using DEVFREQ-event device
94 tristate "i.MX Generic Bus DEVFREQ Driver"
/linux/Documentation/devicetree/bindings/iommu/
H A Dsamsung,sysmmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
10 - Marek Szyprowski <m.szyprowski@samsung.com>
13 Samsung's Exynos architecture contains System MMUs that enables scattered
14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
15 devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
20 another capabilities like L2 TLB or block-fetch buffers to minimize translation
24 peripheral device might have multiple System MMUs (usually one for each bus
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/linux/drivers/ufs/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
12 tristate "PCI bus based UFS Controller support"
31 tristate "Platform bus based UFS Controller support"
35 you have an UFS controller on Platform bus.
45 This selects the Cadence-specific additions to UFSHCD platform driver.
120 tristate "Exynos specific hooks to UFS controller platform driver"
123 This selects the Samsung Exynos SoC specific additions to UFSHCD
124 platform driver. UFS host on Samsung Exynos SoC includes HCI and
125 UNIPRO layer, and associates with UFS-PHY driver.
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/linux/drivers/devfreq/event/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "DEVFREQ-Event device Support"
5 The devfreq-event device provide the raw data and events which
6 indicate the current state of devfreq-event device. The provided
7 data from devfreq-event device is used to monitor the state of
11 The devfreq-event device can support the various type of events
18 tristate "Exynos NoC (Network On Chip) Probe DEVFREQ event Driver"
23 This add the devfreq-event driver for Exynos SoC. It provides NoC
24 (Network on Chip) Probe counters to measure the bandwidth of AXI bus.
27 tristate "Exynos PPMU (Platform Performance Monitoring Unit) DEVFREQ event Driver"
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsamsung,exynos-adc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/samsung,exynos-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Analog to Digital Converter (ADC)
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,exynos-adc-v1 # Exynos5250
17 - samsung,exynos-adc-v2
18 - samsung,exynos3250-adc
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-mixer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Mixer
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
16 Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
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/linux/Documentation/devicetree/bindings/devfreq/event/
H A Dsamsung,exynos-nocp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/devfreq/event/samsung,exynos-nocp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos NoC (Network on Chip) Probe
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 The Samsung Exynos542x SoC has a NoC (Network on Chip) Probe for NoC bus.
19 traffic debug or statistic collectors. Exynos542x bus has multiple NoC probes
25 const: samsung,exynos5420-nocp
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/linux/Documentation/admin-guide/media/
H A Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
8 use neither USB nor PCI bus. Those drivers are called platform
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
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/linux/drivers/pci/controller/dwc/
H A Dpci-exynos.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Samsung Exynos SoCs
5 * Copyright (C) 2013-2020 Samsung Electronics Co., Ltd.
24 #include "pcie-designware.h"
26 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
76 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
81 exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_AWMISC); in exynos_pcie_sideband_dbi_w_mode()
88 val = exynos_pcie_readl(ep->elbi_base, PCIE_ELBI_SLV_ARMISC); in exynos_pcie_sideband_dbi_r_mode()
93 exynos_pcie_writel(ep->elbi_base, val, PCIE_ELBI_SLV_ARMISC); in exynos_pcie_sideband_dbi_r_mode()
100 val = exynos_pcie_readl(ep->elbi_base, PCIE_CORE_RESET); in exynos_pcie_assert_core_reset()
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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos-audss-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Audio SubSystem clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
17 include/dt-bindings/clock/exynos-audss-clk.h header.
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H A Dsamsung,exynosautov9-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Auto v9 SoC clock controller
10 - Chanho Park <chanho61.park@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-exynos5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
17 e.g. for Exynos850 and Exynos Auto V9 SoCs), it might be also necessary to
19 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
24 - enum:
25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
26 - samsung,exynos5260-hsi2c # Exynos5260
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H A Dsamsung,s3c2410-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC I2C Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,s3c2410-i2c
17 - samsung,s3c2440-i2c
18 # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
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/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-usi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's Exynos USI (Universal Serial Interface)
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Krzysztof Kozlowski <krzk@kernel.org>
14 USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
17 child nodes, each representing a serial sub-node device. The mode setting
22 pattern: "^usi@[0-9a-f]+$"
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_gem.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 * exynos drm buffer structure.
22 * - a new handle to this gem object would be created
29 * @dma_addr: bus address(accessed by dma) to allocated memory region.
30 * - this address could be physical address without IOMMU and
66 /* get fake-offset of gem object that can be used with mmap. */
71 * get exynos drm object from gem handle, this function could be used for
79 * put exynos drm object acquired from exynos_drm_gem_get(),
84 drm_gem_object_put(&exynos_gem->base); in exynos_drm_gem_put()
99 /* low-level interface prime helpers */
/linux/drivers/clk/samsung/
H A Dclk-exynos-arm64.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * This file contains shared functions used by some arm64 Exynos SoCs,
18 #include "clk-exynos-arm64.h"
67 * exynos_arm64_init_clocks - Set clocks initial configuration
76 const unsigned long *reg_offs = cmu->clk_regs; in exynos_arm64_init_clocks()
77 size_t reg_offs_len = cmu->nr_clk_regs; in exynos_arm64_init_clocks()
89 if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) { in exynos_arm64_init_clocks()
103 * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
119 if (!cmu->clk_name) in exynos_arm64_enable_bus_clk()
125 parent_clk = clk_get(dev, cmu->clk_name); in exynos_arm64_enable_bus_clk()
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/linux/drivers/char/hw_random/
H A Dexynos-trng.c1 // SPDX-License-Identifier: GPL-2.0
3 * RNG driver for Exynos TRNGs
9 * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by
13 #include <linux/arm-smccc.h>
77 struct clk *pclk; /* bus clock */
85 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; in exynos_trng_do_read_reg()
89 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); in exynos_trng_do_read_reg()
90 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, in exynos_trng_do_read_reg()
95 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max); in exynos_trng_do_read_reg()
126 return -EIO; in exynos_trng_do_read_smc()
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