1 // SPDX-License-Identifier: GPL-2.0-only
8  * This file contains shared functions used by some arm64 Exynos SoCs,
18 #include "clk-exynos-arm64.h"
67  * exynos_arm64_init_clocks - Set clocks initial configuration
76 	const unsigned long *reg_offs = cmu->clk_regs;  in exynos_arm64_init_clocks()
77 	size_t reg_offs_len = cmu->nr_clk_regs;  in exynos_arm64_init_clocks()
89 		if (cmu->manual_plls && is_pll_con1_reg(reg_offs[i])) {  in exynos_arm64_init_clocks()
103  * exynos_arm64_enable_bus_clk - Enable parent clock of specified CMU
119 	if (!cmu->clk_name)  in exynos_arm64_enable_bus_clk()
125 		parent_clk = clk_get(dev, cmu->clk_name);  in exynos_arm64_enable_bus_clk()
128 			data->clk = parent_clk;  in exynos_arm64_enable_bus_clk()
130 		parent_clk = of_clk_get_by_name(np, cmu->clk_name);  in exynos_arm64_enable_bus_clk()
145 	data->clk_save = samsung_clk_alloc_reg_dump(cmu->clk_regs,  in exynos_arm64_cmu_prepare_pm()
146 						    cmu->nr_clk_regs);  in exynos_arm64_cmu_prepare_pm()
147 	if (!data->clk_save)  in exynos_arm64_cmu_prepare_pm()
148 		return -ENOMEM;  in exynos_arm64_cmu_prepare_pm()
150 	data->nr_clk_save = cmu->nr_clk_regs;  in exynos_arm64_cmu_prepare_pm()
151 	data->clk_suspend = cmu->suspend_regs;  in exynos_arm64_cmu_prepare_pm()
152 	data->nr_clk_suspend = cmu->nr_suspend_regs;  in exynos_arm64_cmu_prepare_pm()
153 	data->nr_pclks = of_clk_get_parent_count(dev->of_node);  in exynos_arm64_cmu_prepare_pm()
154 	if (!data->nr_pclks)  in exynos_arm64_cmu_prepare_pm()
157 	data->pclks = devm_kcalloc(dev, sizeof(struct clk *), data->nr_pclks,  in exynos_arm64_cmu_prepare_pm()
159 	if (!data->pclks) {  in exynos_arm64_cmu_prepare_pm()
160 		kfree(data->clk_save);  in exynos_arm64_cmu_prepare_pm()
161 		return -ENOMEM;  in exynos_arm64_cmu_prepare_pm()
164 	for (i = 0; i < data->nr_pclks; i++) {  in exynos_arm64_cmu_prepare_pm()
165 		struct clk *clk = of_clk_get(dev->of_node, i);  in exynos_arm64_cmu_prepare_pm()
168 			kfree(data->clk_save);  in exynos_arm64_cmu_prepare_pm()
169 			while (--i >= 0)  in exynos_arm64_cmu_prepare_pm()
170 				clk_put(data->pclks[i]);  in exynos_arm64_cmu_prepare_pm()
173 		data->pclks[i] = clk;  in exynos_arm64_cmu_prepare_pm()
180  * exynos_arm64_register_cmu - Register specified Exynos CMU domain
203 		pr_err("%s: could not enable bus clock %s; err = %d\n",  in exynos_arm64_register_cmu()
204 		       __func__, cmu->clk_name, err);  in exynos_arm64_register_cmu()
211  * exynos_arm64_register_cmu_pm - Register Exynos CMU domain with PM support
225 	struct device *dev = &pdev->dev;  in exynos_arm64_register_cmu_pm()
226 	struct device_node *np = dev->of_node;  in exynos_arm64_register_cmu_pm()
235 		return -ENOMEM;  in exynos_arm64_register_cmu_pm()
249 		dev_err(dev, "%s: could not enable bus clock %s; err = %d\n",  in exynos_arm64_register_cmu_pm()
250 		       __func__, cmu->clk_name, ret);  in exynos_arm64_register_cmu_pm()
259 	data->ctx = samsung_clk_init(dev, reg_base, cmu->nr_clk_ids);  in exynos_arm64_register_cmu_pm()
271 	samsung_cmu_register_clocks(data->ctx, cmu);  in exynos_arm64_register_cmu_pm()
272 	samsung_clk_of_add_provider(dev->of_node, data->ctx);  in exynos_arm64_register_cmu_pm()
283 	samsung_clk_save(data->ctx->reg_base, data->clk_save,  in exynos_arm64_cmu_suspend()
284 			 data->nr_clk_save);  in exynos_arm64_cmu_suspend()
286 	for (i = 0; i < data->nr_pclks; i++)  in exynos_arm64_cmu_suspend()
287 		clk_prepare_enable(data->pclks[i]);  in exynos_arm64_cmu_suspend()
290 	samsung_clk_restore(data->ctx->reg_base, data->clk_suspend,  in exynos_arm64_cmu_suspend()
291 			    data->nr_clk_suspend);  in exynos_arm64_cmu_suspend()
293 	for (i = 0; i < data->nr_pclks; i++)  in exynos_arm64_cmu_suspend()
294 		clk_disable_unprepare(data->pclks[i]);  in exynos_arm64_cmu_suspend()
296 	clk_disable_unprepare(data->clk);  in exynos_arm64_cmu_suspend()
306 	clk_prepare_enable(data->clk);  in exynos_arm64_cmu_resume()
308 	for (i = 0; i < data->nr_pclks; i++)  in exynos_arm64_cmu_resume()
309 		clk_prepare_enable(data->pclks[i]);  in exynos_arm64_cmu_resume()
311 	samsung_clk_restore(data->ctx->reg_base, data->clk_save,  in exynos_arm64_cmu_resume()
312 			    data->nr_clk_save);  in exynos_arm64_cmu_resume()
314 	for (i = 0; i < data->nr_pclks; i++)  in exynos_arm64_cmu_resume()
315 		clk_disable_unprepare(data->pclks[i]);  in exynos_arm64_cmu_resume()