| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | atmel,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma balasubiramani <dharma.b@microchip.com>
14 The Advanced Interrupt Controller (AIC) is an 8-level priority, individually
16 hundred and twenty-eight interrupt sources.
21 - atmel,at91rm9200-aic
22 - atmel,sama5d2-aic
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| H A D | st,sti-irq-syscfg.txt | 1 STMicroelectronics STi System Configuration Controlled IRQs
2 -----------------------------------------------------------
4 On STi based systems; External, CTI (Core Sight), PMU (Performance Management),
5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
9 - compatible : Should be "st,stih407-irq-syscfg"
10 - st,syscfg : Phandle to Cortex-A9 IRQ system config registers
11 - st,irq-device : Array of IRQs to enable - should be 2 in length
12 - st,fiq-device : Array of FIQs to enable - should be 2 in length
15 - st,invert-ext : External IRQs can be inverted at will. This property inverts
16 these IRQs using bitwise logic. A number of defines have been
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| H A D | microchip,pic32-evic.txt | 5 It handles all internal and external interrupts. This controller exists outside
9 External interrupts have a software configurable edge polarity. Non external
14 -------------------
16 - compatible: Should be "microchip,pic32mzda-evic"
17 - reg: Specifies physical base address and size of register range.
18 - interrupt-controller: Identifies the node as an interrupt controller.
19 - #interrupt cells: Specifies the number of cells used to encode an interrupt
25 hw_irq - represents the hardware interrupt number as in the data sheet.
26 irq_type - is used to describe the type and polarity of an interrupt. For
28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
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| H A D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
22 - reg: Should contain AIC registers location and length
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| H A D | ti,pruss-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controlle
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| H A D | fsl,ls-extirq.txt | 1 * Freescale Layerscape external IRQs
5 the polarity of certain external interrupt lines.
11 - compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".
12 "fsl,ls1043a-extirq": for LS1043A, LS1046A.
13 "fsl,ls1088a-extirq": for LS1088A, LS208xA, LX216xA.
14 - #interrupt-cells: Must be 2. The first element is the index of the
15 external interrupt line. The second element is the trigger type.
16 - #address-cells: Must be 0.
17 - interrupt-controller: Identifies the node as an interrupt controller
18 - reg: Specifies the Interrupt Polarity Control Register (INTPCR) in
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| H A D | microchip,sama7g5-eic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,sama7g5-eic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip External Interrupt Controller
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 support for handling up to 2 external interrupt lines.
19 - microchip,sama7g5-eic
24 interrupt-controller: true
26 '#interrupt-cells':
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| H A D | microchip,eic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip External Interrupt Controller
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
14 support for handling up to 2 external interrupt lines.
19 - microchip,sama7g5-eic
24 interrupt-controller: true
26 '#interrupt-cells':
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| H A D | actions,owl-sirq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
15 and S900) and provides support for handling up to 3 external interrupt lines.
20 - actions,s500-sirq
21 - actions,s700-sirq
22 - actions,s900-sirq
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| H A D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
4 for dynamic IRQ routing, load balancing of common/external IRQs towards core
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
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| /freebsd/sys/contrib/dev/athk/ath11k/ |
| H A D | ahb.c | 1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
11 #include <linux/dma-mapping.h>
27 { .compatible = "qcom,ipq8074-wifi",
30 { .compatible = "qcom,ipq6018-wifi",
33 { .compatible = "qcom,wcn6750-wifi",
36 { .compatible = "qcom,ipq5018-wifi",
47 "misc-pulse1",
48 "misc-latch",
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| /freebsd/sys/contrib/device-tree/src/arm/intel/pxa/ |
| H A D | pxa25x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
14 * The muxing of external clocks/internal dividers for osc* clock
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
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| H A D | pxa27x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | apm-xgene-enet.txt | 1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
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| H A D | fsl-fman.txt | 5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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| /freebsd/sys/contrib/device-tree/src/mips/pic32/ |
| H A D | pic32mzda.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/microchip,pic32-clock.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&evic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
43 compatible = "microchip,pic32mzda-infra";
47 /* external clock input on TxCLKI pin */
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | dlg,da7280.txt | 4 - compatible: Should be "dlg,da7280".
5 - reg: Specifies the I2C slave address.
7 - interrupt-parent : Specifies the phandle of the interrupt controller to
8 which the IRQs from DA7280 are delivered to.
10 - dlg,actuator-type: Set Actuator type. it should be one of:
11 "LRA" - Linear Resonance Actuator type.
12 "ERM-bar" - Bar type Eccentric Rotating Mass.
13 "ERM-coin" - Coin type Eccentric Rotating Mass.
15 - dlg,const-op-mode: Haptic operation mode for FF_CONSTANT.
17 1 - Direct register override(DRO) mode triggered by i2c(default),
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | axp20x.txt | 4 axp152 (X-Powers)
5 axp202 (X-Powers)
6 axp209 (X-Powers)
7 axp221 (X-Powers)
8 axp223 (X-Powers)
9 axp803 (X-Powers)
10 axp806 (X-Powers)
11 axp809 (X-Powers)
12 axp813 (X-Powers)
20 - compatible: should be one of:
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /freebsd/sys/arm64/vmm/io/ |
| H A D | vgic_v3.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2020-2022 Andrew Turner
79 #define VGIC_SGI_NUM (GIC_LAST_SGI - GIC_FIRST_SGI + 1)
80 #define VGIC_PPI_NUM (GIC_LAST_PPI - GIC_FIRST_PPI + 1)
81 #define VGIC_SPI_NUM (GIC_LAST_SPI - GIC_FIRST_SPI + 1)
95 /* List of IRQs that are active or pending */
124 struct vgic_v3_irq *irqs; member
127 /* Per-CPU data not needed by EL2 */
144 /* How many IRQs we support (SGIs + PPIs + SPIs). Not including LPIs */
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| /freebsd/sys/arm64/cavium/ |
| H A D | thunder_pcie_pem.c | 1 /*-
29 /* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
110 * as we want. To support 32-bit cards let's assume
113 * 0x00000000 - 0x000FFFFF IO
114 * 0x00100000 - 0xFFFFFFFF Memory
217 * ARM64TODO Workaround - otherwise an em(4) interface appears to be in thunder_pem_maxslots()
239 *result = sc->id; in thunder_pem_read_ivar()
262 return (pci_domain_activate_bus(sc->id, child, r)); in thunder_pem_activate_resource()
280 return (pci_domain_deactivate_bus(sc->id, child, r)); in thunder_pem_deactivate_resource()
316 start = range_addr_pci_to_phys(sc->ranges, start); in thunder_pem_map_resource()
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| /freebsd/sys/dev/ahci/ |
| H A D | ahci.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
108 return ch->disablephy ? ATA_SC_DET_DISABLE : val; in ahci_ch_detval()
116 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); in ahci_ctlr_setup()
118 if (ctlr->ccc) { in ahci_ctlr_setup()
119 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); in ahci_ctlr_setup()
120 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, in ahci_ctlr_setup()
121 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | in ahci_ctlr_setup()
124 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & in ahci_ctlr_setup()
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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| /freebsd/sys/x86/x86/ |
| H A D | io_apic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
69 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other
70 * IRQs behave as PCI IRQs by default. We also assume that the pin for
165 if (src->io_edgetrigger) in _ioapic_eoi_source()
167 io = (struct ioapic *)isrc->is_pic; in _ioapic_eoi_source()
170 * Handle targeted EOI for level-triggered pins, if broadcast in _ioapic_eoi_source()
173 if (io->io_haseoi) { in _ioapic_eoi_source()
179 io->io_addr + IOAPIC_EOIR); in _ioapic_eoi_source()
180 *apic_eoi = src->io_vector; in _ioapic_eoi_source()
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