1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot/* The pxa3xx skeleton simply augments the 2xx version */ 3*f126890aSEmmanuel Vadot#include "pxa2xx.dtsi" 4*f126890aSEmmanuel Vadot#include "dt-bindings/clock/pxa-clock.h" 5*f126890aSEmmanuel Vadot 6*f126890aSEmmanuel Vadot/ { 7*f126890aSEmmanuel Vadot model = "Marvell PXA27x familiy SoC"; 8*f126890aSEmmanuel Vadot compatible = "marvell,pxa27x"; 9*f126890aSEmmanuel Vadot 10*f126890aSEmmanuel Vadot pxabus { 11*f126890aSEmmanuel Vadot pdma: dma-controller@40000000 { 12*f126890aSEmmanuel Vadot compatible = "marvell,pdma-1.0"; 13*f126890aSEmmanuel Vadot reg = <0x40000000 0x10000>; 14*f126890aSEmmanuel Vadot interrupts = <25>; 15*f126890aSEmmanuel Vadot #dma-cells = <2>; 16*f126890aSEmmanuel Vadot /* For backwards compatibility: */ 17*f126890aSEmmanuel Vadot #dma-channels = <32>; 18*f126890aSEmmanuel Vadot dma-channels = <32>; 19*f126890aSEmmanuel Vadot #dma-requests = <75>; 20*f126890aSEmmanuel Vadot dma-requests = <75>; 21*f126890aSEmmanuel Vadot status = "okay"; 22*f126890aSEmmanuel Vadot }; 23*f126890aSEmmanuel Vadot 24*f126890aSEmmanuel Vadot pxairq: interrupt-controller@40d00000 { 25*f126890aSEmmanuel Vadot marvell,intc-priority; 26*f126890aSEmmanuel Vadot marvell,intc-nr-irqs = <34>; 27*f126890aSEmmanuel Vadot }; 28*f126890aSEmmanuel Vadot 29*f126890aSEmmanuel Vadot pinctrl: pinctrl@40e00000 { 30*f126890aSEmmanuel Vadot reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4 31*f126890aSEmmanuel Vadot 0x40f00020 0x10>; 32*f126890aSEmmanuel Vadot compatible = "marvell,pxa27x-pinctrl"; 33*f126890aSEmmanuel Vadot }; 34*f126890aSEmmanuel Vadot 35*f126890aSEmmanuel Vadot gpio: gpio@40e00000 { 36*f126890aSEmmanuel Vadot compatible = "intel,pxa27x-gpio"; 37*f126890aSEmmanuel Vadot gpio-ranges = <&pinctrl 0 0 128>; 38*f126890aSEmmanuel Vadot clocks = <&clks CLK_NONE>; 39*f126890aSEmmanuel Vadot }; 40*f126890aSEmmanuel Vadot 41*f126890aSEmmanuel Vadot usb0: usb@4c000000 { 42*f126890aSEmmanuel Vadot compatible = "marvell,pxa-ohci"; 43*f126890aSEmmanuel Vadot reg = <0x4c000000 0x10000>; 44*f126890aSEmmanuel Vadot interrupts = <3>; 45*f126890aSEmmanuel Vadot clocks = <&clks CLK_USBHOST>; 46*f126890aSEmmanuel Vadot status = "disabled"; 47*f126890aSEmmanuel Vadot }; 48*f126890aSEmmanuel Vadot 49*f126890aSEmmanuel Vadot pwm0: pwm@40b00000 { 50*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 51*f126890aSEmmanuel Vadot reg = <0x40b00000 0x10>; 52*f126890aSEmmanuel Vadot #pwm-cells = <1>; 53*f126890aSEmmanuel Vadot clocks = <&clks CLK_PWM0>; 54*f126890aSEmmanuel Vadot }; 55*f126890aSEmmanuel Vadot 56*f126890aSEmmanuel Vadot pwm1: pwm@40b00010 { 57*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 58*f126890aSEmmanuel Vadot reg = <0x40b00010 0x10>; 59*f126890aSEmmanuel Vadot #pwm-cells = <1>; 60*f126890aSEmmanuel Vadot clocks = <&clks CLK_PWM1>; 61*f126890aSEmmanuel Vadot }; 62*f126890aSEmmanuel Vadot 63*f126890aSEmmanuel Vadot pwm2: pwm@40c00000 { 64*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 65*f126890aSEmmanuel Vadot reg = <0x40c00000 0x10>; 66*f126890aSEmmanuel Vadot #pwm-cells = <1>; 67*f126890aSEmmanuel Vadot clocks = <&clks CLK_PWM0>; 68*f126890aSEmmanuel Vadot }; 69*f126890aSEmmanuel Vadot 70*f126890aSEmmanuel Vadot pwm3: pwm@40c00010 { 71*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm"; 72*f126890aSEmmanuel Vadot reg = <0x40c00010 0x10>; 73*f126890aSEmmanuel Vadot #pwm-cells = <1>; 74*f126890aSEmmanuel Vadot clocks = <&clks CLK_PWM1>; 75*f126890aSEmmanuel Vadot }; 76*f126890aSEmmanuel Vadot 77*f126890aSEmmanuel Vadot pwri2c: i2c@40f00180 { 78*f126890aSEmmanuel Vadot compatible = "mrvl,pxa-i2c"; 79*f126890aSEmmanuel Vadot reg = <0x40f00180 0x24>; 80*f126890aSEmmanuel Vadot interrupts = <6>; 81*f126890aSEmmanuel Vadot clocks = <&clks CLK_PWRI2C>; 82*f126890aSEmmanuel Vadot #address-cells = <0x1>; 83*f126890aSEmmanuel Vadot #size-cells = <0>; 84*f126890aSEmmanuel Vadot status = "disabled"; 85*f126890aSEmmanuel Vadot }; 86*f126890aSEmmanuel Vadot 87*f126890aSEmmanuel Vadot pxa27x_udc: udc@40600000 { 88*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-udc"; 89*f126890aSEmmanuel Vadot reg = <0x40600000 0x10000>; 90*f126890aSEmmanuel Vadot interrupts = <11>; 91*f126890aSEmmanuel Vadot clocks = <&clks CLK_USB>; 92*f126890aSEmmanuel Vadot status = "disabled"; 93*f126890aSEmmanuel Vadot }; 94*f126890aSEmmanuel Vadot 95*f126890aSEmmanuel Vadot keypad: keypad@41500000 { 96*f126890aSEmmanuel Vadot compatible = "marvell,pxa27x-keypad"; 97*f126890aSEmmanuel Vadot reg = <0x41500000 0x4c>; 98*f126890aSEmmanuel Vadot interrupts = <4>; 99*f126890aSEmmanuel Vadot clocks = <&clks CLK_KEYPAD>; 100*f126890aSEmmanuel Vadot status = "disabled"; 101*f126890aSEmmanuel Vadot }; 102*f126890aSEmmanuel Vadot 103*f126890aSEmmanuel Vadot pxa_camera: imaging@50000000 { 104*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-qci"; 105*f126890aSEmmanuel Vadot reg = <0x50000000 0x1000>; 106*f126890aSEmmanuel Vadot interrupts = <33>; 107*f126890aSEmmanuel Vadot dmas = <&pdma 68 0 /* Y channel */ 108*f126890aSEmmanuel Vadot &pdma 69 0 /* U channel */ 109*f126890aSEmmanuel Vadot &pdma 70 0>; /* V channel */ 110*f126890aSEmmanuel Vadot dma-names = "CI_Y", "CI_U", "CI_V"; 111*f126890aSEmmanuel Vadot 112*f126890aSEmmanuel Vadot clocks = <&clks CLK_CAMERA>; 113*f126890aSEmmanuel Vadot clock-names = "ciclk"; 114*f126890aSEmmanuel Vadot clock-frequency = <5000000>; 115*f126890aSEmmanuel Vadot clock-output-names = "qci_mclk"; 116*f126890aSEmmanuel Vadot 117*f126890aSEmmanuel Vadot status = "disabled"; 118*f126890aSEmmanuel Vadot }; 119*f126890aSEmmanuel Vadot 120*f126890aSEmmanuel Vadot rtc@40900000 { 121*f126890aSEmmanuel Vadot clocks = <&clks CLK_OSC32k768>; 122*f126890aSEmmanuel Vadot }; 123*f126890aSEmmanuel Vadot }; 124*f126890aSEmmanuel Vadot 125*f126890aSEmmanuel Vadot clocks { 126*f126890aSEmmanuel Vadot /* 127*f126890aSEmmanuel Vadot * The muxing of external clocks/internal dividers for osc* clock 128*f126890aSEmmanuel Vadot * sources has been hidden under the carpet by now. 129*f126890aSEmmanuel Vadot */ 130*f126890aSEmmanuel Vadot #address-cells = <1>; 131*f126890aSEmmanuel Vadot #size-cells = <1>; 132*f126890aSEmmanuel Vadot ranges; 133*f126890aSEmmanuel Vadot 134*f126890aSEmmanuel Vadot clks: pxa2xx_clks@41300004 { 135*f126890aSEmmanuel Vadot compatible = "marvell,pxa270-clocks"; 136*f126890aSEmmanuel Vadot #clock-cells = <1>; 137*f126890aSEmmanuel Vadot status = "okay"; 138*f126890aSEmmanuel Vadot }; 139*f126890aSEmmanuel Vadot }; 140*f126890aSEmmanuel Vadot 141*f126890aSEmmanuel Vadot timer@40a00000 { 142*f126890aSEmmanuel Vadot compatible = "marvell,pxa-timer"; 143*f126890aSEmmanuel Vadot reg = <0x40a00000 0x20>; 144*f126890aSEmmanuel Vadot interrupts = <26>; 145*f126890aSEmmanuel Vadot clocks = <&clks CLK_OSTIMER>; 146*f126890aSEmmanuel Vadot status = "okay"; 147*f126890aSEmmanuel Vadot }; 148*f126890aSEmmanuel Vadot 149*f126890aSEmmanuel Vadot pxa270_opp_table: opp_table0 { 150*f126890aSEmmanuel Vadot compatible = "operating-points-v2"; 151*f126890aSEmmanuel Vadot 152*f126890aSEmmanuel Vadot opp-104000000 { 153*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <104000000>; 154*f126890aSEmmanuel Vadot opp-microvolt = <900000 900000 1705000>; 155*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 156*f126890aSEmmanuel Vadot }; 157*f126890aSEmmanuel Vadot opp-156000000 { 158*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <156000000>; 159*f126890aSEmmanuel Vadot opp-microvolt = <1000000 1000000 1705000>; 160*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 161*f126890aSEmmanuel Vadot }; 162*f126890aSEmmanuel Vadot opp-208000000 { 163*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <208000000>; 164*f126890aSEmmanuel Vadot opp-microvolt = <1180000 1180000 1705000>; 165*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 166*f126890aSEmmanuel Vadot }; 167*f126890aSEmmanuel Vadot opp-312000000 { 168*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <312000000>; 169*f126890aSEmmanuel Vadot opp-microvolt = <1250000 1250000 1705000>; 170*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 171*f126890aSEmmanuel Vadot }; 172*f126890aSEmmanuel Vadot opp-416000000 { 173*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <416000000>; 174*f126890aSEmmanuel Vadot opp-microvolt = <1350000 1350000 1705000>; 175*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 176*f126890aSEmmanuel Vadot }; 177*f126890aSEmmanuel Vadot opp-520000000 { 178*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <520000000>; 179*f126890aSEmmanuel Vadot opp-microvolt = <1450000 1450000 1705000>; 180*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 181*f126890aSEmmanuel Vadot }; 182*f126890aSEmmanuel Vadot opp-624000000 { 183*f126890aSEmmanuel Vadot opp-hz = /bits/ 64 <624000000>; 184*f126890aSEmmanuel Vadot opp-microvolt = <1550000 1550000 1705000>; 185*f126890aSEmmanuel Vadot clock-latency-ns = <20>; 186*f126890aSEmmanuel Vadot }; 187*f126890aSEmmanuel Vadot }; 188*f126890aSEmmanuel Vadot}; 189