| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynosautov9-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynosautov9-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanho Park <chanho61.park@samsung.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
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| H A D | samsung,exynos8895-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
19 as a fixed-rate clock in dts.
21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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| H A D | axis,artpec8-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Axis ARTPEC-8 SoC clock controller
10 - Jesper Nilsson <jesper.nilsson@axis.com>
13 ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)
16 The root clock in that root tree is an external clock: OSCCLK (25 MHz).
17 This external clock must be defined as a fixed-rate clock in dts.
19 CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
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| H A D | samsung,exynos850-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sam Protsenko <semen.protsenko@linaro.org>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
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| H A D | samsung,exynos990-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Igor Belwon <igor.belwon@mentallysanemainliners.org>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
18 is an external clock: OSCCLK (26 MHz). This external clock must be defined
19 as a fixed-rate clock in dts.
21 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
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| H A D | google,gs101-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
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| H A D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
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| H A D | samsung,exynos7885-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos7885-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dávid Virág <virag.david003@gmail.com>
11 - Chanwoo Choi <cw00.choi@samsung.com>
12 - Krzysztof Kozlowski <krzk@kernel.org>
13 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 - Tomasz Figa <tomasz.figa@gmail.com>
20 is an external clock: OSCCLK (26 MHz). This external clock must be defined
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| H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
16 connected with an external fixed rate oscillator, which signal is transformed
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
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| /linux/tools/perf/pmu-events/arch/x86/bonnell/ |
| H A D | other.json | 3 "BriefDescription": "Bus queue is empty.",
11 "BriefDescription": "Number of Bus Not Ready signals asserted.",
19 "BriefDescription": "Number of Bus Not Ready signals asserted.",
26 "BriefDescription": "Bus cycles while processor receives data.",
34 "BriefDescription": "Bus cycles when data is sent on the bus.",
42 "BriefDescription": "Bus cycles when data is sent on the bus.",
79 "BriefDescription": "IO requests waiting in the bus queue.",
87 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
95 "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
103 "BriefDescription": "Outstanding cacheable data read bus requests duration.",
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| /linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 access to attached peripherals through memory bus.
30 If you have an embedded system with an AMBA bus and a PL172
42 Used to configure the EBI (external bus interface) when the device-
43 tree is used. This bus supports NANDs, external ethernet controller,
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | renesas,bsc.yaml | 2 ---
3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
4 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 title: Renesas Bus State Controller (BSC)
9 - Geert Uytterhoeven <geert+renesas@glider.be>
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
13 Bridge", or "External Bus Interface") can be found in several Renesas ARM
14 SoCs. It provides an external bus for connecting multiple external
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
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| H A D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
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| /linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | global2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_read()
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_write()
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, in mv88e6xxx_g2_wait_bit()
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_mapping_write()
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_clear()
212 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
213 * Offset 0x0C: Cross-chip Port VLAN Data Register
228 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT in mv88e6xxx_g2_pvt_op()
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| /linux/drivers/bus/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Bus Devices
6 menu "Bus devices"
24 bool "ARM Integrator Logic Module bus"
29 Say y here to enable support for the ARM Logic Module bus
33 tristate "Broadcom STB GISB bus arbiter"
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | marvell,mv88e6xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
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| /linux/Documentation/driver-api/gpio/ |
| H A D | drivers-on-gpio.rst | 6 the right in-kernel and userspace APIs/ABIs for the job, and that these
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
24 - gpio_mouse: drivers/input/mouse/gpio_mouse.c is used to provide a mouse with
29 - gpio-beeper: drivers/input/misc/gpio-beeper.c is used to provide a beep from
30 an external speaker connected to a GPIO line. (If the beep is controlled by
31 off/on, for an actual PWM waveform, see pwm-gpio below.)
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| /linux/tools/testing/selftests/drivers/net/netdevsim/ |
| H A D | udp_tunnel_nic.sh | 2 # SPDX-License-Identifier: GPL-2.0-only
6 NSIM_DEV_SYS=/sys/bus/netdevsim/devices/netdevsim$NSIM_ID
30 [ -e /sys/class/net/$dev ] && ip link del dev $dev
36 if [ -e $NSIM_DEV_SYS ]; then
37 echo $NSIM_ID > /sys/bus/netdevsim/del_device
58 [ "$ipver" != '6' ] || ipfl="-6"
60 [[ ! "$flags" =~ "external" ]] && flags="$flags id $((VNI_GEN++))"
84 [ "$ipver" != '6' ] || ipfl="-6"
86 [[ ! "$flags" =~ "external" ]] && flags="$flags vni $((VNI_GEN++))"
118 echo -e "port: $((val >> 16))\ttype: $((val & 0xffff))"
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl,fman-mdio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
19 - fsl,fman-xmdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
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| /linux/include/soc/fsl/qe/ |
| H A D | immap_qe.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
65 __be32 cetsr2; /* QE time-stamp register 2 */
72 __be16 ceexe1; /* QE external request 1 event register */
74 __be16 ceexm1; /* QE external request 1 mask register */
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| /linux/Documentation/networking/dsa/ |
| H A D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-iio-adc-stm32 | 1 What: /sys/bus/iio/devices/triggerX/trigger_polarity
5 The STM32 ADC can be configured to use external trigger sources
7 conversions on external trigger by either:
9 - "rising-edge"
10 - "falling-edge"
11 - "both-edges".
17 What: /sys/bus/iio/devices/triggerX/trigger_polarity_available
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| /linux/Documentation/i2c/ |
| H A D | summary.rst | 6 a protocol developed by Philips. It is a two-wire protocol with variable
8 an inexpensive bus for connecting many types of devices with infrequent or
14 The latest official I2C specification is the `"I²C-bus specification and user
15 manual" (UM10204) <https://www.nxp.com/docs/en/user-guide/UM10204.pdf>`_
18 SMBus (System Management Bus) is based on the I2C protocol, and is mostly
25 Because the SMBus is mostly a subset of the generalized I2C bus, we can
34 The I2C bus connects one or more controller chips and one or more target chips.
36 .. kernel-figure:: i2c_bus.svg
37 :alt: Simple I2C bus with one controller and 3 targets
39 Simple I2C bus
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| /linux/arch/mips/include/asm/sgi/ |
| H A D | hpc3.h | 40 u32 _unused0[0x1000/4 - 2]; /* padding */
53 #define HPC3_PDMACTRL_RT 0x00000040 /* Use realtime GIO bus servicing */
54 #define HPC3_PDMACTRL_HW 0x0000ff00 /* DMA High-water mark */
58 u32 _unused1[0x1000/4 - 1]; /* padding */
61 /* The HPC3 SCSI registers, this does not include external ones. */
65 u32 _unused0[0x1000/4 - 2]; /* padding */
78 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
89 #define HPC3_SDCFG_HW 0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
105 u32 _unused1[0x1000/4 - 6]; /* padding */
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| /linux/arch/m68k/include/asm/ |
| H A D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
52 * 0xFFFFF1xx -- Chip-Select logic
58 * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
76 #define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */
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