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/linux/sound/pci/
H A Des1968.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Rewritted from card-es1938.c source.
27 * encoding. The codecs are almost always AC-97 compliant codecs,
88 #include <linux/dma-mapping.h>
102 #include <media/drv-intf/tea575x.h>
115 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
117 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ variable
118 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
119 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
120 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_flex_pipe.c1 // SPDX-License-Identifier: GPL-2.0
77 * ice_sect_id - returns section ID
90 * ice_hw_ptype_ena - check if the PTYPE is enabled or not
97 test_bit(ptype, hw->hw_ptype); in ice_hw_ptype_ena()
112 * ice_gen_key_word - generate 16-bits of a key/mask word
120 * This function generates 16-bits from a 8-bit value, an 8-bit don't care mask
121 * and an 8-bit never match mask. The 16-bits of output are divided into 8 bits
133 * ------------------------------
145 return -EIO; in ice_gen_key_word()
150 /* encode the 8 bits into 8-bit key and 8-bit key invert */ in ice_gen_key_word()
[all …]
/linux/drivers/staging/vc04_services/bcm2835-camera/
H A Dbcm2835-camera.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/dma-mapping.h>
19 #include <media/videobuf2-vmalloc.h>
20 #include <media/videobuf2-dma-contig.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ioctl.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-fh.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-common.h>
[all …]
/linux/drivers/clk/bcm/
H A Dclk-cygnus.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
23 #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ argument
24 { .offset = o, .en_shift = es, .high_shift = hs, \
36 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
39 #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } argument
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
65 .enable = ENABLE_VAL(0x4, 6, 0, 12),
[all …]
H A Dclk-nsp.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-nsp.h>
12 #include "clk-iproc.h"
26 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
50 .enable = ENABLE_VAL(0x4, 12, 6, 18),
56 .enable = ENABLE_VAL(0x4, 13, 7, 19),
62 .enable = ENABLE_VAL(0x4, 14, 8, 20),
68 .enable = ENABLE_VAL(0x4, 15, 9, 21),
[all …]
H A Dclk-ns2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-ns2.h>
12 #include "clk-iproc.h"
28 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ argument
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
57 .enable = ENABLE_VAL(0x0, 19, 13, 0),
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
69 .enable = ENABLE_VAL(0x0, 21, 15, 0),
75 .enable = ENABLE_VAL(0x0, 22, 16, 0),
[all …]
/linux/drivers/parisc/
H A Deisa_enumerator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * eisa_enumerator.c - provide support for EISA adapters in PA-RISC machines
36 * little-endian on the big-endian PAROSC */
92 res->name = name; in configure_memory()
93 res->start = mem_parent->start + get_24(buf+len+2); in configure_memory()
94 res->end = res->start + get_16(buf+len+5)*1024; in configure_memory()
95 res->flags = IORESOURCE_MEM; in configure_memory()
182 res->name = board; in configure_port()
183 res->start = get_16(buf+len+1); in configure_port()
184 res->end = get_16(buf+len+1)+(c&HPEE_PORT_SIZE_MASK)+1; in configure_port()
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
33 description: A connection of the 'enable' gpio line.
36 richtek,ld-pulse-delay-us:
[all …]
/linux/arch/powerpc/platforms/85xx/
H A Dxes_mpc85xx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * X-ES board-specific functionality
9 * Author: Nate Case <ncase@xes-inc.com>
24 #include <asm/pci-bridge.h>
36 #define MPC85xx_L2CTL_L2E 0x80000000 /* L2 enable */
81 * Legacy xMon firmware on some X-ES boards does not enable L2 in xes_mpc85xx_fixups()
84 for_each_node_by_name(np, "l2-cache-controller") { in xes_mpc85xx_fixups()
90 "fsl,mpc8548-l2-cache-controller") && in xes_mpc85xx_fixups()
92 "fsl,mpc8540-l2-cache-controller") && in xes_mpc85xx_fixups()
94 "fsl,mpc8560-l2-cache-controller")) in xes_mpc85xx_fixups()
[all …]
/linux/arch/x86/realmode/rm/
H A Dtrampoline_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
15 * with 16-bit addressing and 16-bit data. CS has some value
24 * --full-contents --reloc to make sure there are no relocation
33 #include <asm/processor-flags.h>
69 mov %ax, %es
91 # Enable protected mode
104 /* SEV-ES supports non-zero IP for entry points - no alignment needed */
112 mov %ax, %es
130 movl %edx, %es
150 * Memory encryption is enabled but the SME enable bit for this
[all …]
/linux/arch/x86/kernel/
H A Dhead_32.S1 /* SPDX-License-Identifier: GPL-2.0 */
20 #include <asm/asm-offsets.h>
22 #include <asm/processor-flags.h>
23 #include <asm/msr-index.h>
27 #include <asm/nospec-branch.h>
32 #define pa(X) ((X) - __PAGE_OFFSET)
48 * Worst-case size of the kernel mapping we need to make:
58 * 32-bit kernel entrypoint; only used by the boot CPU. On entry,
59 * %esi points to the real-mode code as a 32-bit pointer.
74 movl %eax,%es
[all …]
/linux/drivers/staging/vc04_services/vchiq-mmal/
H A Dmmal-msg.h1 /* SPDX-License-Identifier: GPL-2.0 */
37 #include "mmal-msg-common.h"
38 #include "mmal-msg-format.h"
39 #include "mmal-msg-port.h"
40 #include "mmal-vchiq.h"
75 MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */
112 u32 status; /* enum mmal_msg_status - how does this differ to
130 /* request and reply to VC to enable a component */
136 u32 status; /* The component enable status */
165 union mmal_es_specific_format es; /* es type specific data */ member
[all …]
/linux/fs/ext4/
H A Dsuper.c1 // SPDX-License-Identifier: GPL-2.0
7 * Laboratoire MASI - Institut Blaise Pascal
16 * Big-endian to little-endian byte-swapping/bitmaps by
28 #include <linux/backing-dev.h>
73 struct ext4_super_block *es);
75 struct ext4_super_block *es);
103 * mmap_lock -> sb_start_pagefault -> invalidate_lock (r) -> transaction start
104 * -> page lock -> i_data_sem (rw)
107 * sb_start_write -> i_mutex -> mmap_lock
108 * sb_start_write -> i_mutex -> transaction start -> page lock ->
[all …]
H A Dresize.c1 // SPDX-License-Identifier: GPL-2.0
29 kvfree(ptr->ptr); in ext4_rcu_ptr_callback()
38 ptr->ptr = to_free; in ext4_kvfree_array_rcu()
39 call_rcu(&ptr->rcu, ext4_rcu_ptr_callback); in ext4_kvfree_array_rcu()
52 return -EPERM; in ext4_resize_begin()
55 * If the reserved GDT blocks is non-zero, the resize_inode feature in ext4_resize_begin()
58 if (sbi->s_es->s_reserved_gdt_blocks && in ext4_resize_begin()
60 ext4_error(sb, "resize_inode disabled but reserved GDT blocks non-zero"); in ext4_resize_begin()
61 return -EFSCORRUPTED; in ext4_resize_begin()
69 if (EXT4_B2C(sbi, sbi->s_sbh->b_blocknr) != in ext4_resize_begin()
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dmvneta.c7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
156 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
158 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
270 * to cover all rate-limit values from 10Kbps up to 5Gbps
300 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
378 #define MVNETA_MAX_RX_BUF_SIZE (PAGE_SIZE - MVNETA_SKB_PAD)
381 (((rxd)->status & MVNETA_RXD_BM_POOL_MASK) >> MVNETA_RXD_BM_POOL_SHIFT)
481 struct mvneta_ethtool_stats es; member
490 /* Pointer to the CPU-local NAPI struct */
599 u32 reserved2; /* hw_cmd - (for future use, PMT) */
[all …]
/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-panda-es.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap4-panda-common.dtsi"
11 model = "TI OMAP4 PandaBoard-ES";
12 compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
20 ti,audio-routing =
33 pinctrl-single,pins = <
41 led_gpio_pins: gpio-led-pmx-pins {
42 pinctrl-single,pins = <
[all …]
/linux/drivers/rtc/
H A Drtc-ds2404.c1 // SPDX-License-Identifier: GPL-2.0
39 struct device *dev = &pdev->dev; in ds2404_gpio_map()
41 /* This will de-assert RESET, declare this GPIO as GPIOD_ACTIVE_LOW */ in ds2404_gpio_map()
42 chip->rst_gpiod = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW); in ds2404_gpio_map()
43 if (IS_ERR(chip->rst_gpiod)) in ds2404_gpio_map()
44 return PTR_ERR(chip->rst_gpiod); in ds2404_gpio_map()
46 chip->clk_gpiod = devm_gpiod_get(dev, "clk", GPIOD_OUT_HIGH); in ds2404_gpio_map()
47 if (IS_ERR(chip->clk_gpiod)) in ds2404_gpio_map()
48 return PTR_ERR(chip->clk_gpiod); in ds2404_gpio_map()
50 chip->dq_gpiod = devm_gpiod_get(dev, "dq", GPIOD_ASIS); in ds2404_gpio_map()
[all …]
/linux/drivers/spi/
H A Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
32 #include <linux/platform_data/spi-omap2-mcspi.h>
49 /* per-channel banks, 0x14 bytes each, first is: */
56 /* per-register bitmasks: */
154 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
161 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
167 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_write_cs_reg()
169 writel_relaxed(val, cs->base + idx); in mcspi_write_cs_reg()
174 struct omap2_mcspi_cs *cs = spi->controller_state; in mcspi_read_cs_reg()
[all …]
/linux/Documentation/sound/
H A Dalsa-configuration.rst2 Advanced Linux Sound Architecture - Driver Configuration guide
9 To enable ALSA support you need at least to build the kernel with
13 Enable "OSS API emulation" (``CONFIG_SND_OSSEMUL``) and both OSS mixer
17 SB Live! then you need to enable "Sequencer support"
20 To make ALSA debug messages more verbose, enable the "Verbose printk"
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
63 Module snd-pcm-oss
[all …]
/linux/arch/x86/boot/compressed/
H A Dhead_64.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 * head.S contains the 32-bit startup code.
14 * kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
33 #include <asm/processor-flags.h>
34 #include <asm/asm-offsets.h>
59 * from startup_32. This is the same as the link-time virtual address of X,
61 * assembler/linker that we do not want the actual run-time address of X. This
62 * prevents the linker from trying to create unwanted run-time relocation
65 * A reference X(%reg) will result in the link-time VA of X being stored with
66 * the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
[all …]
/linux/include/linux/
H A Dfsl_devices.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 PHY CLK to become stable - 10ms*/
30 * Each sub-arch has its own master list of unique devices and
31 * enumerates them by enum fsl_devices in a sub-arch specific header
40 * - platform data structures: <driver>_platform_data
41 * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42 * - platform data board flags: FSL_<driver>_BRD_<FLAG>
47 FSL_USB_VER_NONE = -1,
86 unsigned power_budget; /* hcd->power_budget */
89 unsigned es:1; /* need USBMODE:ES */ member
[all …]
/linux/drivers/soc/tegra/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
8 bool "Enable support for Tegra20 family"
25 bool "Enable support for Tegra30 family"
39 bool "Enable support for Tegra114 family"
51 bool "Enable support for Tegra124 family"
63 # 64-bit ARM SoCs
72 Enable support for NVIDIA Tegra132 SoC, based on the Denver
75 Tegra124's "4+1" Cortex-A15 CPU complex.
84 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
[all …]
/linux/arch/x86/platform/pvh/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define _pa(x) ((x) - __START_KERNEL_map)
12 #define rva(x) ((x) - pvh_start_xen)
22 #include <asm/processor-flags.h>
24 #include <asm/nospec-branch.h>
34 * - `ebx`: contains the physical memory address where the loader has placed
36 * - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
37 * - `cr4`: all bits are cleared.
38 * - `cs `: must be a 32-bit read/execute code segment with a base of `0`
40 * - `ds`, `es`: must be a 32-bit read/write data segment with a base of
[all …]
/linux/arch/mips/include/asm/mach-ath25/
H A Dath25_platform.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * This is board-specific data that is stored in a "fixed" location in flash.
11 * address(es).
32 #define BD_WLAN0 0x00000200 /* Enable WLAN0 */
35 #define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */

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