1 // SPDX-License-Identifier: GPL-2.0+
18 #define DRV_NAME "aspeed-edac"
24 #define ASPEED_MCR_ADDR_UNREC  0x58 /* address of first un-recoverable error */
45 	/* enable write to MCR register set */  in regmap_reg_write()
94 	struct csrow_info *csrow = mci->csrows[0];  in count_rec()
107 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, rec_cnt-1,  in count_rec()
108 				     page, offset, syndrome, 0, 0, -1,  in count_rec()
109 				     "address(es) not available", "");  in count_rec()
119 			     csrow->first_page + page, offset, syndrome,  in count_rec()
120 			     0, 0, -1, "", "");  in count_rec()
127 	struct csrow_info *csrow = mci->csrows[0];  in count_un_rec()
140 			     csrow->first_page + page, offset, syndrome,  in count_un_rec()
141 			     0, 0, -1, "", "");  in count_un_rec()
150 		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, un_rec_cnt-1,  in count_un_rec()
151 				     page, offset, syndrome, 0, 0, -1,  in count_un_rec()
152 				     "address(es) not available", "");  in count_un_rec()
165 	dev_dbg(mci->pdev, "received edac interrupt w/ mcr register 50: 0x%x\n",  in mcr_isr()
172 	dev_dbg(mci->pdev, "%d recoverable interrupts and %d unrecoverable interrupts\n",  in mcr_isr()
194 		dev_dbg(mci->pdev, "received edac interrupt, but did not find any ECC counters\n");  in mcr_isr()
197 	dev_dbg(mci->pdev, "edac interrupt handled. mcr reg 50 is now: 0x%x\n",  in mcr_isr()
211 	dev_dbg(&pdev->dev, "got irq %d\n", irq);  in config_irq()
215 	rc = devm_request_irq(&pdev->dev, irq, mcr_isr, IRQF_TRIGGER_HIGH,  in config_irq()
218 		dev_err(&pdev->dev, "unable to request irq %d\n", irq);  in config_irq()
222 	/* enable interrupts */  in config_irq()
233 	struct csrow_info *csrow = mci->csrows[0];  in init_csrows()
244 		dev_err(mci->pdev, "dt: missing /memory node\n");  in init_csrows()
245 		return -ENODEV;  in init_csrows()
253 		dev_err(mci->pdev, "dt: failed requesting resource for /memory node\n");  in init_csrows()
257 	dev_dbg(mci->pdev, "dt: /memory node resources: first page %pR, PAGE_SHIFT macro=0x%x\n",  in init_csrows()
260 	csrow->first_page = r.start >> PAGE_SHIFT;  in init_csrows()
262 	csrow->last_page = csrow->first_page + nr_pages - 1;  in init_csrows()
267 	dimm = csrow->channels[0]->dimm;  in init_csrows()
268 	dimm->mtype = dram_type;  in init_csrows()
269 	dimm->edac_mode = EDAC_SECDED;  in init_csrows()
270 	dimm->nr_pages = nr_pages / csrow->nr_channels;  in init_csrows()
272 	dev_dbg(mci->pdev, "initialized dimm with first_page=0x%lx and nr_pages=0x%x\n",  in init_csrows()
273 		csrow->first_page, nr_pages);  in init_csrows()
281 	struct device *dev = &pdev->dev;  in aspeed_probe()
300 		dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n");  in aspeed_probe()
301 		return -EPERM;  in aspeed_probe()
316 		return -ENOMEM;  in aspeed_probe()
318 	mci->pdev = &pdev->dev;  in aspeed_probe()
319 	mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;  in aspeed_probe()
320 	mci->edac_ctl_cap = EDAC_FLAG_SECDED;  in aspeed_probe()
321 	mci->edac_cap = EDAC_FLAG_SECDED;  in aspeed_probe()
322 	mci->scrub_cap = SCRUB_FLAG_HW_SRC;  in aspeed_probe()
323 	mci->scrub_mode = SCRUB_HW_SRC;  in aspeed_probe()
324 	mci->mod_name = DRV_NAME;  in aspeed_probe()
325 	mci->ctl_name = "MIC";  in aspeed_probe()
326 	mci->dev_name = dev_name(&pdev->dev);  in aspeed_probe()
330 		dev_err(&pdev->dev, "failed to init csrows\n");  in aspeed_probe()
339 		dev_err(&pdev->dev, "failed to register with EDAC core\n");  in aspeed_probe()
343 	/* register interrupt handler and enable interrupts */  in aspeed_probe()
346 		dev_err(&pdev->dev, "failed setting up irq\n");  in aspeed_probe()
353 	edac_mc_del_mc(&pdev->dev);  in aspeed_probe()
369 	mci = edac_mc_del_mc(&pdev->dev);  in aspeed_remove()
376 	{ .compatible = "aspeed,ast2400-sdram-edac" },
377 	{ .compatible = "aspeed,ast2500-sdram-edac" },
378 	{ .compatible = "aspeed,ast2600-sdram-edac" },