| H A D | intel_cx0_phy.c | 35 bool intel_encoder_is_c10phy(struct intel_encoder *encoder) 37 struct intel_display *display = to_intel_display(encoder); in intel_encoder_is_c10phy() argument 38 enum phy phy = intel_encoder_to_phy(encoder); in intel_encoder_is_c10phy() 62 static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder) in lane_mask_to_lane() 64 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); in intel_cx0_get_owned_lane_mask() argument 86 static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder) in assert_dc_off() 88 struct intel_display *display = to_intel_display(encoder); in intel_cx0_program_msgbus_timer() argument 93 XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane), in intel_cx0_program_msgbus_timer() 107 static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder) 109 struct intel_display *display = to_intel_display(encoder); in intel_cx0_phy_transaction_begin() argument 122 intel_cx0_phy_transaction_end(struct intel_encoder * encoder,intel_wakeref_t wakeref) intel_cx0_phy_transaction_end() argument 131 intel_clear_response_ready_flag(struct intel_encoder * encoder,int lane) intel_clear_response_ready_flag() argument 141 intel_cx0_bus_reset(struct intel_encoder * encoder,int lane) intel_cx0_bus_reset() argument 162 intel_cx0_wait_for_ack(struct intel_encoder * encoder,int command,int lane,u32 * val) intel_cx0_wait_for_ack() argument 210 __intel_cx0_read_once(struct intel_encoder * encoder,int lane,u16 addr) __intel_cx0_read_once() argument 250 __intel_cx0_read(struct intel_encoder * encoder,int lane,u16 addr) __intel_cx0_read() argument 274 intel_cx0_read(struct intel_encoder * encoder,u8 lane_mask,u16 addr) intel_cx0_read() argument 282 __intel_cx0_write_once(struct intel_encoder * encoder,int lane,u16 addr,u8 data,bool committed) __intel_cx0_write_once() argument 341 __intel_cx0_write(struct intel_encoder * encoder,int lane,u16 addr,u8 data,bool committed) __intel_cx0_write() argument 362 intel_cx0_write(struct intel_encoder * encoder,u8 lane_mask,u16 addr,u8 data,bool committed) intel_cx0_write() argument 371 intel_c20_sram_write(struct intel_encoder * encoder,int lane,u16 addr,u16 data) intel_c20_sram_write() argument 385 intel_c20_sram_read(struct intel_encoder * encoder,int lane,u16 addr) intel_c20_sram_read() argument 403 __intel_cx0_rmw(struct intel_encoder * encoder,int lane,u16 addr,u8 clear,u8 set,bool committed) __intel_cx0_rmw() argument 415 intel_cx0_rmw(struct intel_encoder * encoder,u8 lane_mask,u16 addr,u8 clear,u8 set,bool committed) intel_cx0_rmw() argument 452 intel_cx0_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_cx0_phy_set_signal_levels() argument 2014 intel_c10pll_tables_get(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder) intel_c10pll_tables_get() argument 2029 intel_cx0pll_update_ssc(struct intel_encoder * encoder,struct intel_cx0pll_state * pll_state,bool is_dp) intel_cx0pll_update_ssc() argument 2043 intel_c10pll_update_pll(struct intel_encoder * encoder,struct intel_cx0pll_state * pll_state) intel_c10pll_update_pll() argument 2057 intel_c10pll_calc_state_from_table(struct intel_encoder * encoder,const struct intel_c10pll_state * const * tables,bool is_dp,int port_clock,struct intel_cx0pll_state * pll_state) intel_c10pll_calc_state_from_table() argument 2079 intel_c10pll_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder) intel_c10pll_calc_state() argument 2106 intel_c10pll_readout_hw_state(struct intel_encoder * encoder,struct intel_c10pll_state * pll_state) intel_c10pll_readout_hw_state() argument 2133 intel_c10_pll_program(struct intel_display * display,struct intel_encoder * encoder,const struct intel_c10pll_state * pll_state) intel_c10_pll_program() argument 2308 intel_c20_pll_tables_get(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder) intel_c20_pll_tables_get() argument 2336 intel_c20pll_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder) intel_c20pll_calc_state() argument 2366 intel_cx0pll_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder) intel_cx0pll_calc_state() argument 2378 intel_c20pll_calc_port_clock(struct intel_encoder * encoder,const struct intel_c20pll_state * pll_state) intel_c20pll_calc_port_clock() argument 2423 intel_c20pll_readout_hw_state(struct intel_encoder * encoder,struct intel_c20pll_state * pll_state) intel_c20pll_readout_hw_state() argument 2602 intel_c20_protocol_switch_valid(struct intel_encoder * encoder) intel_c20_protocol_switch_valid() argument 2622 intel_c20_pll_program(struct intel_display * display,struct intel_encoder * encoder,const struct intel_c20pll_state * pll_state,bool is_dp,int port_clock) intel_c20_pll_program() argument 2725 intel_c10pll_calc_port_clock(struct intel_encoder * encoder,const struct intel_c10pll_state * pll_state) intel_c10pll_calc_port_clock() argument 2752 intel_program_port_clock_ctl(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state,bool is_dp,int port_clock,bool lane_reversal) intel_program_port_clock_ctl() argument 2809 intel_cx0_powerdown_change_sequence(struct intel_encoder * encoder,u8 lane_mask,u8 state) intel_cx0_powerdown_change_sequence() argument 2846 intel_cx0_setup_powerdown(struct intel_encoder * encoder) intel_cx0_setup_powerdown() argument 2883 intel_cx0_phy_lane_reset(struct intel_encoder * encoder,bool lane_reversal) intel_cx0_phy_lane_reset() argument 2943 intel_cx0_program_phy_lane(struct intel_encoder * encoder,int lane_count,bool lane_reversal) intel_cx0_program_phy_lane() argument 3009 __intel_cx0pll_enable(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state,bool is_dp,int port_clock,int lane_count) __intel_cx0pll_enable() argument 3091 intel_cx0pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_cx0pll_enable() argument 3099 intel_mtl_tbt_calc_port_clock(struct intel_encoder * encoder) intel_mtl_tbt_calc_port_clock() argument 3161 intel_mtl_tbt_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_mtl_tbt_pll_enable() argument 3220 intel_mtl_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_mtl_pll_enable() argument 3236 intel_lnl_mac_transmit_lfps(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_lnl_mac_transmit_lfps() argument 3271 cx0_power_control_disable_val(struct intel_encoder * encoder) cx0_power_control_disable_val() argument 3285 intel_cx0pll_disable(struct intel_encoder * encoder) intel_cx0pll_disable() argument 3336 intel_cx0_pll_is_enabled(struct intel_encoder * encoder) intel_cx0_pll_is_enabled() argument 3346 intel_mtl_tbt_pll_disable(struct intel_encoder * encoder) intel_mtl_tbt_pll_disable() argument 3385 intel_mtl_pll_disable(struct intel_encoder * encoder) intel_mtl_pll_disable() argument 3396 intel_mtl_port_pll_type(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state) intel_mtl_port_pll_type() argument 3418 intel_c10pll_state_verify(const struct intel_crtc_state * state,struct intel_crtc * crtc,struct intel_encoder * encoder,struct intel_c10pll_state * mpllb_hw_state) intel_c10pll_state_verify() argument 3445 intel_cx0pll_readout_hw_state(struct intel_encoder * encoder,struct intel_cx0pll_state * pll_state) intel_cx0pll_readout_hw_state() argument 3514 intel_cx0pll_calc_port_clock(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state) intel_cx0pll_calc_port_clock() argument 3525 intel_c20pll_state_verify(const struct intel_crtc_state * state,struct intel_crtc * crtc,struct intel_encoder * encoder,struct intel_c20pll_state * mpll_hw_state) intel_c20pll_state_verify() argument 3582 struct intel_encoder *encoder; intel_cx0pll_state_verify() local 3623 struct intel_encoder *encoder; intel_cx0_pll_power_save_wa() local [all...] |