13f03ced8SAlex Deucher /* 23f03ced8SAlex Deucher * Copyright 2007-11 Advanced Micro Devices, Inc. 33f03ced8SAlex Deucher * Copyright 2008 Red Hat Inc. 43f03ced8SAlex Deucher * 53f03ced8SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 63f03ced8SAlex Deucher * copy of this software and associated documentation files (the "Software"), 73f03ced8SAlex Deucher * to deal in the Software without restriction, including without limitation 83f03ced8SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 93f03ced8SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 103f03ced8SAlex Deucher * Software is furnished to do so, subject to the following conditions: 113f03ced8SAlex Deucher * 123f03ced8SAlex Deucher * The above copyright notice and this permission notice shall be included in 133f03ced8SAlex Deucher * all copies or substantial portions of the Software. 143f03ced8SAlex Deucher * 153f03ced8SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 163f03ced8SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 173f03ced8SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 183f03ced8SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 193f03ced8SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 203f03ced8SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 213f03ced8SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 223f03ced8SAlex Deucher * 233f03ced8SAlex Deucher * Authors: Dave Airlie 243f03ced8SAlex Deucher * Alex Deucher 253f03ced8SAlex Deucher */ 26c182615fSSam Ravnborg 27f3728734SAlex Deucher #include <linux/backlight.h> 28564d8a2cSMario Kleiner #include <linux/dmi.h> 292ef79416SThomas Zimmermann #include <linux/pci.h> 303f03ced8SAlex Deucher 31c182615fSSam Ravnborg #include <drm/drm_crtc_helper.h> 32e747235eSJani Nikula #include <drm/drm_edid.h> 33c182615fSSam Ravnborg #include <drm/drm_file.h> 34f7d17cd4SThomas Zimmermann #include <drm/drm_modeset_helper_vtables.h> 35c182615fSSam Ravnborg #include <drm/radeon_drm.h> 36c182615fSSam Ravnborg 371eb67781SHans de Goede #include <acpi/video.h> 381eb67781SHans de Goede 39c182615fSSam Ravnborg #include "atom.h" 4054ae7f99SLee Jones #include "radeon_atombios.h" 41c182615fSSam Ravnborg #include "radeon.h" 42c182615fSSam Ravnborg #include "radeon_asic.h" 43c182615fSSam Ravnborg #include "radeon_audio.h" 44c182615fSSam Ravnborg 453f03ced8SAlex Deucher extern int atom_debug; 463f03ced8SAlex Deucher 47f3728734SAlex Deucher static u8 48f3728734SAlex Deucher radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 49f3728734SAlex Deucher { 50f3728734SAlex Deucher u8 backlight_level; 51f3728734SAlex Deucher u32 bios_2_scratch; 52f3728734SAlex Deucher 53f3728734SAlex Deucher if (rdev->family >= CHIP_R600) 54f3728734SAlex Deucher bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 55f3728734SAlex Deucher else 56f3728734SAlex Deucher bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 57f3728734SAlex Deucher 58f3728734SAlex Deucher backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 59f3728734SAlex Deucher ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 60f3728734SAlex Deucher 61f3728734SAlex Deucher return backlight_level; 62f3728734SAlex Deucher } 63f3728734SAlex Deucher 64f3728734SAlex Deucher static void 65f3728734SAlex Deucher radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 66f3728734SAlex Deucher u8 backlight_level) 67f3728734SAlex Deucher { 68f3728734SAlex Deucher u32 bios_2_scratch; 69f3728734SAlex Deucher 70f3728734SAlex Deucher if (rdev->family >= CHIP_R600) 71f3728734SAlex Deucher bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 72f3728734SAlex Deucher else 73f3728734SAlex Deucher bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 74f3728734SAlex Deucher 75f3728734SAlex Deucher bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 76f3728734SAlex Deucher bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 77f3728734SAlex Deucher ATOM_S2_CURRENT_BL_LEVEL_MASK); 78f3728734SAlex Deucher 79f3728734SAlex Deucher if (rdev->family >= CHIP_R600) 80f3728734SAlex Deucher WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 81f3728734SAlex Deucher else 82f3728734SAlex Deucher WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 83f3728734SAlex Deucher } 84f3728734SAlex Deucher 856d92f81dSAlex Deucher u8 866d92f81dSAlex Deucher atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 876d92f81dSAlex Deucher { 886d92f81dSAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 896d92f81dSAlex Deucher struct radeon_device *rdev = dev->dev_private; 906d92f81dSAlex Deucher 916d92f81dSAlex Deucher if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 926d92f81dSAlex Deucher return 0; 936d92f81dSAlex Deucher 946d92f81dSAlex Deucher return radeon_atom_get_backlight_level_from_reg(rdev); 956d92f81dSAlex Deucher } 966d92f81dSAlex Deucher 97fda4b25cSLuca Tettamanti void 9837e9b6a6SAlex Deucher atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 99f3728734SAlex Deucher { 100f3728734SAlex Deucher struct drm_encoder *encoder = &radeon_encoder->base; 101f3728734SAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 102f3728734SAlex Deucher struct radeon_device *rdev = dev->dev_private; 103f3728734SAlex Deucher struct radeon_encoder_atom_dig *dig; 104f3728734SAlex Deucher DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 105f3728734SAlex Deucher int index; 106f3728734SAlex Deucher 10737e9b6a6SAlex Deucher if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 10837e9b6a6SAlex Deucher return; 10937e9b6a6SAlex Deucher 11037e9b6a6SAlex Deucher if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 11137e9b6a6SAlex Deucher radeon_encoder->enc_priv) { 112f3728734SAlex Deucher dig = radeon_encoder->enc_priv; 11337e9b6a6SAlex Deucher dig->backlight_level = level; 114f3728734SAlex Deucher radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 115f3728734SAlex Deucher 116f3728734SAlex Deucher switch (radeon_encoder->encoder_id) { 117f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 118f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 119f3728734SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 120f3728734SAlex Deucher if (dig->backlight_level == 0) { 121f3728734SAlex Deucher args.ucAction = ATOM_LCD_BLOFF; 122f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 123f3728734SAlex Deucher } else { 124f3728734SAlex Deucher args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 125f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 126f3728734SAlex Deucher args.ucAction = ATOM_LCD_BLON; 127f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 128f3728734SAlex Deucher } 129f3728734SAlex Deucher break; 130f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 131f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 132f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 133f3728734SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 134d3200be6SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 135f3728734SAlex Deucher if (dig->backlight_level == 0) 136f3728734SAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 137f3728734SAlex Deucher else { 138f3728734SAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 139f3728734SAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 140f3728734SAlex Deucher } 141f3728734SAlex Deucher break; 142f3728734SAlex Deucher default: 143f3728734SAlex Deucher break; 144f3728734SAlex Deucher } 145f3728734SAlex Deucher } 146f3728734SAlex Deucher } 147f3728734SAlex Deucher 148f3728734SAlex Deucher static u8 radeon_atom_bl_level(struct backlight_device *bd) 149f3728734SAlex Deucher { 150f3728734SAlex Deucher u8 level; 151f3728734SAlex Deucher 152f3728734SAlex Deucher /* Convert brightness to hardware level */ 153f3728734SAlex Deucher if (bd->props.brightness < 0) 154f3728734SAlex Deucher level = 0; 155f3728734SAlex Deucher else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 156f3728734SAlex Deucher level = RADEON_MAX_BL_LEVEL; 157f3728734SAlex Deucher else 158f3728734SAlex Deucher level = bd->props.brightness; 159f3728734SAlex Deucher 160f3728734SAlex Deucher return level; 161f3728734SAlex Deucher } 162f3728734SAlex Deucher 163f3728734SAlex Deucher static int radeon_atom_backlight_update_status(struct backlight_device *bd) 164f3728734SAlex Deucher { 165f3728734SAlex Deucher struct radeon_backlight_privdata *pdata = bl_get_data(bd); 166f3728734SAlex Deucher struct radeon_encoder *radeon_encoder = pdata->encoder; 167f3728734SAlex Deucher 16837e9b6a6SAlex Deucher atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 169f3728734SAlex Deucher 170f3728734SAlex Deucher return 0; 171f3728734SAlex Deucher } 172f3728734SAlex Deucher 173f3728734SAlex Deucher static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 174f3728734SAlex Deucher { 175f3728734SAlex Deucher struct radeon_backlight_privdata *pdata = bl_get_data(bd); 176f3728734SAlex Deucher struct radeon_encoder *radeon_encoder = pdata->encoder; 177f3728734SAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 178f3728734SAlex Deucher struct radeon_device *rdev = dev->dev_private; 179f3728734SAlex Deucher 180f3728734SAlex Deucher return radeon_atom_get_backlight_level_from_reg(rdev); 181f3728734SAlex Deucher } 182f3728734SAlex Deucher 183f3728734SAlex Deucher static const struct backlight_ops radeon_atom_backlight_ops = { 184f3728734SAlex Deucher .get_brightness = radeon_atom_backlight_get_brightness, 185f3728734SAlex Deucher .update_status = radeon_atom_backlight_update_status, 186f3728734SAlex Deucher }; 187f3728734SAlex Deucher 188f3728734SAlex Deucher void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 189f3728734SAlex Deucher struct drm_connector *drm_connector) 190f3728734SAlex Deucher { 191f3728734SAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 192f3728734SAlex Deucher struct radeon_device *rdev = dev->dev_private; 193f3728734SAlex Deucher struct backlight_device *bd; 194f3728734SAlex Deucher struct backlight_properties props; 195f3728734SAlex Deucher struct radeon_backlight_privdata *pdata; 196f3728734SAlex Deucher struct radeon_encoder_atom_dig *dig; 197614499b4SAlex Deucher char bl_name[16]; 198f3728734SAlex Deucher 19980101790SAlex Deucher /* Mac laptops with multiple GPUs use the gmux driver for backlight 20080101790SAlex Deucher * so don't register a backlight device 20180101790SAlex Deucher */ 20280101790SAlex Deucher if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 203364438fdSNicholas Bishop (rdev->pdev->device == 0x6741) && 204347eccc4SKendall Smith !(dmi_match(DMI_PRODUCT_NAME, "iMac12,1") || dmi_match(DMI_PRODUCT_NAME, "iMac12,2"))) 20580101790SAlex Deucher return; 20680101790SAlex Deucher 207f3728734SAlex Deucher if (!radeon_encoder->enc_priv) 208f3728734SAlex Deucher return; 209f3728734SAlex Deucher 210f3728734SAlex Deucher if (!rdev->is_atom_bios) 211f3728734SAlex Deucher return; 212f3728734SAlex Deucher 213f3728734SAlex Deucher if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 214f3728734SAlex Deucher return; 215f3728734SAlex Deucher 2161eb67781SHans de Goede if (!acpi_video_backlight_use_native()) { 2171eb67781SHans de Goede drm_info(dev, "Skipping radeon atom DIG backlight registration\n"); 2181eb67781SHans de Goede return; 2191eb67781SHans de Goede } 2201eb67781SHans de Goede 221f3728734SAlex Deucher pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 222f3728734SAlex Deucher if (!pdata) { 223f3728734SAlex Deucher DRM_ERROR("Memory allocation failed\n"); 224f3728734SAlex Deucher goto error; 225f3728734SAlex Deucher } 226f3728734SAlex Deucher 227f3728734SAlex Deucher memset(&props, 0, sizeof(props)); 228f3728734SAlex Deucher props.max_brightness = RADEON_MAX_BL_LEVEL; 229f3728734SAlex Deucher props.type = BACKLIGHT_RAW; 230614499b4SAlex Deucher snprintf(bl_name, sizeof(bl_name), 231614499b4SAlex Deucher "radeon_bl%d", dev->primary->index); 2325bdebb18SDave Airlie bd = backlight_device_register(bl_name, drm_connector->kdev, 233f3728734SAlex Deucher pdata, &radeon_atom_backlight_ops, &props); 234f3728734SAlex Deucher if (IS_ERR(bd)) { 235f3728734SAlex Deucher DRM_ERROR("Backlight registration failed\n"); 236f3728734SAlex Deucher goto error; 237f3728734SAlex Deucher } 238f3728734SAlex Deucher 239f3728734SAlex Deucher pdata->encoder = radeon_encoder; 240f3728734SAlex Deucher 241f3728734SAlex Deucher dig = radeon_encoder->enc_priv; 242f3728734SAlex Deucher dig->bl_dev = bd; 243f3728734SAlex Deucher 244f3728734SAlex Deucher bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 245201bb624SAlex Deucher /* Set a reasonable default here if the level is 0 otherwise 246201bb624SAlex Deucher * fbdev will attempt to turn the backlight on after console 247201bb624SAlex Deucher * unblanking and it will try and restore 0 which turns the backlight 248201bb624SAlex Deucher * off again. 249201bb624SAlex Deucher */ 250201bb624SAlex Deucher if (bd->props.brightness == 0) 251201bb624SAlex Deucher bd->props.brightness = RADEON_MAX_BL_LEVEL; 252f3728734SAlex Deucher bd->props.power = FB_BLANK_UNBLANK; 253f3728734SAlex Deucher backlight_update_status(bd); 254f3728734SAlex Deucher 255f3728734SAlex Deucher DRM_INFO("radeon atom DIG backlight initialized\n"); 2564cee6a90SAlex Deucher rdev->mode_info.bl_encoder = radeon_encoder; 257f3728734SAlex Deucher 258f3728734SAlex Deucher return; 259f3728734SAlex Deucher 260f3728734SAlex Deucher error: 261f3728734SAlex Deucher kfree(pdata); 262f3728734SAlex Deucher return; 263f3728734SAlex Deucher } 264f3728734SAlex Deucher 265f3728734SAlex Deucher static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 266f3728734SAlex Deucher { 267f3728734SAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 268f3728734SAlex Deucher struct radeon_device *rdev = dev->dev_private; 269f3728734SAlex Deucher struct backlight_device *bd = NULL; 270f3728734SAlex Deucher struct radeon_encoder_atom_dig *dig; 271f3728734SAlex Deucher 272f3728734SAlex Deucher if (!radeon_encoder->enc_priv) 273f3728734SAlex Deucher return; 274f3728734SAlex Deucher 275f3728734SAlex Deucher if (!rdev->is_atom_bios) 276f3728734SAlex Deucher return; 277f3728734SAlex Deucher 278f3728734SAlex Deucher if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 279f3728734SAlex Deucher return; 280f3728734SAlex Deucher 281f3728734SAlex Deucher dig = radeon_encoder->enc_priv; 282f3728734SAlex Deucher bd = dig->bl_dev; 283f3728734SAlex Deucher dig->bl_dev = NULL; 284f3728734SAlex Deucher 285f3728734SAlex Deucher if (bd) { 286f3728734SAlex Deucher struct radeon_legacy_backlight_privdata *pdata; 287f3728734SAlex Deucher 288f3728734SAlex Deucher pdata = bl_get_data(bd); 289f3728734SAlex Deucher backlight_device_unregister(bd); 290f3728734SAlex Deucher kfree(pdata); 291f3728734SAlex Deucher 292f3728734SAlex Deucher DRM_INFO("radeon atom LVDS backlight unloaded\n"); 293f3728734SAlex Deucher } 294f3728734SAlex Deucher } 295f3728734SAlex Deucher 2963f03ced8SAlex Deucher static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 297e811f5aeSLaurent Pinchart const struct drm_display_mode *mode, 2983f03ced8SAlex Deucher struct drm_display_mode *adjusted_mode) 2993f03ced8SAlex Deucher { 3003f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3013f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 3023f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 3033f03ced8SAlex Deucher 3043f03ced8SAlex Deucher /* set the active encoder to connector routing */ 3053f03ced8SAlex Deucher radeon_encoder_set_active_device(encoder); 3063f03ced8SAlex Deucher drm_mode_set_crtcinfo(adjusted_mode, 0); 3073f03ced8SAlex Deucher 3083f03ced8SAlex Deucher /* hw bug */ 3093f03ced8SAlex Deucher if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 3103f03ced8SAlex Deucher && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 3113f03ced8SAlex Deucher adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 3123f03ced8SAlex Deucher 3133104b812SAlex Deucher /* vertical FP must be at least 1 */ 3143104b812SAlex Deucher if (mode->crtc_vsync_start == mode->crtc_vdisplay) 3153104b812SAlex Deucher adjusted_mode->crtc_vsync_start++; 3163104b812SAlex Deucher 317da997620SAlex Deucher /* get the native mode for scaling */ 318da997620SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) { 3193f03ced8SAlex Deucher radeon_panel_mode_fixup(encoder, adjusted_mode); 320da997620SAlex Deucher } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 3213f03ced8SAlex Deucher struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 3223f03ced8SAlex Deucher if (tv_dac) { 3233f03ced8SAlex Deucher if (tv_dac->tv_std == TV_STD_NTSC || 3243f03ced8SAlex Deucher tv_dac->tv_std == TV_STD_NTSC_J || 3253f03ced8SAlex Deucher tv_dac->tv_std == TV_STD_PAL_M) 3263f03ced8SAlex Deucher radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 3273f03ced8SAlex Deucher else 3283f03ced8SAlex Deucher radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 3293f03ced8SAlex Deucher } 330da997620SAlex Deucher } else if (radeon_encoder->rmx_type != RMX_OFF) { 331da997620SAlex Deucher radeon_panel_mode_fixup(encoder, adjusted_mode); 3323f03ced8SAlex Deucher } 3333f03ced8SAlex Deucher 3343f03ced8SAlex Deucher if (ASIC_IS_DCE3(rdev) && 3353f03ced8SAlex Deucher ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3363f03ced8SAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 3373f03ced8SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 33893927f9cSAlex Deucher radeon_dp_set_link_config(connector, adjusted_mode); 3393f03ced8SAlex Deucher } 3403f03ced8SAlex Deucher 3413f03ced8SAlex Deucher return true; 3423f03ced8SAlex Deucher } 3433f03ced8SAlex Deucher 3443f03ced8SAlex Deucher static void 3453f03ced8SAlex Deucher atombios_dac_setup(struct drm_encoder *encoder, int action) 3463f03ced8SAlex Deucher { 3473f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 3483f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 3493f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3503f03ced8SAlex Deucher DAC_ENCODER_CONTROL_PS_ALLOCATION args; 3513f03ced8SAlex Deucher int index = 0; 3523f03ced8SAlex Deucher struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 3533f03ced8SAlex Deucher 3543f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 3553f03ced8SAlex Deucher 3563f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 3573f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 3583f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3593f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 3603f03ced8SAlex Deucher break; 3613f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 3623f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3633f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 3643f03ced8SAlex Deucher break; 3653f03ced8SAlex Deucher } 3663f03ced8SAlex Deucher 3673f03ced8SAlex Deucher args.ucAction = action; 3683f03ced8SAlex Deucher 3693f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 3703f03ced8SAlex Deucher args.ucDacStandard = ATOM_DAC1_PS2; 3713f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 3723f03ced8SAlex Deucher args.ucDacStandard = ATOM_DAC1_CV; 3733f03ced8SAlex Deucher else { 3743f03ced8SAlex Deucher switch (dac_info->tv_std) { 3753f03ced8SAlex Deucher case TV_STD_PAL: 3763f03ced8SAlex Deucher case TV_STD_PAL_M: 3773f03ced8SAlex Deucher case TV_STD_SCART_PAL: 3783f03ced8SAlex Deucher case TV_STD_SECAM: 3793f03ced8SAlex Deucher case TV_STD_PAL_CN: 3803f03ced8SAlex Deucher args.ucDacStandard = ATOM_DAC1_PAL; 3813f03ced8SAlex Deucher break; 3823f03ced8SAlex Deucher case TV_STD_NTSC: 3833f03ced8SAlex Deucher case TV_STD_NTSC_J: 3843f03ced8SAlex Deucher case TV_STD_PAL_60: 3853f03ced8SAlex Deucher default: 3863f03ced8SAlex Deucher args.ucDacStandard = ATOM_DAC1_NTSC; 3873f03ced8SAlex Deucher break; 3883f03ced8SAlex Deucher } 3893f03ced8SAlex Deucher } 3903f03ced8SAlex Deucher args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 3913f03ced8SAlex Deucher 392f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 3933f03ced8SAlex Deucher 3943f03ced8SAlex Deucher } 3953f03ced8SAlex Deucher 3963f03ced8SAlex Deucher static void 3973f03ced8SAlex Deucher atombios_tv_setup(struct drm_encoder *encoder, int action) 3983f03ced8SAlex Deucher { 3993f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 4003f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 4013f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4023f03ced8SAlex Deucher TV_ENCODER_CONTROL_PS_ALLOCATION args; 4033f03ced8SAlex Deucher int index = 0; 4043f03ced8SAlex Deucher struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 4053f03ced8SAlex Deucher 4063f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 4073f03ced8SAlex Deucher 4083f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 4093f03ced8SAlex Deucher 4103f03ced8SAlex Deucher args.sTVEncoder.ucAction = action; 4113f03ced8SAlex Deucher 4123f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 4133f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 4143f03ced8SAlex Deucher else { 4153f03ced8SAlex Deucher switch (dac_info->tv_std) { 4163f03ced8SAlex Deucher case TV_STD_NTSC: 4173f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 4183f03ced8SAlex Deucher break; 4193f03ced8SAlex Deucher case TV_STD_PAL: 4203f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 4213f03ced8SAlex Deucher break; 4223f03ced8SAlex Deucher case TV_STD_PAL_M: 4233f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 4243f03ced8SAlex Deucher break; 4253f03ced8SAlex Deucher case TV_STD_PAL_60: 4263f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 4273f03ced8SAlex Deucher break; 4283f03ced8SAlex Deucher case TV_STD_NTSC_J: 4293f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 4303f03ced8SAlex Deucher break; 4313f03ced8SAlex Deucher case TV_STD_SCART_PAL: 4323f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 4333f03ced8SAlex Deucher break; 4343f03ced8SAlex Deucher case TV_STD_SECAM: 4353f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 4363f03ced8SAlex Deucher break; 4373f03ced8SAlex Deucher case TV_STD_PAL_CN: 4383f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 4393f03ced8SAlex Deucher break; 4403f03ced8SAlex Deucher default: 4413f03ced8SAlex Deucher args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 4423f03ced8SAlex Deucher break; 4433f03ced8SAlex Deucher } 4443f03ced8SAlex Deucher } 4453f03ced8SAlex Deucher 4463f03ced8SAlex Deucher args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 4473f03ced8SAlex Deucher 448f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 4493f03ced8SAlex Deucher 4503f03ced8SAlex Deucher } 4513f03ced8SAlex Deucher 4521f0e2943SAlex Deucher static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 4531f0e2943SAlex Deucher { 4541f0e2943SAlex Deucher int bpc = 8; 4551f0e2943SAlex Deucher 4567d5a33b0SAlex Deucher if (encoder->crtc) { 4577d5a33b0SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 4587d5a33b0SAlex Deucher bpc = radeon_crtc->bpc; 4597d5a33b0SAlex Deucher } 4601f0e2943SAlex Deucher 4611f0e2943SAlex Deucher switch (bpc) { 4621f0e2943SAlex Deucher case 0: 4631f0e2943SAlex Deucher return PANEL_BPC_UNDEFINE; 4641f0e2943SAlex Deucher case 6: 4651f0e2943SAlex Deucher return PANEL_6BIT_PER_COLOR; 4661f0e2943SAlex Deucher case 8: 4671f0e2943SAlex Deucher default: 4681f0e2943SAlex Deucher return PANEL_8BIT_PER_COLOR; 4691f0e2943SAlex Deucher case 10: 4701f0e2943SAlex Deucher return PANEL_10BIT_PER_COLOR; 4711f0e2943SAlex Deucher case 12: 4721f0e2943SAlex Deucher return PANEL_12BIT_PER_COLOR; 4731f0e2943SAlex Deucher case 16: 4741f0e2943SAlex Deucher return PANEL_16BIT_PER_COLOR; 4751f0e2943SAlex Deucher } 4761f0e2943SAlex Deucher } 4771f0e2943SAlex Deucher 4783f03ced8SAlex Deucher union dvo_encoder_control { 4793f03ced8SAlex Deucher ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 4803f03ced8SAlex Deucher DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 4813f03ced8SAlex Deucher DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 482aea65641SAlex Deucher DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; 4833f03ced8SAlex Deucher }; 4843f03ced8SAlex Deucher 4853f03ced8SAlex Deucher void 4863f03ced8SAlex Deucher atombios_dvo_setup(struct drm_encoder *encoder, int action) 4873f03ced8SAlex Deucher { 4883f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 4893f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 4903f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 4913f03ced8SAlex Deucher union dvo_encoder_control args; 4923f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 49324153dd3SAlex Deucher uint8_t frev, crev; 4943f03ced8SAlex Deucher 4953f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 4963f03ced8SAlex Deucher 49724153dd3SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 49824153dd3SAlex Deucher return; 49924153dd3SAlex Deucher 500afceb931SAlex Deucher /* some R4xx chips have the wrong frev */ 501afceb931SAlex Deucher if (rdev->family <= CHIP_RV410) 502afceb931SAlex Deucher frev = 1; 503afceb931SAlex Deucher 50424153dd3SAlex Deucher switch (frev) { 50524153dd3SAlex Deucher case 1: 50624153dd3SAlex Deucher switch (crev) { 50724153dd3SAlex Deucher case 1: 50824153dd3SAlex Deucher /* R4xx, R5xx */ 50924153dd3SAlex Deucher args.ext_tmds.sXTmdsEncoder.ucEnable = action; 51024153dd3SAlex Deucher 5119aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 51224153dd3SAlex Deucher args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 51324153dd3SAlex Deucher 51424153dd3SAlex Deucher args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 51524153dd3SAlex Deucher break; 51624153dd3SAlex Deucher case 2: 51724153dd3SAlex Deucher /* RS600/690/740 */ 5183f03ced8SAlex Deucher args.dvo.sDVOEncoder.ucAction = action; 5193f03ced8SAlex Deucher args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 5203f03ced8SAlex Deucher /* DFP1, CRT1, TV1 depending on the type of port */ 5213f03ced8SAlex Deucher args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 5223f03ced8SAlex Deucher 5239aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 5243f03ced8SAlex Deucher args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 52524153dd3SAlex Deucher break; 52624153dd3SAlex Deucher case 3: 52724153dd3SAlex Deucher /* R6xx */ 52824153dd3SAlex Deucher args.dvo_v3.ucAction = action; 52924153dd3SAlex Deucher args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 53024153dd3SAlex Deucher args.dvo_v3.ucDVOConfig = 0; /* XXX */ 53124153dd3SAlex Deucher break; 532aea65641SAlex Deucher case 4: 533aea65641SAlex Deucher /* DCE8 */ 534aea65641SAlex Deucher args.dvo_v4.ucAction = action; 535aea65641SAlex Deucher args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 536aea65641SAlex Deucher args.dvo_v4.ucDVOConfig = 0; /* XXX */ 537aea65641SAlex Deucher args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 538aea65641SAlex Deucher break; 53924153dd3SAlex Deucher default: 54024153dd3SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 54124153dd3SAlex Deucher break; 54224153dd3SAlex Deucher } 54324153dd3SAlex Deucher break; 54424153dd3SAlex Deucher default: 54524153dd3SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 54624153dd3SAlex Deucher break; 5473f03ced8SAlex Deucher } 5483f03ced8SAlex Deucher 549f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 5503f03ced8SAlex Deucher } 5513f03ced8SAlex Deucher 5523f03ced8SAlex Deucher union lvds_encoder_control { 5533f03ced8SAlex Deucher LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 5543f03ced8SAlex Deucher LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 5553f03ced8SAlex Deucher }; 5563f03ced8SAlex Deucher 5573f03ced8SAlex Deucher void 5583f03ced8SAlex Deucher atombios_digital_setup(struct drm_encoder *encoder, int action) 5593f03ced8SAlex Deucher { 5603f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 5613f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 5623f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 5633f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 5643f03ced8SAlex Deucher union lvds_encoder_control args; 5653f03ced8SAlex Deucher int index = 0; 5663f03ced8SAlex Deucher int hdmi_detected = 0; 5673f03ced8SAlex Deucher uint8_t frev, crev; 5683f03ced8SAlex Deucher 5693f03ced8SAlex Deucher if (!dig) 5703f03ced8SAlex Deucher return; 5713f03ced8SAlex Deucher 5723f03ced8SAlex Deucher if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 5733f03ced8SAlex Deucher hdmi_detected = 1; 5743f03ced8SAlex Deucher 5753f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 5763f03ced8SAlex Deucher 5773f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 5783f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 5793f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 5803f03ced8SAlex Deucher break; 5813f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 5823f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 5833f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 5843f03ced8SAlex Deucher break; 5853f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 5863f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 5873f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 5883f03ced8SAlex Deucher else 5893f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 5903f03ced8SAlex Deucher break; 5913f03ced8SAlex Deucher } 5923f03ced8SAlex Deucher 5933f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 5943f03ced8SAlex Deucher return; 5953f03ced8SAlex Deucher 5963f03ced8SAlex Deucher switch (frev) { 5973f03ced8SAlex Deucher case 1: 5983f03ced8SAlex Deucher case 2: 5993f03ced8SAlex Deucher switch (crev) { 6003f03ced8SAlex Deucher case 1: 6013f03ced8SAlex Deucher args.v1.ucMisc = 0; 6023f03ced8SAlex Deucher args.v1.ucAction = action; 6033f03ced8SAlex Deucher if (hdmi_detected) 6043f03ced8SAlex Deucher args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 6053f03ced8SAlex Deucher args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 6063f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 6073f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 6083f03ced8SAlex Deucher args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 6093f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 6103f03ced8SAlex Deucher args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 6113f03ced8SAlex Deucher } else { 6123f03ced8SAlex Deucher if (dig->linkb) 6133f03ced8SAlex Deucher args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 6149aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 6153f03ced8SAlex Deucher args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 6163f03ced8SAlex Deucher /*if (pScrn->rgbBits == 8) */ 6173f03ced8SAlex Deucher args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 6183f03ced8SAlex Deucher } 6193f03ced8SAlex Deucher break; 6203f03ced8SAlex Deucher case 2: 6213f03ced8SAlex Deucher case 3: 6223f03ced8SAlex Deucher args.v2.ucMisc = 0; 6233f03ced8SAlex Deucher args.v2.ucAction = action; 6243f03ced8SAlex Deucher if (crev == 3) { 6253f03ced8SAlex Deucher if (dig->coherent_mode) 6263f03ced8SAlex Deucher args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 6273f03ced8SAlex Deucher } 6283f03ced8SAlex Deucher if (hdmi_detected) 6293f03ced8SAlex Deucher args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 6303f03ced8SAlex Deucher args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 6313f03ced8SAlex Deucher args.v2.ucTruncate = 0; 6323f03ced8SAlex Deucher args.v2.ucSpatial = 0; 6333f03ced8SAlex Deucher args.v2.ucTemporal = 0; 6343f03ced8SAlex Deucher args.v2.ucFRC = 0; 6353f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 6363f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 6373f03ced8SAlex Deucher args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 6383f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 6393f03ced8SAlex Deucher args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 6403f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 6413f03ced8SAlex Deucher args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 6423f03ced8SAlex Deucher } 6433f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 6443f03ced8SAlex Deucher args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 6453f03ced8SAlex Deucher if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 6463f03ced8SAlex Deucher args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 6473f03ced8SAlex Deucher if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 6483f03ced8SAlex Deucher args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 6493f03ced8SAlex Deucher } 6503f03ced8SAlex Deucher } else { 6513f03ced8SAlex Deucher if (dig->linkb) 6523f03ced8SAlex Deucher args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 6539aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 6543f03ced8SAlex Deucher args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 6553f03ced8SAlex Deucher } 6563f03ced8SAlex Deucher break; 6573f03ced8SAlex Deucher default: 6583f03ced8SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 6593f03ced8SAlex Deucher break; 6603f03ced8SAlex Deucher } 6613f03ced8SAlex Deucher break; 6623f03ced8SAlex Deucher default: 6633f03ced8SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 6643f03ced8SAlex Deucher break; 6653f03ced8SAlex Deucher } 6663f03ced8SAlex Deucher 667f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 6683f03ced8SAlex Deucher } 6693f03ced8SAlex Deucher 6703f03ced8SAlex Deucher int 6713f03ced8SAlex Deucher atombios_get_encoder_mode(struct drm_encoder *encoder) 6723f03ced8SAlex Deucher { 673e55bca26SSlava Grigorev struct drm_device *dev = encoder->dev; 674e55bca26SSlava Grigorev struct radeon_device *rdev = dev->dev_private; 6753f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 6763f03ced8SAlex Deucher struct drm_connector *connector; 6773f03ced8SAlex Deucher struct radeon_connector *radeon_connector; 6783f03ced8SAlex Deucher struct radeon_connector_atom_dig *dig_connector; 6793f03ced8SAlex Deucher 6803f03ced8SAlex Deucher /* dp bridges are always DP */ 6813f03ced8SAlex Deucher if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 6823f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DP; 6833f03ced8SAlex Deucher 6843f03ced8SAlex Deucher /* DVO is always DVO */ 685a59fbb8eSAlex Deucher if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 686a59fbb8eSAlex Deucher (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 6873f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DVO; 6883f03ced8SAlex Deucher 6893f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder(encoder); 6903f03ced8SAlex Deucher /* if we don't have an active device yet, just use one of 6913f03ced8SAlex Deucher * the connectors tied to the encoder. 6923f03ced8SAlex Deucher */ 6933f03ced8SAlex Deucher if (!connector) 6943f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder_init(encoder); 6953f03ced8SAlex Deucher radeon_connector = to_radeon_connector(connector); 6963f03ced8SAlex Deucher 6973f03ced8SAlex Deucher switch (connector->connector_type) { 6983f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_DVII: 6993f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 700108dc8e8SAlex Deucher if (radeon_audio != 0) { 701108dc8e8SAlex Deucher if (radeon_connector->use_digital && 702108dc8e8SAlex Deucher (radeon_connector->audio == RADEON_AUDIO_ENABLE)) 703108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 704*242136edSJani Nikula else if (connector->display_info.is_hdmi && 705108dc8e8SAlex Deucher (radeon_connector->audio == RADEON_AUDIO_AUTO)) 7063f03ced8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 707f92e70caSRafał Miłecki else if (radeon_connector->use_digital) 7083f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 7093f03ced8SAlex Deucher else 7103f03ced8SAlex Deucher return ATOM_ENCODER_MODE_CRT; 711108dc8e8SAlex Deucher } else if (radeon_connector->use_digital) { 712108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 713108dc8e8SAlex Deucher } else { 714108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_CRT; 715108dc8e8SAlex Deucher } 7163f03ced8SAlex Deucher break; 7173f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_DVID: 7183f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_HDMIA: 7193f03ced8SAlex Deucher default: 720108dc8e8SAlex Deucher if (radeon_audio != 0) { 721108dc8e8SAlex Deucher if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 722108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 723*242136edSJani Nikula else if (connector->display_info.is_hdmi && 724108dc8e8SAlex Deucher (radeon_connector->audio == RADEON_AUDIO_AUTO)) 7253f03ced8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 726f92e70caSRafał Miłecki else 7273f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 728108dc8e8SAlex Deucher } else { 729108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 730108dc8e8SAlex Deucher } 7313f03ced8SAlex Deucher break; 7323f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_LVDS: 7333f03ced8SAlex Deucher return ATOM_ENCODER_MODE_LVDS; 7343f03ced8SAlex Deucher break; 7353f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_DisplayPort: 7363f03ced8SAlex Deucher dig_connector = radeon_connector->con_priv; 7373f03ced8SAlex Deucher if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 738108dc8e8SAlex Deucher (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 7393473f542SAlex Deucher if (radeon_audio != 0 && 740*242136edSJani Nikula connector->display_info.has_audio && 7413473f542SAlex Deucher ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 742e55bca26SSlava Grigorev return ATOM_ENCODER_MODE_DP_AUDIO; 7433f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DP; 744108dc8e8SAlex Deucher } else if (radeon_audio != 0) { 745108dc8e8SAlex Deucher if (radeon_connector->audio == RADEON_AUDIO_ENABLE) 746108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 747*242136edSJani Nikula else if (connector->display_info.is_hdmi && 748108dc8e8SAlex Deucher (radeon_connector->audio == RADEON_AUDIO_AUTO)) 7493f03ced8SAlex Deucher return ATOM_ENCODER_MODE_HDMI; 750f92e70caSRafał Miłecki else 7513f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 752108dc8e8SAlex Deucher } else { 753108dc8e8SAlex Deucher return ATOM_ENCODER_MODE_DVI; 754108dc8e8SAlex Deucher } 7553f03ced8SAlex Deucher break; 7563f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_eDP: 7573473f542SAlex Deucher if (radeon_audio != 0 && 758*242136edSJani Nikula connector->display_info.has_audio && 7593473f542SAlex Deucher ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 760e55bca26SSlava Grigorev return ATOM_ENCODER_MODE_DP_AUDIO; 7613f03ced8SAlex Deucher return ATOM_ENCODER_MODE_DP; 7623f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_DVIA: 7633f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_VGA: 7643f03ced8SAlex Deucher return ATOM_ENCODER_MODE_CRT; 7653f03ced8SAlex Deucher break; 7663f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_Composite: 7673f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_SVIDEO: 7683f03ced8SAlex Deucher case DRM_MODE_CONNECTOR_9PinDIN: 7693f03ced8SAlex Deucher /* fix me */ 7703f03ced8SAlex Deucher return ATOM_ENCODER_MODE_TV; 7713f03ced8SAlex Deucher /*return ATOM_ENCODER_MODE_CV;*/ 7723f03ced8SAlex Deucher break; 7733f03ced8SAlex Deucher } 7743f03ced8SAlex Deucher } 7753f03ced8SAlex Deucher 7763f03ced8SAlex Deucher /* 7773f03ced8SAlex Deucher * DIG Encoder/Transmitter Setup 7783f03ced8SAlex Deucher * 7793f03ced8SAlex Deucher * DCE 3.0/3.1 7803f03ced8SAlex Deucher * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 7813f03ced8SAlex Deucher * Supports up to 3 digital outputs 7823f03ced8SAlex Deucher * - 2 DIG encoder blocks. 7833f03ced8SAlex Deucher * DIG1 can drive UNIPHY link A or link B 7843f03ced8SAlex Deucher * DIG2 can drive UNIPHY link B or LVTMA 7853f03ced8SAlex Deucher * 7863f03ced8SAlex Deucher * DCE 3.2 7873f03ced8SAlex Deucher * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 7883f03ced8SAlex Deucher * Supports up to 5 digital outputs 7893f03ced8SAlex Deucher * - 2 DIG encoder blocks. 7903f03ced8SAlex Deucher * DIG1/2 can drive UNIPHY0/1/2 link A or link B 7913f03ced8SAlex Deucher * 7922d415869SAlex Deucher * DCE 4.0/5.0/6.0 7933f03ced8SAlex Deucher * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 7943f03ced8SAlex Deucher * Supports up to 6 digital outputs 7953f03ced8SAlex Deucher * - 6 DIG encoder blocks. 7963f03ced8SAlex Deucher * - DIG to PHY mapping is hardcoded 7973f03ced8SAlex Deucher * DIG1 drives UNIPHY0 link A, A+B 7983f03ced8SAlex Deucher * DIG2 drives UNIPHY0 link B 7993f03ced8SAlex Deucher * DIG3 drives UNIPHY1 link A, A+B 8003f03ced8SAlex Deucher * DIG4 drives UNIPHY1 link B 8013f03ced8SAlex Deucher * DIG5 drives UNIPHY2 link A, A+B 8023f03ced8SAlex Deucher * DIG6 drives UNIPHY2 link B 8033f03ced8SAlex Deucher * 8043f03ced8SAlex Deucher * DCE 4.1 8053f03ced8SAlex Deucher * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 8063f03ced8SAlex Deucher * Supports up to 6 digital outputs 8073f03ced8SAlex Deucher * - 2 DIG encoder blocks. 8082d415869SAlex Deucher * llano 8093f03ced8SAlex Deucher * DIG1/2 can drive UNIPHY0/1/2 link A or link B 8102d415869SAlex Deucher * ontario 8112d415869SAlex Deucher * DIG1 drives UNIPHY0/1/2 link A 8122d415869SAlex Deucher * DIG2 drives UNIPHY0/1/2 link B 8133f03ced8SAlex Deucher * 8143f03ced8SAlex Deucher * Routing 8153f03ced8SAlex Deucher * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 8163f03ced8SAlex Deucher * Examples: 8173f03ced8SAlex Deucher * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 8183f03ced8SAlex Deucher * crtc1 -> dig1 -> UNIPHY0 link B -> DP 8193f03ced8SAlex Deucher * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 8203f03ced8SAlex Deucher * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 8213f03ced8SAlex Deucher */ 8223f03ced8SAlex Deucher 8233f03ced8SAlex Deucher union dig_encoder_control { 8243f03ced8SAlex Deucher DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 8253f03ced8SAlex Deucher DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 8263f03ced8SAlex Deucher DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 8273f03ced8SAlex Deucher DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 8283f03ced8SAlex Deucher }; 8293f03ced8SAlex Deucher 8303f03ced8SAlex Deucher void 831bf071900SDave Airlie atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override) 8323f03ced8SAlex Deucher { 8333f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 8343f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 8353f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 8363f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 8373f03ced8SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 8383f03ced8SAlex Deucher union dig_encoder_control args; 8393f03ced8SAlex Deucher int index = 0; 8403f03ced8SAlex Deucher uint8_t frev, crev; 8413f03ced8SAlex Deucher int dp_clock = 0; 8423f03ced8SAlex Deucher int dp_lane_count = 0; 8433f03ced8SAlex Deucher int hpd_id = RADEON_HPD_NONE; 8443f03ced8SAlex Deucher 8453f03ced8SAlex Deucher if (connector) { 8463f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 8473f03ced8SAlex Deucher struct radeon_connector_atom_dig *dig_connector = 8483f03ced8SAlex Deucher radeon_connector->con_priv; 8493f03ced8SAlex Deucher 8503f03ced8SAlex Deucher dp_clock = dig_connector->dp_clock; 8513f03ced8SAlex Deucher dp_lane_count = dig_connector->dp_lane_count; 8523f03ced8SAlex Deucher hpd_id = radeon_connector->hpd.hpd; 8533f03ced8SAlex Deucher } 8543f03ced8SAlex Deucher 8553f03ced8SAlex Deucher /* no dig encoder assigned */ 8563f03ced8SAlex Deucher if (dig->dig_encoder == -1) 8573f03ced8SAlex Deucher return; 8583f03ced8SAlex Deucher 8593f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 8603f03ced8SAlex Deucher 8613f03ced8SAlex Deucher if (ASIC_IS_DCE4(rdev)) 8623f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 8633f03ced8SAlex Deucher else { 8643f03ced8SAlex Deucher if (dig->dig_encoder) 8653f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 8663f03ced8SAlex Deucher else 8673f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 8683f03ced8SAlex Deucher } 8693f03ced8SAlex Deucher 8703f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 8713f03ced8SAlex Deucher return; 8723f03ced8SAlex Deucher 87358cdcb8bSAlex Deucher switch (frev) { 87458cdcb8bSAlex Deucher case 1: 87558cdcb8bSAlex Deucher switch (crev) { 87658cdcb8bSAlex Deucher case 1: 8773f03ced8SAlex Deucher args.v1.ucAction = action; 8783f03ced8SAlex Deucher args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 8793f03ced8SAlex Deucher if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 8803f03ced8SAlex Deucher args.v3.ucPanelMode = panel_mode; 8813f03ced8SAlex Deucher else 8823f03ced8SAlex Deucher args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 8833f03ced8SAlex Deucher 8843f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 8853f03ced8SAlex Deucher args.v1.ucLaneNum = dp_lane_count; 8869aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 8873f03ced8SAlex Deucher args.v1.ucLaneNum = 8; 8883f03ced8SAlex Deucher else 8893f03ced8SAlex Deucher args.v1.ucLaneNum = 4; 8903f03ced8SAlex Deucher 89158cdcb8bSAlex Deucher switch (radeon_encoder->encoder_id) { 89258cdcb8bSAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 89358cdcb8bSAlex Deucher args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 89458cdcb8bSAlex Deucher break; 89558cdcb8bSAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 89658cdcb8bSAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 89758cdcb8bSAlex Deucher args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 89858cdcb8bSAlex Deucher break; 89958cdcb8bSAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 90058cdcb8bSAlex Deucher args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 90158cdcb8bSAlex Deucher break; 90258cdcb8bSAlex Deucher } 90358cdcb8bSAlex Deucher if (dig->linkb) 90458cdcb8bSAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 90558cdcb8bSAlex Deucher else 90658cdcb8bSAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 907459ee1c3SMario Kleiner 908459ee1c3SMario Kleiner if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 909459ee1c3SMario Kleiner args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 910459ee1c3SMario Kleiner 91158cdcb8bSAlex Deucher break; 91258cdcb8bSAlex Deucher case 2: 91358cdcb8bSAlex Deucher case 3: 91458cdcb8bSAlex Deucher args.v3.ucAction = action; 91558cdcb8bSAlex Deucher args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 91658cdcb8bSAlex Deucher if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 91758cdcb8bSAlex Deucher args.v3.ucPanelMode = panel_mode; 91858cdcb8bSAlex Deucher else 91958cdcb8bSAlex Deucher args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 92058cdcb8bSAlex Deucher 9212f6fa79aSAlex Deucher if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 92258cdcb8bSAlex Deucher args.v3.ucLaneNum = dp_lane_count; 9239aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 92458cdcb8bSAlex Deucher args.v3.ucLaneNum = 8; 92558cdcb8bSAlex Deucher else 92658cdcb8bSAlex Deucher args.v3.ucLaneNum = 4; 92758cdcb8bSAlex Deucher 9282f6fa79aSAlex Deucher if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 92958cdcb8bSAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 930bf071900SDave Airlie if (enc_override != -1) 931bf071900SDave Airlie args.v3.acConfig.ucDigSel = enc_override; 932bf071900SDave Airlie else 93358cdcb8bSAlex Deucher args.v3.acConfig.ucDigSel = dig->dig_encoder; 9341f0e2943SAlex Deucher args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 93558cdcb8bSAlex Deucher break; 93658cdcb8bSAlex Deucher case 4: 93758cdcb8bSAlex Deucher args.v4.ucAction = action; 93858cdcb8bSAlex Deucher args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 93958cdcb8bSAlex Deucher if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 94058cdcb8bSAlex Deucher args.v4.ucPanelMode = panel_mode; 94158cdcb8bSAlex Deucher else 94258cdcb8bSAlex Deucher args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 94358cdcb8bSAlex Deucher 9442f6fa79aSAlex Deucher if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 94558cdcb8bSAlex Deucher args.v4.ucLaneNum = dp_lane_count; 9469aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 94758cdcb8bSAlex Deucher args.v4.ucLaneNum = 8; 94858cdcb8bSAlex Deucher else 94958cdcb8bSAlex Deucher args.v4.ucLaneNum = 4; 95058cdcb8bSAlex Deucher 9512f6fa79aSAlex Deucher if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 952e68adef8SAlex Deucher if (dp_clock == 540000) 9533f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 954e68adef8SAlex Deucher else if (dp_clock == 324000) 955e68adef8SAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; 956e68adef8SAlex Deucher else if (dp_clock == 270000) 957e68adef8SAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 958e68adef8SAlex Deucher else 959e68adef8SAlex Deucher args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; 9603f03ced8SAlex Deucher } 961bf071900SDave Airlie 962bf071900SDave Airlie if (enc_override != -1) 963bf071900SDave Airlie args.v4.acConfig.ucDigSel = enc_override; 964bf071900SDave Airlie else 9653f03ced8SAlex Deucher args.v4.acConfig.ucDigSel = dig->dig_encoder; 9661f0e2943SAlex Deucher args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 9673f03ced8SAlex Deucher if (hpd_id == RADEON_HPD_NONE) 9683f03ced8SAlex Deucher args.v4.ucHPD_ID = 0; 9693f03ced8SAlex Deucher else 9703f03ced8SAlex Deucher args.v4.ucHPD_ID = hpd_id + 1; 9713f03ced8SAlex Deucher break; 9723f03ced8SAlex Deucher default: 97358cdcb8bSAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 9743f03ced8SAlex Deucher break; 9753f03ced8SAlex Deucher } 9763f03ced8SAlex Deucher break; 97758cdcb8bSAlex Deucher default: 97858cdcb8bSAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 9793f03ced8SAlex Deucher break; 9803f03ced8SAlex Deucher } 9813f03ced8SAlex Deucher 982f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 9833f03ced8SAlex Deucher 9843f03ced8SAlex Deucher } 9853f03ced8SAlex Deucher 986bf071900SDave Airlie void 987bf071900SDave Airlie atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 988bf071900SDave Airlie { 989bf071900SDave Airlie atombios_dig_encoder_setup2(encoder, action, panel_mode, -1); 990bf071900SDave Airlie } 991bf071900SDave Airlie 9923f03ced8SAlex Deucher union dig_transmitter_control { 9933f03ced8SAlex Deucher DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 9943f03ced8SAlex Deucher DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 9953f03ced8SAlex Deucher DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 9963f03ced8SAlex Deucher DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 99747aef7a8SAlex Deucher DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 9983f03ced8SAlex Deucher }; 9993f03ced8SAlex Deucher 10003f03ced8SAlex Deucher void 1001bf071900SDave Airlie atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe) 10023f03ced8SAlex Deucher { 10033f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 10043f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 10053f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 10063f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 10073f03ced8SAlex Deucher struct drm_connector *connector; 10083f03ced8SAlex Deucher union dig_transmitter_control args; 10093f03ced8SAlex Deucher int index = 0; 10103f03ced8SAlex Deucher uint8_t frev, crev; 10113f03ced8SAlex Deucher bool is_dp = false; 10123f03ced8SAlex Deucher int pll_id = 0; 10133f03ced8SAlex Deucher int dp_clock = 0; 10143f03ced8SAlex Deucher int dp_lane_count = 0; 10153f03ced8SAlex Deucher int connector_object_id = 0; 10163f03ced8SAlex Deucher int igp_lane_info = 0; 10173f03ced8SAlex Deucher int dig_encoder = dig->dig_encoder; 101847aef7a8SAlex Deucher int hpd_id = RADEON_HPD_NONE; 10193f03ced8SAlex Deucher 10203f03ced8SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_INIT) { 10213f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder_init(encoder); 10223f03ced8SAlex Deucher /* just needed to avoid bailing in the encoder check. the encoder 10233f03ced8SAlex Deucher * isn't used for init 10243f03ced8SAlex Deucher */ 10253f03ced8SAlex Deucher dig_encoder = 0; 10263f03ced8SAlex Deucher } else 10273f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder(encoder); 10283f03ced8SAlex Deucher 10293f03ced8SAlex Deucher if (connector) { 10303f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 10313f03ced8SAlex Deucher struct radeon_connector_atom_dig *dig_connector = 10323f03ced8SAlex Deucher radeon_connector->con_priv; 10333f03ced8SAlex Deucher 103447aef7a8SAlex Deucher hpd_id = radeon_connector->hpd.hpd; 10353f03ced8SAlex Deucher dp_clock = dig_connector->dp_clock; 10363f03ced8SAlex Deucher dp_lane_count = dig_connector->dp_lane_count; 10373f03ced8SAlex Deucher connector_object_id = 10383f03ced8SAlex Deucher (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 10393f03ced8SAlex Deucher igp_lane_info = dig_connector->igp_lane_info; 10403f03ced8SAlex Deucher } 10413f03ced8SAlex Deucher 1042a3b08294SAlex Deucher if (encoder->crtc) { 1043a3b08294SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1044a3b08294SAlex Deucher pll_id = radeon_crtc->pll_id; 1045a3b08294SAlex Deucher } 1046a3b08294SAlex Deucher 10473f03ced8SAlex Deucher /* no dig encoder assigned */ 10483f03ced8SAlex Deucher if (dig_encoder == -1) 10493f03ced8SAlex Deucher return; 10503f03ced8SAlex Deucher 10513f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 10523f03ced8SAlex Deucher is_dp = true; 10533f03ced8SAlex Deucher 10543f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 10553f03ced8SAlex Deucher 10563f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 10573f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 10583f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 10593f03ced8SAlex Deucher break; 10603f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 10613f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 10623f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1063e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 10643f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 10653f03ced8SAlex Deucher break; 10663f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 10673f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 10683f03ced8SAlex Deucher break; 10693f03ced8SAlex Deucher } 10703f03ced8SAlex Deucher 10713f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 10723f03ced8SAlex Deucher return; 10733f03ced8SAlex Deucher 1074a3b08294SAlex Deucher switch (frev) { 1075a3b08294SAlex Deucher case 1: 1076a3b08294SAlex Deucher switch (crev) { 1077a3b08294SAlex Deucher case 1: 10783f03ced8SAlex Deucher args.v1.ucAction = action; 10793f03ced8SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_INIT) { 10803f03ced8SAlex Deucher args.v1.usInitInfo = cpu_to_le16(connector_object_id); 10813f03ced8SAlex Deucher } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 10823f03ced8SAlex Deucher args.v1.asMode.ucLaneSel = lane_num; 10833f03ced8SAlex Deucher args.v1.asMode.ucLaneSet = lane_set; 10843f03ced8SAlex Deucher } else { 10853f03ced8SAlex Deucher if (is_dp) 10866e76a2dfSAlex Deucher args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 10879aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 10883f03ced8SAlex Deucher args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 10893f03ced8SAlex Deucher else 10903f03ced8SAlex Deucher args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 10913f03ced8SAlex Deucher } 10923f03ced8SAlex Deucher 10933f03ced8SAlex Deucher args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 10943f03ced8SAlex Deucher 10953f03ced8SAlex Deucher if (dig_encoder) 10963f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 10973f03ced8SAlex Deucher else 10983f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 10993f03ced8SAlex Deucher 11003f03ced8SAlex Deucher if ((rdev->flags & RADEON_IS_IGP) && 11013f03ced8SAlex Deucher (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 11029aa59993SAlex Deucher if (is_dp || 11039aa59993SAlex Deucher !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 11043f03ced8SAlex Deucher if (igp_lane_info & 0x1) 11053f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 11063f03ced8SAlex Deucher else if (igp_lane_info & 0x2) 11073f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 11083f03ced8SAlex Deucher else if (igp_lane_info & 0x4) 11093f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 11103f03ced8SAlex Deucher else if (igp_lane_info & 0x8) 11113f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 11123f03ced8SAlex Deucher } else { 11133f03ced8SAlex Deucher if (igp_lane_info & 0x3) 11143f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 11153f03ced8SAlex Deucher else if (igp_lane_info & 0xc) 11163f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 11173f03ced8SAlex Deucher } 11183f03ced8SAlex Deucher } 11193f03ced8SAlex Deucher 11203f03ced8SAlex Deucher if (dig->linkb) 11213f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 11223f03ced8SAlex Deucher else 11233f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 11243f03ced8SAlex Deucher 11253f03ced8SAlex Deucher if (is_dp) 11263f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 11273f03ced8SAlex Deucher else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 11283f03ced8SAlex Deucher if (dig->coherent_mode) 11293f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 11309aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 11313f03ced8SAlex Deucher args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 11323f03ced8SAlex Deucher } 1133a3b08294SAlex Deucher break; 1134a3b08294SAlex Deucher case 2: 1135a3b08294SAlex Deucher args.v2.ucAction = action; 1136a3b08294SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1137a3b08294SAlex Deucher args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1138a3b08294SAlex Deucher } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1139a3b08294SAlex Deucher args.v2.asMode.ucLaneSel = lane_num; 1140a3b08294SAlex Deucher args.v2.asMode.ucLaneSet = lane_set; 1141a3b08294SAlex Deucher } else { 1142a3b08294SAlex Deucher if (is_dp) 11436e76a2dfSAlex Deucher args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 11449aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1145a3b08294SAlex Deucher args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1146a3b08294SAlex Deucher else 1147a3b08294SAlex Deucher args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1148a3b08294SAlex Deucher } 1149a3b08294SAlex Deucher 1150a3b08294SAlex Deucher args.v2.acConfig.ucEncoderSel = dig_encoder; 1151a3b08294SAlex Deucher if (dig->linkb) 1152a3b08294SAlex Deucher args.v2.acConfig.ucLinkSel = 1; 1153a3b08294SAlex Deucher 1154a3b08294SAlex Deucher switch (radeon_encoder->encoder_id) { 1155a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1156a3b08294SAlex Deucher args.v2.acConfig.ucTransmitterSel = 0; 1157a3b08294SAlex Deucher break; 1158a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1159a3b08294SAlex Deucher args.v2.acConfig.ucTransmitterSel = 1; 1160a3b08294SAlex Deucher break; 1161a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1162a3b08294SAlex Deucher args.v2.acConfig.ucTransmitterSel = 2; 1163a3b08294SAlex Deucher break; 1164a3b08294SAlex Deucher } 1165a3b08294SAlex Deucher 1166a3b08294SAlex Deucher if (is_dp) { 1167a3b08294SAlex Deucher args.v2.acConfig.fCoherentMode = 1; 1168a3b08294SAlex Deucher args.v2.acConfig.fDPConnector = 1; 1169a3b08294SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1170a3b08294SAlex Deucher if (dig->coherent_mode) 1171a3b08294SAlex Deucher args.v2.acConfig.fCoherentMode = 1; 11729aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1173a3b08294SAlex Deucher args.v2.acConfig.fDualLinkConnector = 1; 1174a3b08294SAlex Deucher } 1175a3b08294SAlex Deucher break; 1176a3b08294SAlex Deucher case 3: 1177a3b08294SAlex Deucher args.v3.ucAction = action; 1178a3b08294SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1179a3b08294SAlex Deucher args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1180a3b08294SAlex Deucher } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1181a3b08294SAlex Deucher args.v3.asMode.ucLaneSel = lane_num; 1182a3b08294SAlex Deucher args.v3.asMode.ucLaneSet = lane_set; 1183a3b08294SAlex Deucher } else { 1184a3b08294SAlex Deucher if (is_dp) 11856e76a2dfSAlex Deucher args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 11869aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1187a3b08294SAlex Deucher args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1188a3b08294SAlex Deucher else 1189a3b08294SAlex Deucher args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1190a3b08294SAlex Deucher } 1191a3b08294SAlex Deucher 1192a3b08294SAlex Deucher if (is_dp) 1193a3b08294SAlex Deucher args.v3.ucLaneNum = dp_lane_count; 11949aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1195a3b08294SAlex Deucher args.v3.ucLaneNum = 8; 1196a3b08294SAlex Deucher else 1197a3b08294SAlex Deucher args.v3.ucLaneNum = 4; 1198a3b08294SAlex Deucher 1199a3b08294SAlex Deucher if (dig->linkb) 1200a3b08294SAlex Deucher args.v3.acConfig.ucLinkSel = 1; 1201a3b08294SAlex Deucher if (dig_encoder & 1) 1202a3b08294SAlex Deucher args.v3.acConfig.ucEncoderSel = 1; 1203a3b08294SAlex Deucher 1204a3b08294SAlex Deucher /* Select the PLL for the PHY 1205a3b08294SAlex Deucher * DP PHY should be clocked from external src if there is 1206a3b08294SAlex Deucher * one. 1207a3b08294SAlex Deucher */ 1208a3b08294SAlex Deucher /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1209a3b08294SAlex Deucher if (is_dp && rdev->clock.dp_extclk) 1210a3b08294SAlex Deucher args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1211a3b08294SAlex Deucher else 1212a3b08294SAlex Deucher args.v3.acConfig.ucRefClkSource = pll_id; 1213a3b08294SAlex Deucher 1214a3b08294SAlex Deucher switch (radeon_encoder->encoder_id) { 1215a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1216a3b08294SAlex Deucher args.v3.acConfig.ucTransmitterSel = 0; 1217a3b08294SAlex Deucher break; 1218a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1219a3b08294SAlex Deucher args.v3.acConfig.ucTransmitterSel = 1; 1220a3b08294SAlex Deucher break; 1221a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1222a3b08294SAlex Deucher args.v3.acConfig.ucTransmitterSel = 2; 1223a3b08294SAlex Deucher break; 1224a3b08294SAlex Deucher } 1225a3b08294SAlex Deucher 1226a3b08294SAlex Deucher if (is_dp) 1227a3b08294SAlex Deucher args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1228a3b08294SAlex Deucher else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1229a3b08294SAlex Deucher if (dig->coherent_mode) 1230a3b08294SAlex Deucher args.v3.acConfig.fCoherentMode = 1; 12319aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1232a3b08294SAlex Deucher args.v3.acConfig.fDualLinkConnector = 1; 1233a3b08294SAlex Deucher } 1234a3b08294SAlex Deucher break; 1235a3b08294SAlex Deucher case 4: 1236a3b08294SAlex Deucher args.v4.ucAction = action; 1237a3b08294SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1238a3b08294SAlex Deucher args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1239a3b08294SAlex Deucher } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1240a3b08294SAlex Deucher args.v4.asMode.ucLaneSel = lane_num; 1241a3b08294SAlex Deucher args.v4.asMode.ucLaneSet = lane_set; 1242a3b08294SAlex Deucher } else { 1243a3b08294SAlex Deucher if (is_dp) 12446e76a2dfSAlex Deucher args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 12459aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1246a3b08294SAlex Deucher args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1247a3b08294SAlex Deucher else 1248a3b08294SAlex Deucher args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1249a3b08294SAlex Deucher } 1250a3b08294SAlex Deucher 1251a3b08294SAlex Deucher if (is_dp) 1252a3b08294SAlex Deucher args.v4.ucLaneNum = dp_lane_count; 12539aa59993SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1254a3b08294SAlex Deucher args.v4.ucLaneNum = 8; 1255a3b08294SAlex Deucher else 1256a3b08294SAlex Deucher args.v4.ucLaneNum = 4; 1257a3b08294SAlex Deucher 1258a3b08294SAlex Deucher if (dig->linkb) 1259a3b08294SAlex Deucher args.v4.acConfig.ucLinkSel = 1; 1260a3b08294SAlex Deucher if (dig_encoder & 1) 1261a3b08294SAlex Deucher args.v4.acConfig.ucEncoderSel = 1; 1262a3b08294SAlex Deucher 1263a3b08294SAlex Deucher /* Select the PLL for the PHY 1264a3b08294SAlex Deucher * DP PHY should be clocked from external src if there is 1265a3b08294SAlex Deucher * one. 1266a3b08294SAlex Deucher */ 1267a3b08294SAlex Deucher /* On DCE5 DCPLL usually generates the DP ref clock */ 1268a3b08294SAlex Deucher if (is_dp) { 1269a3b08294SAlex Deucher if (rdev->clock.dp_extclk) 1270a3b08294SAlex Deucher args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1271a3b08294SAlex Deucher else 1272a3b08294SAlex Deucher args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1273a3b08294SAlex Deucher } else 1274a3b08294SAlex Deucher args.v4.acConfig.ucRefClkSource = pll_id; 1275a3b08294SAlex Deucher 1276a3b08294SAlex Deucher switch (radeon_encoder->encoder_id) { 1277a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1278a3b08294SAlex Deucher args.v4.acConfig.ucTransmitterSel = 0; 1279a3b08294SAlex Deucher break; 1280a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1281a3b08294SAlex Deucher args.v4.acConfig.ucTransmitterSel = 1; 1282a3b08294SAlex Deucher break; 1283a3b08294SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1284a3b08294SAlex Deucher args.v4.acConfig.ucTransmitterSel = 2; 1285a3b08294SAlex Deucher break; 1286a3b08294SAlex Deucher } 1287a3b08294SAlex Deucher 1288a3b08294SAlex Deucher if (is_dp) 1289a3b08294SAlex Deucher args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1290a3b08294SAlex Deucher else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1291a3b08294SAlex Deucher if (dig->coherent_mode) 1292a3b08294SAlex Deucher args.v4.acConfig.fCoherentMode = 1; 12939aa59993SAlex Deucher if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1294a3b08294SAlex Deucher args.v4.acConfig.fDualLinkConnector = 1; 1295a3b08294SAlex Deucher } 1296a3b08294SAlex Deucher break; 129747aef7a8SAlex Deucher case 5: 129847aef7a8SAlex Deucher args.v5.ucAction = action; 129947aef7a8SAlex Deucher if (is_dp) 130047aef7a8SAlex Deucher args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 130147aef7a8SAlex Deucher else 130247aef7a8SAlex Deucher args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 130347aef7a8SAlex Deucher 130447aef7a8SAlex Deucher switch (radeon_encoder->encoder_id) { 130547aef7a8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 130647aef7a8SAlex Deucher if (dig->linkb) 130747aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 130847aef7a8SAlex Deucher else 130947aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 131047aef7a8SAlex Deucher break; 131147aef7a8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 131247aef7a8SAlex Deucher if (dig->linkb) 131347aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 131447aef7a8SAlex Deucher else 131547aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 131647aef7a8SAlex Deucher break; 131747aef7a8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 131847aef7a8SAlex Deucher if (dig->linkb) 131947aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 132047aef7a8SAlex Deucher else 132147aef7a8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 132247aef7a8SAlex Deucher break; 1323e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1324e68adef8SAlex Deucher args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; 1325e68adef8SAlex Deucher break; 132647aef7a8SAlex Deucher } 132747aef7a8SAlex Deucher if (is_dp) 132847aef7a8SAlex Deucher args.v5.ucLaneNum = dp_lane_count; 1329d03874c8SAlex Deucher else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 133047aef7a8SAlex Deucher args.v5.ucLaneNum = 8; 133147aef7a8SAlex Deucher else 133247aef7a8SAlex Deucher args.v5.ucLaneNum = 4; 133347aef7a8SAlex Deucher args.v5.ucConnObjId = connector_object_id; 133447aef7a8SAlex Deucher args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 133547aef7a8SAlex Deucher 133647aef7a8SAlex Deucher if (is_dp && rdev->clock.dp_extclk) 133747aef7a8SAlex Deucher args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 133847aef7a8SAlex Deucher else 133947aef7a8SAlex Deucher args.v5.asConfig.ucPhyClkSrcId = pll_id; 134047aef7a8SAlex Deucher 134147aef7a8SAlex Deucher if (is_dp) 134247aef7a8SAlex Deucher args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 134347aef7a8SAlex Deucher else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 134447aef7a8SAlex Deucher if (dig->coherent_mode) 134547aef7a8SAlex Deucher args.v5.asConfig.ucCoherentMode = 1; 134647aef7a8SAlex Deucher } 134747aef7a8SAlex Deucher if (hpd_id == RADEON_HPD_NONE) 134847aef7a8SAlex Deucher args.v5.asConfig.ucHPDSel = 0; 134947aef7a8SAlex Deucher else 135047aef7a8SAlex Deucher args.v5.asConfig.ucHPDSel = hpd_id + 1; 1351bf071900SDave Airlie args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder); 135247aef7a8SAlex Deucher args.v5.ucDPLaneSet = lane_set; 135347aef7a8SAlex Deucher break; 1354a3b08294SAlex Deucher default: 1355a3b08294SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1356a3b08294SAlex Deucher break; 1357a3b08294SAlex Deucher } 1358a3b08294SAlex Deucher break; 1359a3b08294SAlex Deucher default: 1360a3b08294SAlex Deucher DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1361a3b08294SAlex Deucher break; 13623f03ced8SAlex Deucher } 13633f03ced8SAlex Deucher 1364f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 13653f03ced8SAlex Deucher } 13663f03ced8SAlex Deucher 1367bf071900SDave Airlie void 1368bf071900SDave Airlie atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 1369bf071900SDave Airlie { 1370bf071900SDave Airlie atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1); 1371bf071900SDave Airlie } 1372bf071900SDave Airlie 13733f03ced8SAlex Deucher bool 13743f03ced8SAlex Deucher atombios_set_edp_panel_power(struct drm_connector *connector, int action) 13753f03ced8SAlex Deucher { 13763f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 13773f03ced8SAlex Deucher struct drm_device *dev = radeon_connector->base.dev; 13783f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 13793f03ced8SAlex Deucher union dig_transmitter_control args; 13803f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 13813f03ced8SAlex Deucher uint8_t frev, crev; 13823f03ced8SAlex Deucher 13833f03ced8SAlex Deucher if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 13843f03ced8SAlex Deucher goto done; 13853f03ced8SAlex Deucher 13863f03ced8SAlex Deucher if (!ASIC_IS_DCE4(rdev)) 13873f03ced8SAlex Deucher goto done; 13883f03ced8SAlex Deucher 13893f03ced8SAlex Deucher if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 13903f03ced8SAlex Deucher (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 13913f03ced8SAlex Deucher goto done; 13923f03ced8SAlex Deucher 13933f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 13943f03ced8SAlex Deucher goto done; 13953f03ced8SAlex Deucher 13963f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 13973f03ced8SAlex Deucher 13983f03ced8SAlex Deucher args.v1.ucAction = action; 13993f03ced8SAlex Deucher 1400f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 14013f03ced8SAlex Deucher 14023f03ced8SAlex Deucher /* wait for the panel to power up */ 14033f03ced8SAlex Deucher if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 14043f03ced8SAlex Deucher int i; 14053f03ced8SAlex Deucher 14063f03ced8SAlex Deucher for (i = 0; i < 300; i++) { 14073f03ced8SAlex Deucher if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 14083f03ced8SAlex Deucher return true; 14093f03ced8SAlex Deucher mdelay(1); 14103f03ced8SAlex Deucher } 14113f03ced8SAlex Deucher return false; 14123f03ced8SAlex Deucher } 14133f03ced8SAlex Deucher done: 14143f03ced8SAlex Deucher return true; 14153f03ced8SAlex Deucher } 14163f03ced8SAlex Deucher 14173f03ced8SAlex Deucher union external_encoder_control { 14183f03ced8SAlex Deucher EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 14193f03ced8SAlex Deucher EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 14203f03ced8SAlex Deucher }; 14213f03ced8SAlex Deucher 14223f03ced8SAlex Deucher static void 14233f03ced8SAlex Deucher atombios_external_encoder_setup(struct drm_encoder *encoder, 14243f03ced8SAlex Deucher struct drm_encoder *ext_encoder, 14253f03ced8SAlex Deucher int action) 14263f03ced8SAlex Deucher { 14273f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 14283f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 14293f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 14303f03ced8SAlex Deucher struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 14313f03ced8SAlex Deucher union external_encoder_control args; 14323f03ced8SAlex Deucher struct drm_connector *connector; 14333f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 14343f03ced8SAlex Deucher u8 frev, crev; 14353f03ced8SAlex Deucher int dp_clock = 0; 14363f03ced8SAlex Deucher int dp_lane_count = 0; 14373f03ced8SAlex Deucher int connector_object_id = 0; 14383f03ced8SAlex Deucher u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 14393f03ced8SAlex Deucher 14403f03ced8SAlex Deucher if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 14413f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder_init(encoder); 14423f03ced8SAlex Deucher else 14433f03ced8SAlex Deucher connector = radeon_get_connector_for_encoder(encoder); 14443f03ced8SAlex Deucher 14453f03ced8SAlex Deucher if (connector) { 14463f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 14473f03ced8SAlex Deucher struct radeon_connector_atom_dig *dig_connector = 14483f03ced8SAlex Deucher radeon_connector->con_priv; 14493f03ced8SAlex Deucher 14503f03ced8SAlex Deucher dp_clock = dig_connector->dp_clock; 14513f03ced8SAlex Deucher dp_lane_count = dig_connector->dp_lane_count; 14523f03ced8SAlex Deucher connector_object_id = 14533f03ced8SAlex Deucher (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 14543f03ced8SAlex Deucher } 14553f03ced8SAlex Deucher 14563f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 14573f03ced8SAlex Deucher 14583f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 14593f03ced8SAlex Deucher return; 14603f03ced8SAlex Deucher 14613f03ced8SAlex Deucher switch (frev) { 14623f03ced8SAlex Deucher case 1: 14633f03ced8SAlex Deucher /* no params on frev 1 */ 14643f03ced8SAlex Deucher break; 14653f03ced8SAlex Deucher case 2: 14663f03ced8SAlex Deucher switch (crev) { 14673f03ced8SAlex Deucher case 1: 14683f03ced8SAlex Deucher case 2: 14693f03ced8SAlex Deucher args.v1.sDigEncoder.ucAction = action; 14703f03ced8SAlex Deucher args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 14713f03ced8SAlex Deucher args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 14723f03ced8SAlex Deucher 14733f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 14743f03ced8SAlex Deucher if (dp_clock == 270000) 14753f03ced8SAlex Deucher args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 14763f03ced8SAlex Deucher args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 14779aa59993SAlex Deucher } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 14783f03ced8SAlex Deucher args.v1.sDigEncoder.ucLaneNum = 8; 14793f03ced8SAlex Deucher else 14803f03ced8SAlex Deucher args.v1.sDigEncoder.ucLaneNum = 4; 14813f03ced8SAlex Deucher break; 14823f03ced8SAlex Deucher case 3: 14833f03ced8SAlex Deucher args.v3.sExtEncoder.ucAction = action; 14843f03ced8SAlex Deucher if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 14853f03ced8SAlex Deucher args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 14863f03ced8SAlex Deucher else 14873f03ced8SAlex Deucher args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 14883f03ced8SAlex Deucher args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 14893f03ced8SAlex Deucher 14903f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 14913f03ced8SAlex Deucher if (dp_clock == 270000) 14923f03ced8SAlex Deucher args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 14933f03ced8SAlex Deucher else if (dp_clock == 540000) 14943f03ced8SAlex Deucher args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 14953f03ced8SAlex Deucher args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 14969aa59993SAlex Deucher } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 14973f03ced8SAlex Deucher args.v3.sExtEncoder.ucLaneNum = 8; 14983f03ced8SAlex Deucher else 14993f03ced8SAlex Deucher args.v3.sExtEncoder.ucLaneNum = 4; 15003f03ced8SAlex Deucher switch (ext_enum) { 15013f03ced8SAlex Deucher case GRAPH_OBJECT_ENUM_ID1: 15023f03ced8SAlex Deucher args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 15033f03ced8SAlex Deucher break; 15043f03ced8SAlex Deucher case GRAPH_OBJECT_ENUM_ID2: 15053f03ced8SAlex Deucher args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 15063f03ced8SAlex Deucher break; 15073f03ced8SAlex Deucher case GRAPH_OBJECT_ENUM_ID3: 15083f03ced8SAlex Deucher args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 15093f03ced8SAlex Deucher break; 15103f03ced8SAlex Deucher } 15111f0e2943SAlex Deucher args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 15123f03ced8SAlex Deucher break; 15133f03ced8SAlex Deucher default: 15143f03ced8SAlex Deucher DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 15153f03ced8SAlex Deucher return; 15163f03ced8SAlex Deucher } 15173f03ced8SAlex Deucher break; 15183f03ced8SAlex Deucher default: 15193f03ced8SAlex Deucher DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 15203f03ced8SAlex Deucher return; 15213f03ced8SAlex Deucher } 1522f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 15233f03ced8SAlex Deucher } 15243f03ced8SAlex Deucher 15253f03ced8SAlex Deucher static void 15263f03ced8SAlex Deucher atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 15273f03ced8SAlex Deucher { 15283f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 15293f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 15303f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 15313f03ced8SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 15323f03ced8SAlex Deucher ENABLE_YUV_PS_ALLOCATION args; 15333f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 15343f03ced8SAlex Deucher uint32_t temp, reg; 15353f03ced8SAlex Deucher 15363f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 15373f03ced8SAlex Deucher 15383f03ced8SAlex Deucher if (rdev->family >= CHIP_R600) 15393f03ced8SAlex Deucher reg = R600_BIOS_3_SCRATCH; 15403f03ced8SAlex Deucher else 15413f03ced8SAlex Deucher reg = RADEON_BIOS_3_SCRATCH; 15423f03ced8SAlex Deucher 15433f03ced8SAlex Deucher /* XXX: fix up scratch reg handling */ 15443f03ced8SAlex Deucher temp = RREG32(reg); 15453f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 15463f03ced8SAlex Deucher WREG32(reg, (ATOM_S3_TV1_ACTIVE | 15473f03ced8SAlex Deucher (radeon_crtc->crtc_id << 18))); 15483f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 15493f03ced8SAlex Deucher WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 15503f03ced8SAlex Deucher else 15513f03ced8SAlex Deucher WREG32(reg, 0); 15523f03ced8SAlex Deucher 15533f03ced8SAlex Deucher if (enable) 15543f03ced8SAlex Deucher args.ucEnable = ATOM_ENABLE; 15553f03ced8SAlex Deucher args.ucCRTC = radeon_crtc->crtc_id; 15563f03ced8SAlex Deucher 1557f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 15583f03ced8SAlex Deucher 15593f03ced8SAlex Deucher WREG32(reg, temp); 15603f03ced8SAlex Deucher } 15613f03ced8SAlex Deucher 15623f03ced8SAlex Deucher static void 15633f03ced8SAlex Deucher radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 15643f03ced8SAlex Deucher { 15653f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 15663f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 15673f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 15683f03ced8SAlex Deucher DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 15693f03ced8SAlex Deucher int index = 0; 15703f03ced8SAlex Deucher 15713f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 15723f03ced8SAlex Deucher 15733f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 15743f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 15753f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 15763f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 15773f03ced8SAlex Deucher break; 15783f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 15793f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 15803f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 15813f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 15823f03ced8SAlex Deucher break; 15833f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 15843f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 15853f03ced8SAlex Deucher break; 15863f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 15873f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 15883f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 15893f03ced8SAlex Deucher else 15903f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 15913f03ced8SAlex Deucher break; 15923f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 15933f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 15943f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 15953f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 15963f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 15973f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 15983f03ced8SAlex Deucher else 15993f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 16003f03ced8SAlex Deucher break; 16013f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 16023f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 16033f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 16043f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 16053f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 16063f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 16073f03ced8SAlex Deucher else 16083f03ced8SAlex Deucher index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 16093f03ced8SAlex Deucher break; 16103f03ced8SAlex Deucher default: 16113f03ced8SAlex Deucher return; 16123f03ced8SAlex Deucher } 16133f03ced8SAlex Deucher 16143f03ced8SAlex Deucher switch (mode) { 16153f03ced8SAlex Deucher case DRM_MODE_DPMS_ON: 16163f03ced8SAlex Deucher args.ucAction = ATOM_ENABLE; 16173f03ced8SAlex Deucher /* workaround for DVOOutputControl on some RS690 systems */ 16183f03ced8SAlex Deucher if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 16193f03ced8SAlex Deucher u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 16203f03ced8SAlex Deucher WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1621f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 16223f03ced8SAlex Deucher WREG32(RADEON_BIOS_3_SCRATCH, reg); 16233f03ced8SAlex Deucher } else 1624f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 16253f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1626ae93580eSAlex Deucher if (rdev->mode_info.bl_encoder) { 16274281f46eSMichel Dänzer struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 16284281f46eSMichel Dänzer 16294281f46eSMichel Dänzer atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1630ae93580eSAlex Deucher } else { 1631ae93580eSAlex Deucher args.ucAction = ATOM_LCD_BLON; 1632f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 1633ae93580eSAlex Deucher } 16343f03ced8SAlex Deucher } 16353f03ced8SAlex Deucher break; 16363f03ced8SAlex Deucher case DRM_MODE_DPMS_STANDBY: 16373f03ced8SAlex Deucher case DRM_MODE_DPMS_SUSPEND: 16383f03ced8SAlex Deucher case DRM_MODE_DPMS_OFF: 16393f03ced8SAlex Deucher args.ucAction = ATOM_DISABLE; 1640f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 16413f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 16423f03ced8SAlex Deucher args.ucAction = ATOM_LCD_BLOFF; 1643f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 16443f03ced8SAlex Deucher } 16453f03ced8SAlex Deucher break; 16463f03ced8SAlex Deucher } 16473f03ced8SAlex Deucher } 16483f03ced8SAlex Deucher 16493f03ced8SAlex Deucher static void 16503f03ced8SAlex Deucher radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 16513f03ced8SAlex Deucher { 16523f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 16533f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 16543f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 16558d1af57aSAlex Deucher struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 16568d1af57aSAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 16573f03ced8SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 16583f03ced8SAlex Deucher struct radeon_connector *radeon_connector = NULL; 16593f03ced8SAlex Deucher struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 16606f50e075SAlex Deucher bool travis_quirk = false; 16613f03ced8SAlex Deucher 16623f03ced8SAlex Deucher if (connector) { 16633f03ced8SAlex Deucher radeon_connector = to_radeon_connector(connector); 16643f03ced8SAlex Deucher radeon_dig_connector = radeon_connector->con_priv; 16656f50e075SAlex Deucher if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == 16666f50e075SAlex Deucher ENCODER_OBJECT_ID_TRAVIS) && 16676f50e075SAlex Deucher (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 16686f50e075SAlex Deucher !ASIC_IS_DCE5(rdev)) 16696f50e075SAlex Deucher travis_quirk = true; 16703f03ced8SAlex Deucher } 16713f03ced8SAlex Deucher 16723f03ced8SAlex Deucher switch (mode) { 16733f03ced8SAlex Deucher case DRM_MODE_DPMS_ON: 16748d1af57aSAlex Deucher if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 16758d1af57aSAlex Deucher if (!connector) 16768d1af57aSAlex Deucher dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 16778d1af57aSAlex Deucher else 16788d1af57aSAlex Deucher dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 16798d1af57aSAlex Deucher 16808d1af57aSAlex Deucher /* setup and enable the encoder */ 1681fcedac67SJerome Glisse atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 16828d1af57aSAlex Deucher atombios_dig_encoder_setup(encoder, 16838d1af57aSAlex Deucher ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 16848d1af57aSAlex Deucher dig->panel_mode); 16858d1af57aSAlex Deucher if (ext_encoder) { 16868d1af57aSAlex Deucher if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 16878d1af57aSAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, 16888d1af57aSAlex Deucher EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1689fcedac67SJerome Glisse } 16908d1af57aSAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 16918d1af57aSAlex Deucher /* setup and enable the encoder */ 16928d1af57aSAlex Deucher atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1693fcedac67SJerome Glisse } else { 16948d1af57aSAlex Deucher /* setup and enable the encoder and transmitter */ 16958d1af57aSAlex Deucher atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 16968d1af57aSAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1697fcedac67SJerome Glisse } 16983f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 16993f03ced8SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 17003f03ced8SAlex Deucher atombios_set_edp_panel_power(connector, 17013f03ced8SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 17023f03ced8SAlex Deucher radeon_dig_connector->edp_on = true; 17033f03ced8SAlex Deucher } 17046f50e075SAlex Deucher } 17056f50e075SAlex Deucher /* enable the transmitter */ 17066f50e075SAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 17076f50e075SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 17086f50e075SAlex Deucher /* DP_SET_POWER_D0 is set in radeon_dp_link_train */ 17093f03ced8SAlex Deucher radeon_dp_link_train(encoder, connector); 17103f03ced8SAlex Deucher if (ASIC_IS_DCE4(rdev)) 17113f03ced8SAlex Deucher atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 17123f03ced8SAlex Deucher } 1713ae93580eSAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1714ae93580eSAlex Deucher if (rdev->mode_info.bl_encoder) 17154281f46eSMichel Dänzer atombios_set_backlight_level(radeon_encoder, dig->backlight_level); 1716ae93580eSAlex Deucher else 1717ae93580eSAlex Deucher atombios_dig_transmitter_setup(encoder, 1718ae93580eSAlex Deucher ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1719ae93580eSAlex Deucher } 17206f50e075SAlex Deucher if (ext_encoder) 17216f50e075SAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 17223f03ced8SAlex Deucher break; 17233f03ced8SAlex Deucher case DRM_MODE_DPMS_STANDBY: 17243f03ced8SAlex Deucher case DRM_MODE_DPMS_SUSPEND: 17253f03ced8SAlex Deucher case DRM_MODE_DPMS_OFF: 17269843ead0SDave Airlie 172740390961SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 17286f50e075SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) 17296f50e075SAlex Deucher atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 17306f50e075SAlex Deucher } 17316f50e075SAlex Deucher if (ext_encoder) 17326f50e075SAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 17336f50e075SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 17346f50e075SAlex Deucher atombios_dig_transmitter_setup(encoder, 17356f50e075SAlex Deucher ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 17366f50e075SAlex Deucher 17376f50e075SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && 17386f50e075SAlex Deucher connector && !travis_quirk) 17396f50e075SAlex Deucher radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 17406f50e075SAlex Deucher if (ASIC_IS_DCE4(rdev)) { 17418d1af57aSAlex Deucher /* disable the transmitter */ 17426f50e075SAlex Deucher atombios_dig_transmitter_setup(encoder, 17436f50e075SAlex Deucher ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 17448d1af57aSAlex Deucher } else { 17458d1af57aSAlex Deucher /* disable the encoder and transmitter */ 17466f50e075SAlex Deucher atombios_dig_transmitter_setup(encoder, 17476f50e075SAlex Deucher ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 17488d1af57aSAlex Deucher atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 17498d1af57aSAlex Deucher } 17503f03ced8SAlex Deucher if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 17516f50e075SAlex Deucher if (travis_quirk) 17526f50e075SAlex Deucher radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); 17533f03ced8SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 17543f03ced8SAlex Deucher atombios_set_edp_panel_power(connector, 17553f03ced8SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_OFF); 17563f03ced8SAlex Deucher radeon_dig_connector->edp_on = false; 17573f03ced8SAlex Deucher } 17583f03ced8SAlex Deucher } 17593f03ced8SAlex Deucher break; 17603f03ced8SAlex Deucher } 17613f03ced8SAlex Deucher } 17623f03ced8SAlex Deucher 17633f03ced8SAlex Deucher static void 17643f03ced8SAlex Deucher radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 17653f03ced8SAlex Deucher { 17663f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 17673f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 17683f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 17695c046a57SAlex Deucher int encoder_mode = atombios_get_encoder_mode(encoder); 17703f03ced8SAlex Deucher 17713f03ced8SAlex Deucher DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 17723f03ced8SAlex Deucher radeon_encoder->encoder_id, mode, radeon_encoder->devices, 17733f03ced8SAlex Deucher radeon_encoder->active_device); 17745c046a57SAlex Deucher 177538aef154SAlex Deucher if ((radeon_audio != 0) && 17765c046a57SAlex Deucher ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 177738aef154SAlex Deucher ENCODER_MODE_IS_DP(encoder_mode))) 17785c046a57SAlex Deucher radeon_audio_dpms(encoder, mode); 17795c046a57SAlex Deucher 17803f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 17813f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 17823f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 17833f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 17843f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 17853f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 17863f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 17873f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 17883f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 17893f03ced8SAlex Deucher radeon_atom_encoder_dpms_avivo(encoder, mode); 17903f03ced8SAlex Deucher break; 17913f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 17923f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 17933f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1794e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 17953f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 17963f03ced8SAlex Deucher radeon_atom_encoder_dpms_dig(encoder, mode); 17973f03ced8SAlex Deucher break; 17983f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 17993f03ced8SAlex Deucher if (ASIC_IS_DCE5(rdev)) { 18003f03ced8SAlex Deucher switch (mode) { 18013f03ced8SAlex Deucher case DRM_MODE_DPMS_ON: 18023f03ced8SAlex Deucher atombios_dvo_setup(encoder, ATOM_ENABLE); 18033f03ced8SAlex Deucher break; 18043f03ced8SAlex Deucher case DRM_MODE_DPMS_STANDBY: 18053f03ced8SAlex Deucher case DRM_MODE_DPMS_SUSPEND: 18063f03ced8SAlex Deucher case DRM_MODE_DPMS_OFF: 18073f03ced8SAlex Deucher atombios_dvo_setup(encoder, ATOM_DISABLE); 18083f03ced8SAlex Deucher break; 18093f03ced8SAlex Deucher } 18103f03ced8SAlex Deucher } else if (ASIC_IS_DCE3(rdev)) 18113f03ced8SAlex Deucher radeon_atom_encoder_dpms_dig(encoder, mode); 18123f03ced8SAlex Deucher else 18133f03ced8SAlex Deucher radeon_atom_encoder_dpms_avivo(encoder, mode); 18143f03ced8SAlex Deucher break; 18153f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 18163f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 18173f03ced8SAlex Deucher if (ASIC_IS_DCE5(rdev)) { 18183f03ced8SAlex Deucher switch (mode) { 18193f03ced8SAlex Deucher case DRM_MODE_DPMS_ON: 18203f03ced8SAlex Deucher atombios_dac_setup(encoder, ATOM_ENABLE); 18213f03ced8SAlex Deucher break; 18223f03ced8SAlex Deucher case DRM_MODE_DPMS_STANDBY: 18233f03ced8SAlex Deucher case DRM_MODE_DPMS_SUSPEND: 18243f03ced8SAlex Deucher case DRM_MODE_DPMS_OFF: 18253f03ced8SAlex Deucher atombios_dac_setup(encoder, ATOM_DISABLE); 18263f03ced8SAlex Deucher break; 18273f03ced8SAlex Deucher } 18283f03ced8SAlex Deucher } else 18293f03ced8SAlex Deucher radeon_atom_encoder_dpms_avivo(encoder, mode); 18303f03ced8SAlex Deucher break; 18313f03ced8SAlex Deucher default: 18323f03ced8SAlex Deucher return; 18333f03ced8SAlex Deucher } 18343f03ced8SAlex Deucher 18353f03ced8SAlex Deucher radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 18363f03ced8SAlex Deucher 18373f03ced8SAlex Deucher } 18383f03ced8SAlex Deucher 18393f03ced8SAlex Deucher union crtc_source_param { 18403f03ced8SAlex Deucher SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 18413f03ced8SAlex Deucher SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 18423f03ced8SAlex Deucher }; 18433f03ced8SAlex Deucher 18443f03ced8SAlex Deucher static void 18453f03ced8SAlex Deucher atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 18463f03ced8SAlex Deucher { 18473f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 18483f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 18493f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 18503f03ced8SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 18513f03ced8SAlex Deucher union crtc_source_param args; 18523f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 18533f03ced8SAlex Deucher uint8_t frev, crev; 18543f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig; 18553f03ced8SAlex Deucher 18563f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 18573f03ced8SAlex Deucher 18583f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 18593f03ced8SAlex Deucher return; 18603f03ced8SAlex Deucher 18613f03ced8SAlex Deucher switch (frev) { 18623f03ced8SAlex Deucher case 1: 18633f03ced8SAlex Deucher switch (crev) { 18643f03ced8SAlex Deucher case 1: 18653f03ced8SAlex Deucher default: 18663f03ced8SAlex Deucher if (ASIC_IS_AVIVO(rdev)) 18673f03ced8SAlex Deucher args.v1.ucCRTC = radeon_crtc->crtc_id; 18683f03ced8SAlex Deucher else { 18693c20d544SWambui Karuga if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) 18703f03ced8SAlex Deucher args.v1.ucCRTC = radeon_crtc->crtc_id; 18713c20d544SWambui Karuga else 18723f03ced8SAlex Deucher args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 18733f03ced8SAlex Deucher } 18743f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 18753f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 18763f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 18773f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 18783f03ced8SAlex Deucher break; 18793f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 18803f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 18813f03ced8SAlex Deucher if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 18823f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 18833f03ced8SAlex Deucher else 18843f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 18853f03ced8SAlex Deucher break; 18863f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 18873f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 18883f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 18893f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 18903f03ced8SAlex Deucher break; 18913f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 18923f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 18933f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 18943f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 18953f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 18963f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 18973f03ced8SAlex Deucher else 18983f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 18993f03ced8SAlex Deucher break; 19003f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 19013f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 19023f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 19033f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 19043f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 19053f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 19063f03ced8SAlex Deucher else 19073f03ced8SAlex Deucher args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 19083f03ced8SAlex Deucher break; 19093f03ced8SAlex Deucher } 19103f03ced8SAlex Deucher break; 19113f03ced8SAlex Deucher case 2: 19123f03ced8SAlex Deucher args.v2.ucCRTC = radeon_crtc->crtc_id; 19133f03ced8SAlex Deucher if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 19143f03ced8SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 19153f03ced8SAlex Deucher 19163f03ced8SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 19173f03ced8SAlex Deucher args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 19183f03ced8SAlex Deucher else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 19193f03ced8SAlex Deucher args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 19203f03ced8SAlex Deucher else 19213f03ced8SAlex Deucher args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 192264252835SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 192364252835SAlex Deucher args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 192464252835SAlex Deucher } else { 19253f03ced8SAlex Deucher args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 192664252835SAlex Deucher } 19273f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 19283f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 19293f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 19303f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1931e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 19323f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 19333f03ced8SAlex Deucher dig = radeon_encoder->enc_priv; 19343f03ced8SAlex Deucher switch (dig->dig_encoder) { 19353f03ced8SAlex Deucher case 0: 19363f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 19373f03ced8SAlex Deucher break; 19383f03ced8SAlex Deucher case 1: 19393f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 19403f03ced8SAlex Deucher break; 19413f03ced8SAlex Deucher case 2: 19423f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 19433f03ced8SAlex Deucher break; 19443f03ced8SAlex Deucher case 3: 19453f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 19463f03ced8SAlex Deucher break; 19473f03ced8SAlex Deucher case 4: 19483f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 19493f03ced8SAlex Deucher break; 19503f03ced8SAlex Deucher case 5: 19513f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 19523f03ced8SAlex Deucher break; 1953e68adef8SAlex Deucher case 6: 1954e68adef8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; 1955e68adef8SAlex Deucher break; 19563f03ced8SAlex Deucher } 19573f03ced8SAlex Deucher break; 19583f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 19593f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 19603f03ced8SAlex Deucher break; 19613f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 19623f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 19633f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 19643f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 19653f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 19663f03ced8SAlex Deucher else 19673f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 19683f03ced8SAlex Deucher break; 19693f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 19703f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 19713f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 19723f03ced8SAlex Deucher else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 19733f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 19743f03ced8SAlex Deucher else 19753f03ced8SAlex Deucher args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 19763f03ced8SAlex Deucher break; 19773f03ced8SAlex Deucher } 19783f03ced8SAlex Deucher break; 19793f03ced8SAlex Deucher } 19803f03ced8SAlex Deucher break; 19813f03ced8SAlex Deucher default: 19823f03ced8SAlex Deucher DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 19833f03ced8SAlex Deucher return; 19843f03ced8SAlex Deucher } 19853f03ced8SAlex Deucher 1986f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 19873f03ced8SAlex Deucher 19883f03ced8SAlex Deucher /* update scratch regs with new routing */ 19893f03ced8SAlex Deucher radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 19903f03ced8SAlex Deucher } 19913f03ced8SAlex Deucher 19923f03ced8SAlex Deucher static void 19933f03ced8SAlex Deucher atombios_apply_encoder_quirks(struct drm_encoder *encoder, 19943f03ced8SAlex Deucher struct drm_display_mode *mode) 19953f03ced8SAlex Deucher { 19963f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 19973f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 19983f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 19993f03ced8SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 20003f03ced8SAlex Deucher 20013f03ced8SAlex Deucher /* Funky macbooks */ 2002d86a4126SThomas Zimmermann if ((rdev->pdev->device == 0x71C5) && 2003d86a4126SThomas Zimmermann (rdev->pdev->subsystem_vendor == 0x106b) && 2004d86a4126SThomas Zimmermann (rdev->pdev->subsystem_device == 0x0080)) { 20053f03ced8SAlex Deucher if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 20063f03ced8SAlex Deucher uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 20073f03ced8SAlex Deucher 20083f03ced8SAlex Deucher lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 20093f03ced8SAlex Deucher lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 20103f03ced8SAlex Deucher 20113f03ced8SAlex Deucher WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 20123f03ced8SAlex Deucher } 20133f03ced8SAlex Deucher } 20143f03ced8SAlex Deucher 20153f03ced8SAlex Deucher /* set scaler clears this on some chips */ 20163f03ced8SAlex Deucher if (ASIC_IS_AVIVO(rdev) && 20173f03ced8SAlex Deucher (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 2018d798f2f2SAlex Deucher if (ASIC_IS_DCE8(rdev)) { 2019d798f2f2SAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2020d798f2f2SAlex Deucher WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 2021d798f2f2SAlex Deucher CIK_INTERLEAVE_EN); 2022d798f2f2SAlex Deucher else 2023d798f2f2SAlex Deucher WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 2024d798f2f2SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 20253f03ced8SAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 20263f03ced8SAlex Deucher WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 20273f03ced8SAlex Deucher EVERGREEN_INTERLEAVE_EN); 20283f03ced8SAlex Deucher else 20293f03ced8SAlex Deucher WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 20303f03ced8SAlex Deucher } else { 20313f03ced8SAlex Deucher if (mode->flags & DRM_MODE_FLAG_INTERLACE) 20323f03ced8SAlex Deucher WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 20333f03ced8SAlex Deucher AVIVO_D1MODE_INTERLEAVE_EN); 20343f03ced8SAlex Deucher else 20353f03ced8SAlex Deucher WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 20363f03ced8SAlex Deucher } 20373f03ced8SAlex Deucher } 20383f03ced8SAlex Deucher } 20393f03ced8SAlex Deucher 20408f0fc088SDave Airlie void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx) 20418f0fc088SDave Airlie { 20428f0fc088SDave Airlie if (enc_idx < 0) 20438f0fc088SDave Airlie return; 20448f0fc088SDave Airlie rdev->mode_info.active_encoders &= ~(1 << enc_idx); 20458f0fc088SDave Airlie } 20468f0fc088SDave Airlie 20478f0fc088SDave Airlie int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) 20483f03ced8SAlex Deucher { 20493f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 20503f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 20513f03ced8SAlex Deucher struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 20523f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 20533f03ced8SAlex Deucher struct drm_encoder *test_encoder; 205441fa5437SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 20553f03ced8SAlex Deucher uint32_t dig_enc_in_use = 0; 20568f0fc088SDave Airlie int enc_idx = -1; 20573f03ced8SAlex Deucher 20588f0fc088SDave Airlie if (fe_idx >= 0) { 20598f0fc088SDave Airlie enc_idx = fe_idx; 20608f0fc088SDave Airlie goto assigned; 20618f0fc088SDave Airlie } 206241fa5437SAlex Deucher if (ASIC_IS_DCE6(rdev)) { 206341fa5437SAlex Deucher /* DCE6 */ 206441fa5437SAlex Deucher switch (radeon_encoder->encoder_id) { 206541fa5437SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 206641fa5437SAlex Deucher if (dig->linkb) 20678f0fc088SDave Airlie enc_idx = 1; 206841fa5437SAlex Deucher else 20698f0fc088SDave Airlie enc_idx = 0; 207041fa5437SAlex Deucher break; 207141fa5437SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 207241fa5437SAlex Deucher if (dig->linkb) 20738f0fc088SDave Airlie enc_idx = 3; 207441fa5437SAlex Deucher else 20758f0fc088SDave Airlie enc_idx = 2; 207641fa5437SAlex Deucher break; 207741fa5437SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 207841fa5437SAlex Deucher if (dig->linkb) 20798f0fc088SDave Airlie enc_idx = 5; 208041fa5437SAlex Deucher else 20818f0fc088SDave Airlie enc_idx = 4; 208241fa5437SAlex Deucher break; 2083e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 20848f0fc088SDave Airlie enc_idx = 6; 2085e68adef8SAlex Deucher break; 208641fa5437SAlex Deucher } 20878f0fc088SDave Airlie goto assigned; 208841fa5437SAlex Deucher } else if (ASIC_IS_DCE4(rdev)) { 20893f03ced8SAlex Deucher /* DCE4/5 */ 209041fa5437SAlex Deucher if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 20913f03ced8SAlex Deucher /* ontario follows DCE4 */ 20923f03ced8SAlex Deucher if (rdev->family == CHIP_PALM) { 20933f03ced8SAlex Deucher if (dig->linkb) 20948f0fc088SDave Airlie enc_idx = 1; 20953f03ced8SAlex Deucher else 20968f0fc088SDave Airlie enc_idx = 0; 20973f03ced8SAlex Deucher } else 20983f03ced8SAlex Deucher /* llano follows DCE3.2 */ 20998f0fc088SDave Airlie enc_idx = radeon_crtc->crtc_id; 21003f03ced8SAlex Deucher } else { 21013f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 21023f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 21033f03ced8SAlex Deucher if (dig->linkb) 21048f0fc088SDave Airlie enc_idx = 1; 21053f03ced8SAlex Deucher else 21068f0fc088SDave Airlie enc_idx = 0; 21073f03ced8SAlex Deucher break; 21083f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 21093f03ced8SAlex Deucher if (dig->linkb) 21108f0fc088SDave Airlie enc_idx = 3; 21113f03ced8SAlex Deucher else 21128f0fc088SDave Airlie enc_idx = 2; 21133f03ced8SAlex Deucher break; 21143f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 21153f03ced8SAlex Deucher if (dig->linkb) 21168f0fc088SDave Airlie enc_idx = 5; 21173f03ced8SAlex Deucher else 21188f0fc088SDave Airlie enc_idx = 4; 21193f03ced8SAlex Deucher break; 21203f03ced8SAlex Deucher } 21213f03ced8SAlex Deucher } 21228f0fc088SDave Airlie goto assigned; 21233f03ced8SAlex Deucher } 21243f03ced8SAlex Deucher 2125564d8a2cSMario Kleiner /* 2126564d8a2cSMario Kleiner * On DCE32 any encoder can drive any block so usually just use crtc id, 212705eacc19SMark Hawrylak * but Apple thinks different at least on iMac10,1 and iMac11,2, so there use linkb, 2128564d8a2cSMario Kleiner * otherwise the internal eDP panel will stay dark. 2129564d8a2cSMario Kleiner */ 21303f03ced8SAlex Deucher if (ASIC_IS_DCE32(rdev)) { 213105eacc19SMark Hawrylak if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") || 213205eacc19SMark Hawrylak dmi_match(DMI_PRODUCT_NAME, "iMac11,2")) 2133564d8a2cSMario Kleiner enc_idx = (dig->linkb) ? 1 : 0; 2134564d8a2cSMario Kleiner else 21358f0fc088SDave Airlie enc_idx = radeon_crtc->crtc_id; 2136564d8a2cSMario Kleiner 21378f0fc088SDave Airlie goto assigned; 21383f03ced8SAlex Deucher } 21393f03ced8SAlex Deucher 21403f03ced8SAlex Deucher /* on DCE3 - LVTMA can only be driven by DIGB */ 21413f03ced8SAlex Deucher list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 21423f03ced8SAlex Deucher struct radeon_encoder *radeon_test_encoder; 21433f03ced8SAlex Deucher 21443f03ced8SAlex Deucher if (encoder == test_encoder) 21453f03ced8SAlex Deucher continue; 21463f03ced8SAlex Deucher 21473f03ced8SAlex Deucher if (!radeon_encoder_is_digital(test_encoder)) 21483f03ced8SAlex Deucher continue; 21493f03ced8SAlex Deucher 21503f03ced8SAlex Deucher radeon_test_encoder = to_radeon_encoder(test_encoder); 21513f03ced8SAlex Deucher dig = radeon_test_encoder->enc_priv; 21523f03ced8SAlex Deucher 21533f03ced8SAlex Deucher if (dig->dig_encoder >= 0) 21543f03ced8SAlex Deucher dig_enc_in_use |= (1 << dig->dig_encoder); 21553f03ced8SAlex Deucher } 21563f03ced8SAlex Deucher 21573f03ced8SAlex Deucher if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 21583f03ced8SAlex Deucher if (dig_enc_in_use & 0x2) 21593f03ced8SAlex Deucher DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 21603f03ced8SAlex Deucher return 1; 21613f03ced8SAlex Deucher } 21623f03ced8SAlex Deucher if (!(dig_enc_in_use & 1)) 21633f03ced8SAlex Deucher return 0; 21643f03ced8SAlex Deucher return 1; 21658f0fc088SDave Airlie 21668f0fc088SDave Airlie assigned: 21678f0fc088SDave Airlie if (enc_idx == -1) { 21688f0fc088SDave Airlie DRM_ERROR("Got encoder index incorrect - returning 0\n"); 21698f0fc088SDave Airlie return 0; 21708f0fc088SDave Airlie } 21713c20d544SWambui Karuga if (rdev->mode_info.active_encoders & (1 << enc_idx)) 21728f0fc088SDave Airlie DRM_ERROR("chosen encoder in use %d\n", enc_idx); 21733c20d544SWambui Karuga 21748f0fc088SDave Airlie rdev->mode_info.active_encoders |= (1 << enc_idx); 21758f0fc088SDave Airlie return enc_idx; 21763f03ced8SAlex Deucher } 21773f03ced8SAlex Deucher 21783f03ced8SAlex Deucher /* This only needs to be called once at startup */ 21793f03ced8SAlex Deucher void 21803f03ced8SAlex Deucher radeon_atom_encoder_init(struct radeon_device *rdev) 21813f03ced8SAlex Deucher { 21823f03ced8SAlex Deucher struct drm_device *dev = rdev->ddev; 21833f03ced8SAlex Deucher struct drm_encoder *encoder; 21843f03ced8SAlex Deucher 21853f03ced8SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 21863f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 21873f03ced8SAlex Deucher struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 21883f03ced8SAlex Deucher 21893f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 21903f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 21913f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 21923f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2193e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 21943f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 21953f03ced8SAlex Deucher atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 21963f03ced8SAlex Deucher break; 21973f03ced8SAlex Deucher default: 21983f03ced8SAlex Deucher break; 21993f03ced8SAlex Deucher } 22003f03ced8SAlex Deucher 22011d3949c4SAlex Deucher if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 22023f03ced8SAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, 22033f03ced8SAlex Deucher EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 22043f03ced8SAlex Deucher } 22053f03ced8SAlex Deucher } 22063f03ced8SAlex Deucher 22073f03ced8SAlex Deucher static void 22083f03ced8SAlex Deucher radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 22093f03ced8SAlex Deucher struct drm_display_mode *mode, 22103f03ced8SAlex Deucher struct drm_display_mode *adjusted_mode) 22113f03ced8SAlex Deucher { 22123f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 22133f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 22143f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 22153473f542SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 22166f945693SSlava Grigorev int encoder_mode; 22173f03ced8SAlex Deucher 22183f03ced8SAlex Deucher radeon_encoder->pixel_clock = adjusted_mode->clock; 22193f03ced8SAlex Deucher 22208d1af57aSAlex Deucher /* need to call this here rather than in prepare() since we need some crtc info */ 22218d1af57aSAlex Deucher radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 22228d1af57aSAlex Deucher 22233f03ced8SAlex Deucher if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 22243f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 22253f03ced8SAlex Deucher atombios_yuv_setup(encoder, true); 22263f03ced8SAlex Deucher else 22273f03ced8SAlex Deucher atombios_yuv_setup(encoder, false); 22283f03ced8SAlex Deucher } 22293f03ced8SAlex Deucher 22303f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 22313f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 22323f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 22333f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 22343f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 22353f03ced8SAlex Deucher atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 22363f03ced8SAlex Deucher break; 22373f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 22383f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 22393f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2240e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 22413f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 22428d1af57aSAlex Deucher /* handled in dpms */ 22433f03ced8SAlex Deucher break; 22443f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 22453f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 22463f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 22473f03ced8SAlex Deucher atombios_dvo_setup(encoder, ATOM_ENABLE); 22483f03ced8SAlex Deucher break; 22493f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 22503f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 22513f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 22523f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 22533f03ced8SAlex Deucher atombios_dac_setup(encoder, ATOM_ENABLE); 22543f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 22553f03ced8SAlex Deucher if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 22563f03ced8SAlex Deucher atombios_tv_setup(encoder, ATOM_ENABLE); 22573f03ced8SAlex Deucher else 22583f03ced8SAlex Deucher atombios_tv_setup(encoder, ATOM_DISABLE); 22593f03ced8SAlex Deucher } 22603f03ced8SAlex Deucher break; 22613f03ced8SAlex Deucher } 22623f03ced8SAlex Deucher 22633f03ced8SAlex Deucher atombios_apply_encoder_quirks(encoder, adjusted_mode); 22645c046a57SAlex Deucher 22655c046a57SAlex Deucher encoder_mode = atombios_get_encoder_mode(encoder); 22665c046a57SAlex Deucher if (connector && (radeon_audio != 0) && 22675c046a57SAlex Deucher ((encoder_mode == ATOM_ENCODER_MODE_HDMI) || 22687726e72bSAlex Deucher ENCODER_MODE_IS_DP(encoder_mode))) 22695c046a57SAlex Deucher radeon_audio_mode_set(encoder, adjusted_mode); 22703f03ced8SAlex Deucher } 22713f03ced8SAlex Deucher 22723f03ced8SAlex Deucher static bool 22733f03ced8SAlex Deucher atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 22743f03ced8SAlex Deucher { 22753f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 22763f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 22773f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 22783f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 22793f03ced8SAlex Deucher 22803f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 22813f03ced8SAlex Deucher ATOM_DEVICE_CV_SUPPORT | 22823f03ced8SAlex Deucher ATOM_DEVICE_CRT_SUPPORT)) { 22833f03ced8SAlex Deucher DAC_LOAD_DETECTION_PS_ALLOCATION args; 22843f03ced8SAlex Deucher int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 22853f03ced8SAlex Deucher uint8_t frev, crev; 22863f03ced8SAlex Deucher 22873f03ced8SAlex Deucher memset(&args, 0, sizeof(args)); 22883f03ced8SAlex Deucher 22893f03ced8SAlex Deucher if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 22903f03ced8SAlex Deucher return false; 22913f03ced8SAlex Deucher 22923f03ced8SAlex Deucher args.sDacload.ucMisc = 0; 22933f03ced8SAlex Deucher 22943f03ced8SAlex Deucher if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 22953f03ced8SAlex Deucher (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 22963f03ced8SAlex Deucher args.sDacload.ucDacType = ATOM_DAC_A; 22973f03ced8SAlex Deucher else 22983f03ced8SAlex Deucher args.sDacload.ucDacType = ATOM_DAC_B; 22993f03ced8SAlex Deucher 23003f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 23013f03ced8SAlex Deucher args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 23023f03ced8SAlex Deucher else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 23033f03ced8SAlex Deucher args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 23043f03ced8SAlex Deucher else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 23053f03ced8SAlex Deucher args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 23063f03ced8SAlex Deucher if (crev >= 3) 23073f03ced8SAlex Deucher args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 23083f03ced8SAlex Deucher } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 23093f03ced8SAlex Deucher args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 23103f03ced8SAlex Deucher if (crev >= 3) 23113f03ced8SAlex Deucher args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 23123f03ced8SAlex Deucher } 23133f03ced8SAlex Deucher 2314f7a16fa3SAlexander Richards atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); 23153f03ced8SAlex Deucher 23163f03ced8SAlex Deucher return true; 23173f03ced8SAlex Deucher } else 23183f03ced8SAlex Deucher return false; 23193f03ced8SAlex Deucher } 23203f03ced8SAlex Deucher 23213f03ced8SAlex Deucher static enum drm_connector_status 23223f03ced8SAlex Deucher radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 23233f03ced8SAlex Deucher { 23243f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 23253f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 23263f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 23273f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 23283f03ced8SAlex Deucher uint32_t bios_0_scratch; 23293f03ced8SAlex Deucher 23303f03ced8SAlex Deucher if (!atombios_dac_load_detect(encoder, connector)) { 23313f03ced8SAlex Deucher DRM_DEBUG_KMS("detect returned false \n"); 23323f03ced8SAlex Deucher return connector_status_unknown; 23333f03ced8SAlex Deucher } 23343f03ced8SAlex Deucher 23353f03ced8SAlex Deucher if (rdev->family >= CHIP_R600) 23363f03ced8SAlex Deucher bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 23373f03ced8SAlex Deucher else 23383f03ced8SAlex Deucher bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 23393f03ced8SAlex Deucher 23403f03ced8SAlex Deucher DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 23413f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 23423f03ced8SAlex Deucher if (bios_0_scratch & ATOM_S0_CRT1_MASK) 23433f03ced8SAlex Deucher return connector_status_connected; 23443f03ced8SAlex Deucher } 23453f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 23463f03ced8SAlex Deucher if (bios_0_scratch & ATOM_S0_CRT2_MASK) 23473f03ced8SAlex Deucher return connector_status_connected; 23483f03ced8SAlex Deucher } 23493f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 23503f03ced8SAlex Deucher if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 23513f03ced8SAlex Deucher return connector_status_connected; 23523f03ced8SAlex Deucher } 23533f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 23543f03ced8SAlex Deucher if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 23553f03ced8SAlex Deucher return connector_status_connected; /* CTV */ 23563f03ced8SAlex Deucher else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 23573f03ced8SAlex Deucher return connector_status_connected; /* STV */ 23583f03ced8SAlex Deucher } 23593f03ced8SAlex Deucher return connector_status_disconnected; 23603f03ced8SAlex Deucher } 23613f03ced8SAlex Deucher 23623f03ced8SAlex Deucher static enum drm_connector_status 23633f03ced8SAlex Deucher radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 23643f03ced8SAlex Deucher { 23653f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 23663f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 23673f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 23683f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 23693f03ced8SAlex Deucher struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 23703f03ced8SAlex Deucher u32 bios_0_scratch; 23713f03ced8SAlex Deucher 23723f03ced8SAlex Deucher if (!ASIC_IS_DCE4(rdev)) 23733f03ced8SAlex Deucher return connector_status_unknown; 23743f03ced8SAlex Deucher 23753f03ced8SAlex Deucher if (!ext_encoder) 23763f03ced8SAlex Deucher return connector_status_unknown; 23773f03ced8SAlex Deucher 23783f03ced8SAlex Deucher if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 23793f03ced8SAlex Deucher return connector_status_unknown; 23803f03ced8SAlex Deucher 23813f03ced8SAlex Deucher /* load detect on the dp bridge */ 23823f03ced8SAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, 23833f03ced8SAlex Deucher EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 23843f03ced8SAlex Deucher 23853f03ced8SAlex Deucher bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 23863f03ced8SAlex Deucher 23873f03ced8SAlex Deucher DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 23883f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 23893f03ced8SAlex Deucher if (bios_0_scratch & ATOM_S0_CRT1_MASK) 23903f03ced8SAlex Deucher return connector_status_connected; 23913f03ced8SAlex Deucher } 23923f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 23933f03ced8SAlex Deucher if (bios_0_scratch & ATOM_S0_CRT2_MASK) 23943f03ced8SAlex Deucher return connector_status_connected; 23953f03ced8SAlex Deucher } 23963f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 23973f03ced8SAlex Deucher if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 23983f03ced8SAlex Deucher return connector_status_connected; 23993f03ced8SAlex Deucher } 24003f03ced8SAlex Deucher if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 24013f03ced8SAlex Deucher if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 24023f03ced8SAlex Deucher return connector_status_connected; /* CTV */ 24033f03ced8SAlex Deucher else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 24043f03ced8SAlex Deucher return connector_status_connected; /* STV */ 24053f03ced8SAlex Deucher } 24063f03ced8SAlex Deucher return connector_status_disconnected; 24073f03ced8SAlex Deucher } 24083f03ced8SAlex Deucher 24093f03ced8SAlex Deucher void 24103f03ced8SAlex Deucher radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 24113f03ced8SAlex Deucher { 24123f03ced8SAlex Deucher struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 24133f03ced8SAlex Deucher 24143f03ced8SAlex Deucher if (ext_encoder) 24153f03ced8SAlex Deucher /* ddc_setup on the dp bridge */ 24163f03ced8SAlex Deucher atombios_external_encoder_setup(encoder, ext_encoder, 24173f03ced8SAlex Deucher EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 24183f03ced8SAlex Deucher 24193f03ced8SAlex Deucher } 24203f03ced8SAlex Deucher 24213f03ced8SAlex Deucher static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 24223f03ced8SAlex Deucher { 2423cfcbd6d3SRafał Miłecki struct radeon_device *rdev = encoder->dev->dev_private; 24243f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 24253f03ced8SAlex Deucher struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 24263f03ced8SAlex Deucher 24273f03ced8SAlex Deucher if ((radeon_encoder->active_device & 24283f03ced8SAlex Deucher (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 24293f03ced8SAlex Deucher (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 24303f03ced8SAlex Deucher ENCODER_OBJECT_ID_NONE)) { 24313f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2432cfcbd6d3SRafał Miłecki if (dig) { 24338f0fc088SDave Airlie if (dig->dig_encoder >= 0) 24348f0fc088SDave Airlie radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 24358f0fc088SDave Airlie dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1); 2436cfcbd6d3SRafał Miłecki if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2437cfcbd6d3SRafał Miłecki if (rdev->family >= CHIP_R600) 2438cfcbd6d3SRafał Miłecki dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2439cfcbd6d3SRafał Miłecki else 2440cfcbd6d3SRafał Miłecki /* RS600/690/740 have only 1 afmt block */ 2441cfcbd6d3SRafał Miłecki dig->afmt = rdev->mode_info.afmt[0]; 2442cfcbd6d3SRafał Miłecki } 2443cfcbd6d3SRafał Miłecki } 24443f03ced8SAlex Deucher } 24453f03ced8SAlex Deucher 24463f03ced8SAlex Deucher radeon_atom_output_lock(encoder, true); 24473f03ced8SAlex Deucher 24483f03ced8SAlex Deucher if (connector) { 24493f03ced8SAlex Deucher struct radeon_connector *radeon_connector = to_radeon_connector(connector); 24503f03ced8SAlex Deucher 24513f03ced8SAlex Deucher /* select the clock/data port if it uses a router */ 24523f03ced8SAlex Deucher if (radeon_connector->router.cd_valid) 24533f03ced8SAlex Deucher radeon_router_select_cd_port(radeon_connector); 24543f03ced8SAlex Deucher 24553f03ced8SAlex Deucher /* turn eDP panel on for mode set */ 24563f03ced8SAlex Deucher if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 24573f03ced8SAlex Deucher atombios_set_edp_panel_power(connector, 24583f03ced8SAlex Deucher ATOM_TRANSMITTER_ACTION_POWER_ON); 24593f03ced8SAlex Deucher } 24603f03ced8SAlex Deucher 24613f03ced8SAlex Deucher /* this is needed for the pll/ss setup to work correctly in some cases */ 24623f03ced8SAlex Deucher atombios_set_encoder_crtc_source(encoder); 2463134b480fSAlex Deucher /* set up the FMT blocks */ 2464134b480fSAlex Deucher if (ASIC_IS_DCE8(rdev)) 2465134b480fSAlex Deucher dce8_program_fmt(encoder); 2466134b480fSAlex Deucher else if (ASIC_IS_DCE4(rdev)) 2467134b480fSAlex Deucher dce4_program_fmt(encoder); 2468134b480fSAlex Deucher else if (ASIC_IS_DCE3(rdev)) 2469134b480fSAlex Deucher dce3_program_fmt(encoder); 2470134b480fSAlex Deucher else if (ASIC_IS_AVIVO(rdev)) 2471134b480fSAlex Deucher avivo_program_fmt(encoder); 24723f03ced8SAlex Deucher } 24733f03ced8SAlex Deucher 24743f03ced8SAlex Deucher static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 24753f03ced8SAlex Deucher { 24768d1af57aSAlex Deucher /* need to call this here as we need the crtc set up */ 24773f03ced8SAlex Deucher radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 24783f03ced8SAlex Deucher radeon_atom_output_lock(encoder, false); 24793f03ced8SAlex Deucher } 24803f03ced8SAlex Deucher 24813f03ced8SAlex Deucher static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 24823f03ced8SAlex Deucher { 24833f03ced8SAlex Deucher struct drm_device *dev = encoder->dev; 24843f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 24853f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 24863f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig; 24873f03ced8SAlex Deucher 24883f03ced8SAlex Deucher /* check for pre-DCE3 cards with shared encoders; 24893f03ced8SAlex Deucher * can't really use the links individually, so don't disable 24903f03ced8SAlex Deucher * the encoder if it's in use by another connector 24913f03ced8SAlex Deucher */ 24923f03ced8SAlex Deucher if (!ASIC_IS_DCE3(rdev)) { 24933f03ced8SAlex Deucher struct drm_encoder *other_encoder; 24943f03ced8SAlex Deucher struct radeon_encoder *other_radeon_encoder; 24953f03ced8SAlex Deucher 24963f03ced8SAlex Deucher list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 24973f03ced8SAlex Deucher other_radeon_encoder = to_radeon_encoder(other_encoder); 24983f03ced8SAlex Deucher if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 24993f03ced8SAlex Deucher drm_helper_encoder_in_use(other_encoder)) 25003f03ced8SAlex Deucher goto disable_done; 25013f03ced8SAlex Deucher } 25023f03ced8SAlex Deucher } 25033f03ced8SAlex Deucher 25043f03ced8SAlex Deucher radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 25053f03ced8SAlex Deucher 25063f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 25073f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 25083f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 25093f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 25103f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 25113f03ced8SAlex Deucher atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 25123f03ced8SAlex Deucher break; 25133f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 25143f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 25153f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2516e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 25173f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 25188d1af57aSAlex Deucher /* handled in dpms */ 25193f03ced8SAlex Deucher break; 25203f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 25213f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 25223f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 25233f03ced8SAlex Deucher atombios_dvo_setup(encoder, ATOM_DISABLE); 25243f03ced8SAlex Deucher break; 25253f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 25263f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 25273f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 25283f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 25293f03ced8SAlex Deucher atombios_dac_setup(encoder, ATOM_DISABLE); 25303f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 25313f03ced8SAlex Deucher atombios_tv_setup(encoder, ATOM_DISABLE); 25323f03ced8SAlex Deucher break; 25333f03ced8SAlex Deucher } 25343f03ced8SAlex Deucher 25353f03ced8SAlex Deucher disable_done: 25363f03ced8SAlex Deucher if (radeon_encoder_is_digital(encoder)) { 25378f0fc088SDave Airlie if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 25388f0fc088SDave Airlie if (rdev->asic->display.hdmi_enable) 25398f0fc088SDave Airlie radeon_hdmi_enable(rdev, encoder, false); 25403f03ced8SAlex Deucher } 25418f0fc088SDave Airlie if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) { 25428f0fc088SDave Airlie dig = radeon_encoder->enc_priv; 25438f0fc088SDave Airlie radeon_atom_release_dig_encoder(rdev, dig->dig_encoder); 25448f0fc088SDave Airlie dig->dig_encoder = -1; 25458f0fc088SDave Airlie radeon_encoder->active_device = 0; 25468f0fc088SDave Airlie } 25478f0fc088SDave Airlie } else 25483f03ced8SAlex Deucher radeon_encoder->active_device = 0; 25493f03ced8SAlex Deucher } 25503f03ced8SAlex Deucher 25513f03ced8SAlex Deucher /* these are handled by the primary encoders */ 25523f03ced8SAlex Deucher static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 25533f03ced8SAlex Deucher { 25543f03ced8SAlex Deucher 25553f03ced8SAlex Deucher } 25563f03ced8SAlex Deucher 25573f03ced8SAlex Deucher static void radeon_atom_ext_commit(struct drm_encoder *encoder) 25583f03ced8SAlex Deucher { 25593f03ced8SAlex Deucher 25603f03ced8SAlex Deucher } 25613f03ced8SAlex Deucher 25623f03ced8SAlex Deucher static void 25633f03ced8SAlex Deucher radeon_atom_ext_mode_set(struct drm_encoder *encoder, 25643f03ced8SAlex Deucher struct drm_display_mode *mode, 25653f03ced8SAlex Deucher struct drm_display_mode *adjusted_mode) 25663f03ced8SAlex Deucher { 25673f03ced8SAlex Deucher 25683f03ced8SAlex Deucher } 25693f03ced8SAlex Deucher 25703f03ced8SAlex Deucher static void radeon_atom_ext_disable(struct drm_encoder *encoder) 25713f03ced8SAlex Deucher { 25723f03ced8SAlex Deucher 25733f03ced8SAlex Deucher } 25743f03ced8SAlex Deucher 25753f03ced8SAlex Deucher static void 25763f03ced8SAlex Deucher radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 25773f03ced8SAlex Deucher { 25783f03ced8SAlex Deucher 25793f03ced8SAlex Deucher } 25803f03ced8SAlex Deucher 25813f03ced8SAlex Deucher static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 25823f03ced8SAlex Deucher .dpms = radeon_atom_ext_dpms, 25833f03ced8SAlex Deucher .prepare = radeon_atom_ext_prepare, 25843f03ced8SAlex Deucher .mode_set = radeon_atom_ext_mode_set, 25853f03ced8SAlex Deucher .commit = radeon_atom_ext_commit, 25863f03ced8SAlex Deucher .disable = radeon_atom_ext_disable, 25873f03ced8SAlex Deucher /* no detect for TMDS/LVDS yet */ 25883f03ced8SAlex Deucher }; 25893f03ced8SAlex Deucher 25903f03ced8SAlex Deucher static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 25913f03ced8SAlex Deucher .dpms = radeon_atom_encoder_dpms, 25923f03ced8SAlex Deucher .mode_fixup = radeon_atom_mode_fixup, 25933f03ced8SAlex Deucher .prepare = radeon_atom_encoder_prepare, 25943f03ced8SAlex Deucher .mode_set = radeon_atom_encoder_mode_set, 25953f03ced8SAlex Deucher .commit = radeon_atom_encoder_commit, 25963f03ced8SAlex Deucher .disable = radeon_atom_encoder_disable, 25973f03ced8SAlex Deucher .detect = radeon_atom_dig_detect, 25983f03ced8SAlex Deucher }; 25993f03ced8SAlex Deucher 26003f03ced8SAlex Deucher static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 26013f03ced8SAlex Deucher .dpms = radeon_atom_encoder_dpms, 26023f03ced8SAlex Deucher .mode_fixup = radeon_atom_mode_fixup, 26033f03ced8SAlex Deucher .prepare = radeon_atom_encoder_prepare, 26043f03ced8SAlex Deucher .mode_set = radeon_atom_encoder_mode_set, 26053f03ced8SAlex Deucher .commit = radeon_atom_encoder_commit, 26063f03ced8SAlex Deucher .detect = radeon_atom_dac_detect, 26073f03ced8SAlex Deucher }; 26083f03ced8SAlex Deucher 26093f03ced8SAlex Deucher void radeon_enc_destroy(struct drm_encoder *encoder) 26103f03ced8SAlex Deucher { 26113f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2612f3728734SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2613f3728734SAlex Deucher radeon_atom_backlight_exit(radeon_encoder); 26143f03ced8SAlex Deucher kfree(radeon_encoder->enc_priv); 26153f03ced8SAlex Deucher drm_encoder_cleanup(encoder); 26163f03ced8SAlex Deucher kfree(radeon_encoder); 26173f03ced8SAlex Deucher } 26183f03ced8SAlex Deucher 26193f03ced8SAlex Deucher static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 26203f03ced8SAlex Deucher .destroy = radeon_enc_destroy, 26213f03ced8SAlex Deucher }; 26223f03ced8SAlex Deucher 26231109ca09SLauri Kasanen static struct radeon_encoder_atom_dac * 26243f03ced8SAlex Deucher radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 26253f03ced8SAlex Deucher { 26263f03ced8SAlex Deucher struct drm_device *dev = radeon_encoder->base.dev; 26273f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 26283f03ced8SAlex Deucher struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 26293f03ced8SAlex Deucher 26303f03ced8SAlex Deucher if (!dac) 26313f03ced8SAlex Deucher return NULL; 26323f03ced8SAlex Deucher 26333f03ced8SAlex Deucher dac->tv_std = radeon_atombios_get_tv_info(rdev); 26343f03ced8SAlex Deucher return dac; 26353f03ced8SAlex Deucher } 26363f03ced8SAlex Deucher 26371109ca09SLauri Kasanen static struct radeon_encoder_atom_dig * 26383f03ced8SAlex Deucher radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 26393f03ced8SAlex Deucher { 26403f03ced8SAlex Deucher int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 26413f03ced8SAlex Deucher struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 26423f03ced8SAlex Deucher 26433f03ced8SAlex Deucher if (!dig) 26443f03ced8SAlex Deucher return NULL; 26453f03ced8SAlex Deucher 26463f03ced8SAlex Deucher /* coherent mode by default */ 26473f03ced8SAlex Deucher dig->coherent_mode = true; 26483f03ced8SAlex Deucher dig->dig_encoder = -1; 26493f03ced8SAlex Deucher 26503f03ced8SAlex Deucher if (encoder_enum == 2) 26513f03ced8SAlex Deucher dig->linkb = true; 26523f03ced8SAlex Deucher else 26533f03ced8SAlex Deucher dig->linkb = false; 26543f03ced8SAlex Deucher 26553f03ced8SAlex Deucher return dig; 26563f03ced8SAlex Deucher } 26573f03ced8SAlex Deucher 26583f03ced8SAlex Deucher void 26593f03ced8SAlex Deucher radeon_add_atom_encoder(struct drm_device *dev, 26603f03ced8SAlex Deucher uint32_t encoder_enum, 26613f03ced8SAlex Deucher uint32_t supported_device, 26623f03ced8SAlex Deucher u16 caps) 26633f03ced8SAlex Deucher { 26643f03ced8SAlex Deucher struct radeon_device *rdev = dev->dev_private; 26653f03ced8SAlex Deucher struct drm_encoder *encoder; 26663f03ced8SAlex Deucher struct radeon_encoder *radeon_encoder; 26673f03ced8SAlex Deucher 26683f03ced8SAlex Deucher /* see if we already added it */ 26693f03ced8SAlex Deucher list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 26703f03ced8SAlex Deucher radeon_encoder = to_radeon_encoder(encoder); 26713f03ced8SAlex Deucher if (radeon_encoder->encoder_enum == encoder_enum) { 26723f03ced8SAlex Deucher radeon_encoder->devices |= supported_device; 26733f03ced8SAlex Deucher return; 26743f03ced8SAlex Deucher } 26753f03ced8SAlex Deucher 26763f03ced8SAlex Deucher } 26773f03ced8SAlex Deucher 26783f03ced8SAlex Deucher /* add a new one */ 26793f03ced8SAlex Deucher radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 26803f03ced8SAlex Deucher if (!radeon_encoder) 26813f03ced8SAlex Deucher return; 26823f03ced8SAlex Deucher 26833f03ced8SAlex Deucher encoder = &radeon_encoder->base; 26843f03ced8SAlex Deucher switch (rdev->num_crtc) { 26853f03ced8SAlex Deucher case 1: 26863f03ced8SAlex Deucher encoder->possible_crtcs = 0x1; 26873f03ced8SAlex Deucher break; 26883f03ced8SAlex Deucher case 2: 26893f03ced8SAlex Deucher default: 26903f03ced8SAlex Deucher encoder->possible_crtcs = 0x3; 26913f03ced8SAlex Deucher break; 26923f03ced8SAlex Deucher case 4: 26933f03ced8SAlex Deucher encoder->possible_crtcs = 0xf; 26943f03ced8SAlex Deucher break; 26953f03ced8SAlex Deucher case 6: 26963f03ced8SAlex Deucher encoder->possible_crtcs = 0x3f; 26973f03ced8SAlex Deucher break; 26983f03ced8SAlex Deucher } 26993f03ced8SAlex Deucher 27003f03ced8SAlex Deucher radeon_encoder->enc_priv = NULL; 27013f03ced8SAlex Deucher 27023f03ced8SAlex Deucher radeon_encoder->encoder_enum = encoder_enum; 27033f03ced8SAlex Deucher radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 27043f03ced8SAlex Deucher radeon_encoder->devices = supported_device; 27053f03ced8SAlex Deucher radeon_encoder->rmx_type = RMX_OFF; 27063f03ced8SAlex Deucher radeon_encoder->underscan_type = UNDERSCAN_OFF; 27073f03ced8SAlex Deucher radeon_encoder->is_ext_encoder = false; 27083f03ced8SAlex Deucher radeon_encoder->caps = caps; 27093f03ced8SAlex Deucher 27103f03ced8SAlex Deucher switch (radeon_encoder->encoder_id) { 27113f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVDS: 27123f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 27133f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 27143f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 27153f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 27163f03ced8SAlex Deucher radeon_encoder->rmx_type = RMX_FULL; 271713a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 271813a3d91fSVille Syrjälä DRM_MODE_ENCODER_LVDS, NULL); 27193f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 27203f03ced8SAlex Deucher } else { 272113a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 272213a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 27233f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 27243f03ced8SAlex Deucher } 27253f03ced8SAlex Deucher drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 27263f03ced8SAlex Deucher break; 27273f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC1: 272813a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 272913a3d91fSVille Syrjälä DRM_MODE_ENCODER_DAC, NULL); 27303f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 27313f03ced8SAlex Deucher drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 27323f03ced8SAlex Deucher break; 27333f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DAC2: 27343f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 27353f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 273613a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 273713a3d91fSVille Syrjälä DRM_MODE_ENCODER_TVDAC, NULL); 27383f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 27393f03ced8SAlex Deucher drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 27403f03ced8SAlex Deucher break; 27413f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DVO1: 27423f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 27433f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_DDI: 27443f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 27453f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 27463f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 27473f03ced8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2748e68adef8SAlex Deucher case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 27493f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 27503f03ced8SAlex Deucher radeon_encoder->rmx_type = RMX_FULL; 275113a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 275213a3d91fSVille Syrjälä DRM_MODE_ENCODER_LVDS, NULL); 27533f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 27543f03ced8SAlex Deucher } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 275513a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 275613a3d91fSVille Syrjälä DRM_MODE_ENCODER_DAC, NULL); 27573f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 27583f03ced8SAlex Deucher } else { 275913a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 276013a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 27613f03ced8SAlex Deucher radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 27623f03ced8SAlex Deucher } 27633f03ced8SAlex Deucher drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 27643f03ced8SAlex Deucher break; 27653f03ced8SAlex Deucher case ENCODER_OBJECT_ID_SI170B: 27663f03ced8SAlex Deucher case ENCODER_OBJECT_ID_CH7303: 27673f03ced8SAlex Deucher case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 27683f03ced8SAlex Deucher case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 27693f03ced8SAlex Deucher case ENCODER_OBJECT_ID_TITFP513: 27703f03ced8SAlex Deucher case ENCODER_OBJECT_ID_VT1623: 27713f03ced8SAlex Deucher case ENCODER_OBJECT_ID_HDMI_SI1930: 27723f03ced8SAlex Deucher case ENCODER_OBJECT_ID_TRAVIS: 27733f03ced8SAlex Deucher case ENCODER_OBJECT_ID_NUTMEG: 27743f03ced8SAlex Deucher /* these are handled by the primary encoders */ 27753f03ced8SAlex Deucher radeon_encoder->is_ext_encoder = true; 27763f03ced8SAlex Deucher if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 277713a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 277813a3d91fSVille Syrjälä DRM_MODE_ENCODER_LVDS, NULL); 27793f03ced8SAlex Deucher else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 278013a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 278113a3d91fSVille Syrjälä DRM_MODE_ENCODER_DAC, NULL); 27823f03ced8SAlex Deucher else 278313a3d91fSVille Syrjälä drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, 278413a3d91fSVille Syrjälä DRM_MODE_ENCODER_TMDS, NULL); 27853f03ced8SAlex Deucher drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 27863f03ced8SAlex Deucher break; 27873f03ced8SAlex Deucher } 27883f03ced8SAlex Deucher } 2789