| /linux/Documentation/devicetree/bindings/power/reset/ |
| H A D | keystone-reset.txt | 1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
7 SoC. Each watchdog timer event input is connected to the Reset Mux
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
16 - ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
18 reset control registers.
20 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
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| /linux/drivers/phy/amlogic/ |
| H A D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/reset.h>
23 /* [31] soft reset for the phy.
24 * 1: reset. 0: dessert the reset.
25 * [30] clock lane soft reset.
26 * [29] data byte lane 3 soft reset.
27 * [28] data byte lane 2 soft reset.
28 * [27] data byte lane 1 soft reset.
29 * [26] data byte lane 0 soft reset.
32 * [12] mipi HSbyteclk enable.
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | hisilicon,histb-xhci.txt | 6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
19 "soft": for soft reset
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| /linux/drivers/power/reset/ |
| H A D | brcm-kona-reset.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 * A soft reset is triggered by writing a 0 to bit 0 of the soft reset in kona_reset_handler()
23 * and the enable bit in the write access enable register. in kona_reset_handler()
39 return devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, in kona_reset_probe()
44 { .compatible = "brcm,bcm21664-resetmgr" },
51 .name = "brcm-kona-reset",
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu_v13_0_4_ppsmc.h | 27 /*! @mainpage PMFW-PPS (PPLib) Message Interface
70 #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
74 #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCL…
76 #define PPSMC_MSG_EnableGfxImu 0x16 ///< Enable GFX IMU
82 #define PPSMC_MSG_SetSoftMaxGfxClk 0x1B ///< Set soft max for GFX CLK
85 #define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x1D ///< Set soft max for SOC CLK
86 #define PPSMC_MSG_SetSoftMaxFclkByFreq 0x1E ///< Set soft max for FCLK
87 #define PPSMC_MSG_SetSoftMaxVcn 0x1F ///< Set soft max for VCN clocks (VCLK and DCL…
93 #define PPSMC_MSG_SetSoftMinSocclkByFreq 0x24 ///< Set soft min for SOC CLK
99 …pIspByTile 0x2A ///< This message is used to power up ISP tiles and enable the ISP DPM
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| /linux/sound/soc/codecs/ |
| H A D | tda7419.c | 1 // SPDX-License-Identifier: GPL-2.0-only
136 if (tvc->reg == tvc->rreg) in tda7419_vol_is_stereo()
146 (struct tda7419_vol_control *)kcontrol->private_value; in tda7419_vol_info()
148 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; in tda7419_vol_info()
149 uinfo->count = tda7419_vol_is_stereo(tvc) ? 2 : 1; in tda7419_vol_info()
150 uinfo->value.integer.min = tvc->min; in tda7419_vol_info()
151 uinfo->value.integer.max = tvc->max; in tda7419_vol_info()
163 val = 0 - val; in tda7419_vol_get_value()
166 val = val - thresh; in tda7419_vol_get_value()
168 val = thresh - val; in tda7419_vol_get_value()
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| /linux/arch/powerpc/kernel/ |
| H A D | irq_64.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
39 #include <linux/radix-tree.h>
74 WARN_ON(!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)); in next_interrupt()
79 * We are responding to the next interrupt, so interrupt-off in next_interrupt()
80 * latencies should be reset here. in next_interrupt()
90 if (local_paca->irq_happened & irq) { in irq_happened_test_and_clear()
91 local_paca->irq_happened &= ~irq; in irq_happened_test_and_clear()
108 WARN_ON(!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)); in __replay_soft_interrupts()
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | img,pistachio-reset.txt | 1 Pistachio Reset Controller
4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
25 compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd";
28 clock-names = "sys";
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| /linux/include/soc/at91/ |
| H A D | sama7-ddr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
19 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
30 #define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
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| /linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_crtc.c | 1 // SPDX-License-Identifier: GPL-2.0+
17 * After the CRTC soft reset, the vblank counter would be reset to zero.
24 struct lsdc_device *ldev = lcrtc->ldev; in lsdc_crtc0_soft_reset()
31 /* Soft reset bit, active low */ in lsdc_crtc0_soft_reset()
50 struct lsdc_device *ldev = lcrtc->ldev; in lsdc_crtc1_soft_reset()
57 /* Soft reset bit, active low */ in lsdc_crtc1_soft_reset()
76 struct lsdc_device *ldev = lcrtc->ldev; in lsdc_crtc0_enable()
82 * This may happen in extremely rare cases, but a soft reset can in lsdc_crtc0_enable()
87 drm_warn(&ldev->base, "%s stall\n", lcrtc->base.name); in lsdc_crtc0_enable()
96 struct lsdc_device *ldev = lcrtc->ldev; in lsdc_crtc0_disable()
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| /linux/drivers/parisc/ |
| H A D | power.c | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * HP PARISC soft power switch driver
5 * Copyright (c) 2001-2023 Helge Deller <deller@gmx.de>
8 * Support of the soft power switch button may be enabled or disabled at
82 /* filename in /proc which can be used to enable/disable the power switch */
85 /* soft power switch enabled/disabled */
90 .procname = "soft-power",
122 * Non-Gecko-style machines: in kpowerswd()
134 * Warning: Some machines never reset the DIAG flag, even if in kpowerswd()
174 * be executed any longer. This function then re-enables
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| /linux/Documentation/PCI/ |
| H A D | pci-error-recovery.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 :Authors: - Linas Vepstas <linasvepstas@gmail.com>
9 - Richard Lary <rlary@us.ibm.com>
10 - Mike Mason <mmlnx@us.ibm.com>
17 and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
22 offered, so that the affected PCI device(s) are reset and put back
23 into working condition. The reset phase requires coordination
32 including multiple instances of a device driver on multi-function
34 waiting for some i/o-space register to change, when it never will.
39 is forced by the need to handle multi-function devices, that is,
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| /linux/drivers/media/platform/imagination/ |
| H A D | e5010-jpeg-enc-hw.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
7 * Author: David Huang <d-huang@ti.com>
14 #include "e5010-jpeg-enc-hw.h"
64 dev_warn(dev, "MMU soft reset timed out, forcing system soft reset\n"); in e5010_reset()
71 void e5010_hw_bypass_mmu(void __iomem *mmu_base, u32 enable) in e5010_hw_bypass_mmu() argument
78 enable); in e5010_hw_bypass_mmu()
81 int e5010_hw_enable_output_address_error_irq(void __iomem *core_base, u32 enable) in e5010_hw_enable_output_address_error_irq() argument
87 enable); in e5010_hw_enable_output_address_error_irq()
106 int e5010_hw_enable_picture_done_irq(void __iomem *core_base, u32 enable) in e5010_hw_enable_picture_done_irq() argument
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| /linux/arch/arc/kernel/ |
| H A D | intc-compact.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
18 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
19 * -Called very early (start_kernel -> setup_arch -> setup_processor)
22 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
32 * Write to register, even if no LV2 IRQs configured to reset it in arc_init_IRQ()
38 pr_info("Level-2 interrupts bitset %x\n", level_mask); in arc_init_IRQ()
54 * ARC700 core includes a simple on-chip intc supporting
55 * -per IRQ enable/disable
56 * -2 levels of interrupts (high/low)
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| /linux/arch/arm/mach-mvebu/ |
| H A D | system-controller.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * but rather provide system-level features. This basic
14 * system-controller driver provides a device tree binding for those
19 * soft-reset, but it might be extended in the future.
28 #include "mvebu-soc-id.h"
79 .compatible = "marvell,orion-system-controller",
82 .compatible = "marvell,armada-370-xp-system-controller",
85 .compatible = "marvell,armada-375-system-controller",
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| /linux/drivers/watchdog/ |
| H A D | octeon-wdt-main.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2007-2017 Cavium, Inc.
11 * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>,
16 * "AS-IS" and at no charge.
25 * only result is a watchdog reset sooner than was requested. But
31 * irq is asserted, then if it is not reset, after the next period NMI
32 * is asserted, then after an additional period a chip wide soft reset.
33 * So for the software counters, we reset watchdog after each period
37 * to the serial port and then wait for the reset.
40 * one CPU suffers a lockup, we also get a register dump and reset.
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| /linux/arch/sparc/include/asm/ |
| H A D | bbc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
22 #define BBC_SPG 0x06 /* [B] Soft POR Gen */
23 #define BBC_SXG 0x07 /* [B] Soft XIR Gen */
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pcie-histb.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
22 #include <linux/reset.h>
24 #include "pcie-designware.h"
26 #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
69 return readl(histb_pcie->ctrl + reg); in histb_pcie_readl()
74 writel(val, histb_pcie->ctrl + reg); in histb_pcie_writel()
77 static void histb_pcie_dbi_w_mode(struct dw_pcie_rp *pp, bool enable) in histb_pcie_dbi_w_mode() argument
84 if (enable) in histb_pcie_dbi_w_mode()
91 static void histb_pcie_dbi_r_mode(struct dw_pcie_rp *pp, bool enable) in histb_pcie_dbi_r_mode() argument
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| /linux/include/soc/canaan/ |
| H A D | k210-sysctl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
11 * Taken from Kendryte SDK (kendryte-standalone-sdk).
22 #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */
23 #define K210_SYSCTL_EN_PERI 0x2C /* Peripheral clock enable */
24 #define K210_SYSCTL_SOFT_RESET 0x30 /* Soft reset ctrl */
25 #define K210_SYSCTL_PERI_RESET 0x34 /* Peripheral reset controller */
36 #define K210_SYSCTL_RESET_STAT 0x60 /* Reset source status */
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| /linux/drivers/char/mwave/ |
| H A D | 3780i.h | 3 * 3780i.h -- declarations for 3780i.c
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45 * 10/23/2000 - Alpha Release
62 #define DSP_MsaDataDSISHigh 0x0008 /* MSA data register: d-store word or high byte of i-stor…
63 #define DSP_MsaDataISLow 0x000A /* MSA data register: low word of i-store */
69 unsigned char SoftReset:1; /* RW: Soft reset 0=normal, 1=soft reset active */
76 unsigned short EnableDspInt:1; /* RW: Enable DSP to X86 ISA interrupt 0=mask it, 1=enable it */
77 unsigned short MemAutoInc:1; /* RW: Memory address auto increment, 0=disable, 1=enable */
78 unsigned short IoAutoInc:1; /* RW: I/O address auto increment, 0=disable, 1=enable */
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| /linux/arch/arm/mm/ |
| H A D | proc-sa110.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-sa110.S
5 * Copyright (C) 1997-2002 Russell King
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
11 * functions on the StrongARM-110.
18 #include <asm/asm-offsets.h>
21 #include <asm/pgtable-hwdef.h>
24 #include "proc-macros.S"
38 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
58 * Perform a soft reset of the system. Put the CPU into the
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| /linux/arch/arm/mach-omap2/ |
| H A D | hdq1w.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * IP block integration code for the HDQ1W/1-wire IP block
8 * Based on the I2C reset code in arch/arm/mach-omap2/i2c.c by
26 * omap_hdq1w_reset - reset the OMAP HDQ1W module
29 * OCP soft reset the HDQ1W IP block. Section 20.6.1.4 "HDQ1W/1-Wire
30 * Software Reset" of the OMAP34xx Technical Reference Manual Revision
32 * the reset to succeed, the HDQ1W module's internal clock gate must be
34 * module. In this sense, it's rather similar to the I2C custom reset
45 /* Enable the module's internal clocks */ in omap_hdq1w_reset()
52 oh->class->sysc->syss_offs) in omap_hdq1w_reset()
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| /linux/drivers/dma/ppc4xx/ |
| H A D | xor.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * 2006-2009 (C) DENX Software Engineering.
26 #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
27 #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
43 * XORCore Control Set and Reset Register bits
45 #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
46 #define XOR_CRSR_XAE_BIT (1<<30) /* enable */
47 #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
53 * XORCore Interrupt Enable Register
55 #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
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| /linux/sound/soc/loongson/ |
| H A D | loongson_i2s.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define I2S_CTRL_RX_EN BIT(13) /* RX enable */
34 #define I2S_CTRL_TX_EN BIT(12) /* TX enable */
35 #define I2S_CTRL_RX_DMA_EN BIT(11) /* DMA RX enable */
37 #define I2S_CTRL_TX_DMA_EN BIT(7) /* DMA TX enable */
38 #define I2S_CTRL_RESET BIT(4) /* Controller soft reset */
39 #define I2S_CTRL_MCLK_EN BIT(3) /* Enable MCLK */
40 #define I2S_CTRL_RX_INT_EN BIT(1) /* RX interrupt enable */
41 #define I2S_CTRL_TX_INT_EN BIT(0) /* TX interrupt enable */
43 #define LS_I2S_DRVNAME "loongson-i2s"
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| /linux/drivers/platform/mips/ |
| H A D | ls2k-reset.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson-2K1000 reset support
13 #define RST_CNT 0x30 /* Reset Control Register */
26 /* Sleep Enable | Soft Off*/ in ls2k_poweroff()
34 np = of_find_compatible_node(NULL, NULL, "loongson,ls2k-pm"); in ls2k_reset_init()
37 return -ENODEV; in ls2k_reset_init()
44 return -ENOMEM; in ls2k_reset_init()
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