Lines Matching +full:enable +full:- +full:soft +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * 2006-2009 (C) DENX Software Engineering.
26 #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
27 #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
43 * XORCore Control Set and Reset Register bits
45 #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
46 #define XOR_CRSR_XAE_BIT (1<<30) /* enable */
47 #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
53 * XORCore Interrupt Enable Register
55 #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
56 #define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
57 #define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
58 #define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
59 #define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
66 * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
83 * XOR hardware registers Table 19-3, UM 1.22
86 u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
97 u32 crrr; /* control reset register */
101 u32 ier; /* interrupt enable register */