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/freebsd/sys/contrib/device-tree/Bindings/c6x/
H A Ddscr.txt2 ------------------------------------
12 enable (and disable in some cases) SoC pin drivers, select peripheral clock
19 For device state control (enable/disable), each device control is assigned an
24 - compatible: must be "ti,c64x+dscr"
25 - reg: register area base and size
34 - ti,dscr-devstat
35 offset of the devstat register
37 - ti,dscr-silicon-rev
38 offset, start bit, and bitsize of silicon revision field
40 - ti,dscr-rmii-resets
[all …]
/freebsd/sys/dev/smc/
H A Dif_smcreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 /* All Banks, Offset 0xe: Bank Select Register */
37 /* Bank 0, Offset 0x0: Transmit Control Register */
39 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
43 #define TCR_NOCRC 0x0100 /* Disable/enable CRC */
45 #define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */
50 /* Bank 0, Offset 0x2: EPH Status Register */
67 /* Bank 0, Offset 0x4: Receive Control Register */
70 #define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
[all …]
H A Dapm,xgene-device-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
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H A Dvt8500.txt1 Device Tree Clock bindings for arch-vt8500
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
13 "via,vt8500-device-clock" - for a VT/WM device clock
16 - reg : shall be the control register offset from PMC base for the pll clock.
17 - clocks : shall be the input parent clock phandle for the clock. This should
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dspear_spics.txt17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
32 compatible = "st,spear-spics-gpio";
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H A Dst,spear-spics-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/st,spear-spics-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
27 const: st,spear-spics-gpio
32 gpio-controller: true
34 '#gpio-cells':
37 st-spics,peripcfg-reg:
38 description: Offset of the peripcfg register.
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/freebsd/share/man/man4/
H A Dice.42 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
73 .Bl -bullet -compact
91 .Sx Link-Level Flow Control
113 .Sx Optics and auto-negotiation
115 .Sx PCI-Express Slot Bandwidth
236 To use RDMA monitoring, more MSI-X interrupts may need to be reserved.
241 .Bd -literal -offset indent
245 The number of extra MSI-X interrupt vectors may need to be adjusted.
248 .Bd -literal -offset indent
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H A Dacpi_hp.435 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
48 driver provides support for ACPI-controlled features found on HP laptops
63 .Bl -tag -width "subsystem" -offset indent -compact
77 .Bl -tag -width "0xc0" -offset indent -compact
99 .Bl -tag -width indent
103 (read-only)
106 (read-only)
114 .Bl -tag -width indent
118 (read-only)
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H A Dvirtio_scsi.435 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
54 .Bl -tag -width "xxxxxx"
56 In the initial QEMU release with VirtIO SCSI support, in-flight
63 To enable debugging prints from the
66 .Bd -literal -offset indent
75 .Bl -tag -width 6n -offset indent
77 Enable informational prints.
79 Enable prints for driver errors.
81 Enable tracing prints.
H A Dirdma.41 .\" Copyright(c) 2016 - 2022 Intel Corporation
14 .\" - Redistributions of source code must retain the above
18 .\" - Redistributions in binary form must reproduce the above
41 .Bl -tag -width indent
53 driver provides RDMA protocol support on RDMA-capable Intel Ethernet 800 Series
65 .Bl -tag -width indent
84 Value is given as a percentage (1-100).
129 .Bl -tag -width indent
143 .Bl -enum
146 .Bd -literal -offset indent
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H A Dena.41 .\" SPDX-License-Identifier: BSD-2-Clause
3 .\" Copyright (c) 2015-2024 Amazon.com, Inc. or its affiliates.
40 .Bd -ragged -offset indent
47 .Bd -literal -offset indent
58 The driver supports a range of ENA devices, is link-speed independent
62 Some ENA devices support SR-IOV.
63 This driver is used for both the SR-IOV Physical Function (PF) and Virtual
66 The ENA devices enable high speed and low overhead network traffic
68 is advertised by the device via the Admin Queue), a dedicated MSI-X
77 Receive-side scaling (RSS) is supported for multi-core scaling.
[all …]
H A Dath.41 .\"-
2 .\" Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
39 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
61 IBSS, MBSS, WDS/DWDS TDMA, and host-based access point operation modes.
70 AR5210-based devices support 802.11a operation with transmit speeds
72 AR5211-based devices support 802.11a and 802.11b operation with transmit
75 AR5212-based devices support 802.11a, 802.11b, and 802.11g operation
83 only interoperable with other Atheros-based devices.)
84 AR5212-based and AR5416-based devices also support half- (10MHz) and quarter-width (5MHz) channels.
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/freebsd/usr.sbin/binmiscctl/
H A Dbinmiscctl.81 .\"-
38 .Fl -interpreter
40 .Fl -magic
42 .Fl -size
44 .Op Fl -mask Ar mask
45 .Op Fl -offset Ar offset
46 .Op Fl -set-enabled
47 .Op Fl -pre-open
52 .Cm enable
76 .Bl -tag -width indent
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-storm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
/freebsd/crypto/heimdal/lib/krb5/
H A Dkrb5.conf.51 .\" Copyright (c) 1999 - 2005 Kungliga Tekniska Högskolan
53 .Bd -literal -offset indent
81 consists of one or more non-whitespace characters.
83 STRINGs that are specified later in this man-page uses the following
85 .Bl -tag -width "xxx" -offset indent
93 valid encryption types are: des-cbc-crc, des-cbc-md4, des-cbc-md5,
94 des3-cbc-sha1, arcfour-hmac-md5, aes128-cts-hmac-sha1-96, and
95 aes256-cts-hmac-sha1-96 .
101 .Bl -tag -width "xxx" -offset indent
107 .Bl -enum -compact
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/freebsd/sbin/camcontrol/
H A Dcamcontrol.8123 .Op Fl S Ar offset
145 .Bk -words
171 .Op Fl a Ar enable|disable
172 .Op Fl A Ar enable|disable
173 .Op Fl s Ar enable|disable
174 .Op Fl S Ar enable|disable
208 .Op Fl D Ar enable|disable
210 .Op Fl O Ar offset
213 .Op Fl T Ar enable|disable
402 .Bl -tag -width 14n
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.c1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
132 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_accel_mask()
146 device_t pdev = accel_dev->accel_pci_dev.pci_dev; in get_ae_mask()
163 return self ? hweight32(self->accel_mask) : 0; in get_num_accels()
169 return self ? hweight32(self->ae_mask) : 0; in get_num_aes()
198 * c4xxx_set_ssm_wdtimer() - Initialize the slice hang watchdog timer.
206 struct adf_hw_device_data *hw_device = accel_dev->hw_device; in c4xxx_set_ssm_wdtimer()
208 &GET_BARS(accel_dev)[hw_device->get_misc_bar_id(hw_device)]; in c4xxx_set_ssm_wdtimer()
209 struct resource *csr = misc_bar->virt_addr; in c4xxx_set_ssm_wdtimer()
[all …]
/freebsd/cddl/usr.sbin/dwatch/
H A Ddwatch.11 .\" Copyright (c) 2014-2018 Devin Teske
50 .Op Fl -
78 probe-specific data.
90 .Dl 2017 May 29 08:23:20 0.0 dtrace[60671]: dtrace -s /dev/stdin
104 .Dl date/time uid.gid execname[pid]: {->,<-, |} prov:mod:func:name ...
108 .Ql dwatch -F BEGIN
127 .Dl " -+= pid3 uid3.gid3 psargs3"
128 .Dl " \e\\-+= pid2 uid2.gid2 psargs2"
129 .Dl " \e\\-+= pid1 uid1.gid1 psargs1"
130 .Dl " \e\\-+= pid0 uid0.guid0 psargs0"
[all …]
/freebsd/sys/dev/clk/
H A Dclk_gate.c1 /*-
51 static int clknode_gate_set_gate(struct clknode *clk, bool enable);
52 static int clknode_gate_get_gate(struct clknode *clk, bool *enable);
54 uint32_t offset; member
81 clknode_gate_set_gate(struct clknode *clk, bool enable) in clknode_gate_set_gate() argument
89 rv = MD4(clk, sc->offset, sc->mask << sc->shift, in clknode_gate_set_gate()
90 (enable ? sc->on_value : sc->off_value) << sc->shift); in clknode_gate_set_gate()
95 RD4(clk, sc->offset, &reg); in clknode_gate_set_gate()
109 rv = RD4(clk, sc->offset, &reg); in clknode_gate_get_gate()
113 reg = (reg >> sc->shift) & sc->mask; in clknode_gate_get_gate()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
24 - enable-method: should be "brcm,bcm63138"
25 - resets: phandle to the relevant PMB controller, one integer indicating the internal
[all …]
/freebsd/usr.sbin/service/
H A Dservice.876 .Bl -tag -width F1
78 Enable debugging.
143 .Ex -std
149 Enable a service, then start it:
150 .Bd -literal -offset indent
151 service sshd enable
156 .Bd -literal -offset indent
162 .Bd -literal -offset indent
167 .Bd -literal -offset indent
172 .Bd -literal -offset indent
[all …]
/freebsd/sys/dev/e1000/
H A De1000_phy.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
68 * Setups up the function pointers to no-op functions
72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic()
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->ops.acquire = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
78 phy->ops.check_polarity = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
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/freebsd/sbin/mdconfig/
H A Dmdconfig.85 .\" Poul-Henning Kamp All rights reserved.
80 .Bl -tag -width indent
94 .Bl -tag -width "malloc"
102 malloc-backed memory disk is a very easy way to
192 .Bd -literal -offset indent
197 .Bl -tag -width indent
208 backed devices: enable/disable caching of data in system caches.
223 The result is that with normal (non-zfs) caching,
234 Enable/disable compression features to reduce memory usage.
236 Disable/enable extra sanity checks to prevent the user from doing something
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