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/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3368-evb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2015 Caesar Wang <wxt@rock-chips.com>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
13 mmc0 = &emmc;
17 stdout-path = "serial2:115200n8";
26 compatible = "pwm-backlight";
27 brightness-levels = <
60 default-brightness-level = <128>;
61 enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
[all …]
H A Drk3368-orion-r68-meta.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
12 compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
17 mmc1 = &emmc;
21 stdout-path = "serial2:115200n8";
29 emmc_pwrseq: emmc-pwrseq {
30 compatible = "mmc-pwrseq-emmc";
31 pinctrl-0 = <&emmc_reset>;
32 pinctrl-names = "default";
[all …]
H A Drk3368-r88.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
17 mmc1 = &emmc;
21 stdout-path = "serial2:115200n8";
29 emmc_pwrseq: emmc-pwrseq {
30 compatible = "mmc-pwrseq-emmc";
31 pinctrl-0 = <&emmc_reset>;
32 pinctrl-names = "default";
33 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>;
[all …]
H A Dpx30-ringneck.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
13 mmc0 = &emmc;
20 attiny-updi-gate-regulator {
21 compatible = "regulator-output";
22 vout-supply = <&vg_attiny_updi>;
25 emmc_pwrseq: emmc-pwrseq {
26 compatible = "mmc-pwrseq-emmc";
27 pinctrl-0 = <&emmc_reset>;
[all …]
H A Dpx30-pp1516.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
14 mmc0 = &emmc;
18 stdout-path = "serial5:115200n8";
22 compatible = "pwm-backlight";
23 power-supply = <&vcc5v0_sys>;
28 compatible = "pwm-beeper";
[all …]
H A Dpx30-cobra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
16 mmc0 = &emmc;
20 stdout-path = "serial5:115200n8";
24 compatible = "pwm-backlight";
25 power-supply = <&vcc5v0_sys>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7622-rfb1.dts6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
18 chassis-type = "embedded";
19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
[all …]
H A Dmt7622-bananapi-bpi-r64.dts5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
14 mmc0 = &emmc;
18 stdout-path = "serial2:115200n8";
31 power_button: power-button {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pwr_key_l>;
36 key-power {
[all …]
H A Drk3288-phycore-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device tree file for Phytec phyCORE-RK3288 SoM
8 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "phytec,rk3288-phycore-som", "rockchip,rk3288";
29 ext_gmac: external-gmac-clock {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <125000000>;
33 clock-output-names = "ext_gmac";
36 leds: user-leds {
[all …]
H A Drv1126-pinctrl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <arm64/rockchip/rockchip-pinconf.dtsi>
15 /omit-if-no-ref/
16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17 rockchip,pins =
22 emmc {
23 /omit-if-no-ref/
24 emmc_rstnout: emmc-rstnout {
25 rockchip,pins =
[all …]
H A Drk3288-veyron-pinky.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "../cros-ec-sbs.dtsi"
14 compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
17 /delete-node/regulator-backlight;
18 /delete-node/regulator-panel;
19 /delete-node/emmc-pwrseq;
20 /delete-node/vcc18-lcd;
24 /delete-property/power-supply;
[all …]
H A Drk3066a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/clock/rk3066a-cru.h>
10 #include <dt-bindings/power/rk3066-power.h>
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "rockchip,rk3066-smp";
28 compatible = "arm,cortex-a9";
29 next-level-cache = <&L2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dpoplar-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/pinctrl/hisi.h>
19 emmc_pins_1: emmc-pins-1 {
20 pinctrl-single,pins = <
31 pinctrl-single,bias-pulldown = <
34 pinctrl-single,bias-pullup = <
37 pinctrl-single,slew-rate = <
40 pinctrl-single,drive-strength = <
45 emmc_pins_2: emmc-pins-2 {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dairoha,en7581-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The Airoha's EN7581 Pin controller is used to control SoC pins.
17 const: airoha,en7581-pinctrl
22 gpio-controller: true
24 '#gpio-cells':
27 gpio-ranges:
[all …]
H A Dmediatek,mt7986-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctr
[all...]
H A Drealtek,rtd1315e-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - TY Chang <tychang@realtek.com>
14 The Realtek DHC RTD1315E is a high-definition media processor SoC. The
20 const: realtek,rtd1315e-pinctrl
26 '-pins$':
29 - $ref: pincfg-node.yaml#
30 - $ref: pinmux-node.yaml#
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/sophgo/
H A Dsg2042-evb-v2.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v2", "sophgo,sg2042";
16 stdout-path = "serial0";
19 pwmfan: pwm-fan {
20 compatible = "pwm-fan";
21 cooling-levels = <103 128 179 230 255>;
23 #cooling-cells = <2>;
26 thermal-zones {
[all …]
H A Dsg2042-milkv-pioneer.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
12 model = "Milk-V Pioneer";
16 stdout-path = "serial0";
19 gpio-power {
20 compatible = "gpio-keys";
22 key-power {
26 linux,input-type = <EV_KEY>;
27 debounce-interval = <100>;
[all …]
H A Dsg2042-evb-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "sophgo,sg2042-evb-v1", "sophgo,sg2042";
16 stdout-path = "serial0";
19 gpio-power {
20 compatible = "gpio-keys";
22 key-power {
26 linux,input-type = <EV_KEY>;
27 debounce-interval = <100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Drzg2l-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
13 #define EMMC 1 macro
18 * Disable eMMC by setting "#define EMMC 0" above.
20 #define SDHI (!EMMC)
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
[all …]
H A Drzv2-evk-cn15-emmc.dtso1 // SPDX-License-Identifier: GPL-2.0
3 * Shared DT overlay for the eMMC Sub Board (RTK0EF0186B02000BJ), which
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
22 sdhi0_emmc_pins: emmc-pins {
23 sd0-clk {
24 pins = "SD0CLK";
25 renesas,output-impedance = <3>;
26 slew-rate = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-s4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/gpio/meson-s4-gpio.h>
10 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
11 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
12 #include <dt-bindings/power/meson-s4-power.h>
13 #include <dt-bindings/reset/amlogic,meson-s4-reset.h>
17 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/microchip/
H A Dsparx5_pcb134_emmc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Sparx5 PCB134 Reference Board (eMMC enabled)";
11 compatible = "microchip,sparx5-pcb134", "microchip,sparx5";
20 emmc_pins: emmc-pins {
24 pins = "GPIO_34", "GPIO_38", "GPIO_39",
28 drive-strength = <3>;
29 function = "emmc";
35 pinctrl-0 = <&emmc_pins>;
36 non-removable;
[all …]
H A Dsparx5_pcb135_emmc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 model = "Sparx5 PCB135 Reference Board (eMMC enabled)";
11 compatible = "microchip,sparx5-pcb135", "microchip,sparx5";
20 emmc_pins: emmc-pins {
24 pins = "GPIO_34", "GPIO_38", "GPIO_39",
28 drive-strength = <3>;
29 function = "emmc";
35 pinctrl-0 = <&emmc_pins>;
36 non-removable;
[all …]

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