Home
last modified time | relevance | path

Searched +full:el3 +full:- (Results 1 – 25 of 32) sorted by relevance

12

/linux/Documentation/arch/arm64/
H A Dbooting.rst13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level, EL3 is the highest priority
33 ---------------------------
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
96 - code0/code1 are responsible for branching to stext.
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
21 - one or more IRS (Interrupt Routing Service)
22 - zero or more ITS (Interrupt Translation Service)
25 - PE-Private Peripheral Interrupts (PPI)
26 - Shared Peripheral Interrupts (SPI)
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dintel,stratix10-svc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
11 - Mahesh Rao <mahesh.rao@altera.com>
14 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
21 communication with SDM, only the secure world of software (EL3, Exception
23 exception layers must channel through the EL3 software whenever it needs
30 code running in EL3.
[all …]
/linux/Documentation/translations/zh_TW/arch/arm64/
H A Dbooting.txt1 SPDX-License-Identifier: GPL-2.0
15 ---------------------------------------------------------------------
30 ---------------------------------------------------------------------
40 AArch64 異常模型由多個異常級（EL0 - EL3）組成，對於 EL0 和 EL1 異常級
42 EL3 是最高特權級，且僅存在於安全模式下。
58 -----------------
69 ---------------
81 -------------
91 -------------
111 - 自 v3.17 起，除非另有說明，所有域都是小端模式。
[all …]
/linux/Documentation/translations/zh_CN/arch/arm64/
H A Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
38 EL3 是最高特权级，且仅存在于安全模式下。
54 -----------------
65 ---------------
77 -------------
87 -------------
107 - 自 v3.17 起，除非另有说明，所有域都是小端模式。
109 - code0/code1 负责跳转到 stext.
[all …]
/linux/include/linux/firmware/intel/
H A Dstratix10-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
9 #include <linux/arm-smccc.h>
15 * monitor software in Secure Monitor Exception Level 3 (EL3).
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
24 * EL1 and EL3 communicates pointer as physical address rather than the
31 * STD call starts a operation which can be preempted by a non-secure
81 * Sync call used by service driver at EL1 to request the FPGA in EL3 to
88 * a2-7: not used.
[all …]
/linux/Documentation/driver-api/firmware/
H A Dother_interfaces.rst5 --------------
7 .. kernel-doc:: drivers/firmware/dmi_scan.c
11 --------------
13 .. kernel-doc:: drivers/firmware/edd.c
17 -------------------------------------
19 .. kernel-doc:: drivers/firmware/sysfb.c
23 ---------------------------------
28 Exception Level 3 (EL3).
33 of the requests on to a secure monitor (EL3).
35 .. kernel-doc:: include/linux/firmware/intel/stratix10-svc-client.h
[all …]
/linux/drivers/net/ethernet/3com/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
20 config EL3 config
50 (PC-card) Fast Ethernet card to your computer.
60 (PC-card) Ethernet card to your computer.
93 3C990-TX, 3CR990-TX-95, 3CR990-TX-97, 3CR990-FX-95, 3CR990-FX-97,
94 3CR990SVR, 3CR990SVR95, 3CR990SVR97, 3CR990-FX-95 Server,
95 3CR990-FX-97 Server, 3C990B-TX-M, 3C990BSVR
H A D3c589_cs.c5 * Copyright (C) 1999 David A. Hinds -- dahinds@users.sourceforge.net
124 #define WN0_IRQ 0x08 /* Window 0: Set IRQ line in bits 12-15. */
200 dev_dbg(&link->dev, "3c589_attach()\n"); in tc589_probe()
205 return -ENOMEM; in tc589_probe()
207 link->priv = dev; in tc589_probe()
208 lp->p_dev = link; in tc589_probe()
210 spin_lock_init(&lp->lock); in tc589_probe()
211 link->resource[0]->end = 16; in tc589_probe()
212 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_16; in tc589_probe()
214 link->config_flags |= CONF_ENABLE_IRQ; in tc589_probe()
[all …]
H A D3c509.c3 Written 1993-2000 by Donald Becker.
5 Copyright 1994-2000 by Donald Becker.
20 a priori which of several ISA-mode cards will be detected first.
36 other cleanups. -djb
39 v1.13 9/8/97 Made 'max_interrupt_work' an insmod-settable variable -djb
40 v1.14 10/15/97 Avoided waiting..discard message for fast machines -djb
41 v1.15 1/31/98 Faster recovery for Tx errors. -djb
42 v1.16 2/3/98 Different ID port handling to avoid sound cards. -djb
44 - Avoid bogus detect of 3c590's (Andrzej Krzysztofowicz)
45 - Reviewed against 1.18 from scyld.com
[all …]
H A D3c574_cs.c3 Written 1993-1998 by
27 II. Board-specific settings
29 None -- PC cards are autoconfigured.
33 The 3c574 uses a Boomerang-style interface, without the bus-master capability.
39 RunnerWrCtrl. These are 11 bit down-counters that are preloaded with the
41 or Tx FIFO. The chip is then able to hide the internal-PCI-bus to PC-card
46 0x0800-0x0fff can translated to the PIO FIFO. Thus memory operations (faster
56 register set, 1-5 are various PC card control registers, and 16-31 are
167 On the "Odie" this window is always mapped at offsets 0x10-0x1f.
212 code size of a per-interface flag is not worthwhile. */
[all …]
/linux/tools/perf/arch/arm64/util/
H A Darm64_exception_types.h1 // SPDX-License-Identifier: GPL-2.0
13 /* The hyp-stub will return this for any kvm_call_hyp() call */
39 /* Unallocated EC: 0x0F - 0x10 */
54 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
64 /* Unallocated EC: 0x29 - 0x2B */
75 /* Unallocated EC: 0x36 - 0x37 */
81 /* Unallocated EC: 0x3D - 0x3F */
/linux/arch/arm64/include/asm/
H A Dkvm_pkvm.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 - Google LLC
14 /* Maximum number of VMs that can co-exist under pKVM. */
26 * This functions as an allow-list of protected VM capabilities.
56 unsigned long nr_pages = reg->size >> PAGE_SHIFT; in hyp_vmemmap_memblock_size()
59 start = (reg->base >> PAGE_SHIFT) * vmemmap_entry_size; in hyp_vmemmap_memblock_size()
64 return end - start; in hyp_vmemmap_memblock_size()
102 /* Cover all of memory with page-granularity */ in __hyp_pgtable_total_pages()
105 res += __hyp_pgtable_max_pages(reg->size >> PAGE_SHIFT); in __hyp_pgtable_total_pages()
128 * Include an extra 16 pages to safely upper-bound the worst case of in host_s2_pgtable_pages()
[all …]
H A Desr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - ARM Ltd
28 /* Unallocated EC: 0x0F - 0x10 */
43 #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
53 /* Unallocated EC: 0x29 - 0x2B */
64 /* Unallocated EC: 0x36 - 0x37 */
70 /* Unallocated EC: 0x3D - 0x3F */
133 #define ESR_ELx_FSC_ADDRSZ_nL(n) ((n) == -1 ? 0x25 : 0x2C)
185 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
268 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
[all …]
/linux/drivers/firmware/efi/
H A Dcper-arm.c1 // SPDX-License-Identifier: GPL-2.0
28 "AArch64 EL3 context registers",
245 printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); in cper_print_proc_arm()
247 len = proc->section_length - (sizeof(*proc) + in cper_print_proc_arm()
248 proc->err_info_num * (sizeof(*err_info))); in cper_print_proc_arm()
250 printk("%ssection length: %d\n", pfx, proc->section_length); in cper_print_proc_arm()
252 printk("%sfirmware-generated error record is incorrect\n", pfx); in cper_print_proc_arm()
253 printk("%sERR_INFO_NUM is %d\n", pfx, proc->err_info_num); in cper_print_proc_arm()
257 if (proc->validation_bits & CPER_ARM_VALID_MPIDR) in cper_print_proc_arm()
259 pfx, proc->mpidr); in cper_print_proc_arm()
[all …]
/linux/arch/arm64/kvm/
H A Dpmu-emul.c1 // SPDX-License-Identifier: GPL-2.0-only
35 return container_of(pmc, struct kvm_vcpu, arch.pmu.pmc[pmc->idx]); in kvm_pmc_to_vcpu()
40 return &vcpu->arch.pmu.pmc[cnt_idx]; in kvm_vcpu_idx_to_pmc()
75 if (kvm_has_feat(kvm, ID_AA64PFR0_EL1, EL3, IMP)) in kvm_pmu_evtyper_mask()
84 * kvm_pmc_is_64bit - determine if counter is 64bit
91 return (pmc->idx == ARMV8_PMU_CYCLE_IDX || in kvm_pmc_is_64bit()
92 kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5)); in kvm_pmc_is_64bit()
100 if (kvm_pmu_counter_is_hyp(vcpu, pmc->idx)) in kvm_pmc_has_64bit_overflow()
103 return (pmc->idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) || in kvm_pmc_has_64bit_overflow()
104 (pmc->idx == ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC)); in kvm_pmc_has_64bit_overflow()
[all …]
H A Dhandle_exit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
21 #include <asm/debug-monitors.h>
42 vcpu->stat.hvc_exit_stat++; in handle_hvc()
67 * "If an SMC instruction executed at Non-secure EL1 is in handle_smc()
72 * otherwise return to the same address. Furthermore, pre-incrementing in handle_smc()
90 * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed in handle_smc()
91 * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than in handle_smc()
116 * kvm_handle_wfx - handle a wait-for-interrupts or wait-for-event
[all …]
H A Dconfig.c1 // SPDX-License-Identifier: GPL-2.0-only
105 * Declare the dependency between a non-FGT register, a set of
142 #define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP
278 * Revists this if KVM ever supports SME -- this really should in feat_sme_smps()
290 * Revists this if KVM ever supports SPE -- this really should in feat_spe_fds()
300 * Revists this if KVM ever supports both MPAM and TRBE -- in feat_trbe_mpam()
1185 return map->flags & RES0_POINTER ? ~(*map->res0p) : map->bits; in reg_feat_map_bits()
1190 check_feat_map(r->bit_feat_map, r->bit_feat_map_sz, in check_reg_desc()
1191 ~reg_feat_map_bits(&r->feat_map), r->name); in check_reg_desc()
1217 u64 regval = kvm->arch.id_regs[map->regidx]; in idreg_feat_match()
[all …]
H A Dsys_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
20 #include <linux/irqchip/arm-gic-v3.h>
25 #include <asm/debug-monitors.h>
74 "sys_reg read to write-only register"); in read_from_write_only()
82 "sys_reg write to read-only register"); in write_to_read_only()
142 /* Non-mapped EL2 registers are by definition in memory. */ in locate_direct_register()
154 loc->loc = SR_LOC_MEMORY; in locate_mapped_el2_register()
158 loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED; in locate_mapped_el2_register()
[all …]
H A Demulate-nested.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 - Linaro and Columbia University
448 [id - __MULTIPLE_CONTROL_BITS__] = \
574 KVM_BUG_ON(1, vcpu->kvm); in check_mdcr_hpmn()
585 [id - __COMPLEX_CONDITIONS__] = fn
607 * [63] RES0 - Must be zero, as lost on insertion in the xarray
657 * re-injected in the nested hypervisor.
1988 * read-side mappings, and only the write-side mappings that
2074 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", in print_nv_trap_error()
2075 type, tc->line, in print_nv_trap_error()
[all …]
H A Dnested.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 - Columbia University and Linaro Ltd.
28 /* -1 when not mapped on a CPU */
39 * Ratio of live shadow S2 MMU per vcpu. This is a trade-off between
48 kvm->arch.nested_mmus = NULL; in kvm_init_nested()
49 kvm->arch.nested_mmus_size = 0; in kvm_init_nested()
50 atomic_set(&kvm->arch.vncr_map_count, 0); in kvm_init_nested()
70 struct kvm *kvm = vcpu->kvm; in kvm_vcpu_init_nested()
74 if (test_bit(KVM_ARM_VCPU_HAS_EL2_E2H0, kvm->arch.vcpu_features) && in kvm_vcpu_init_nested()
76 return -EINVAL; in kvm_vcpu_init_nested()
[all …]
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/irqchip/arm-gic-v3.h>
82 * - Needed by common Linux distributions (e.g., floating point)
83 * - Trivial to support, e.g., supporting the feature does not introduce or
85 * - Cannot be trapped or prevent the guest from using anyway
92 MAX_FEAT(ID_AA64PFR0_EL1, EL3, IMP),
171 * However, both have Not-Implemented values that are non-zero. Define them
200 u64 min_signed = (1UL << width) - 1UL; in get_restricted_features()
201 u64 sign_bit = 1UL << (width - 1); in get_restricted_features()
202 u64 mask = GENMASK_ULL(width + shift - 1, shift); in get_restricted_features()
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
476 0b0001 EL3
1217 UnsignedEnum 15:12 EL3
1371 0b11 EL3
/linux/tools/testing/selftests/kvm/arm64/
H A Dset_id_regs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * set_id_regs - Test for setting ID register from usersapce.
139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
271 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0); in get_safe_value()
273 if (ftr_bits->sign == FTR_UNSIGNED) { in get_safe_value()
274 switch (ftr_bits->type) { in get_safe_value()
276 ftr = ftr_bits->safe_val; in get_safe_value()
279 if (ftr > ftr_bits->safe_val) in get_safe_value()
280 ftr--; in get_safe_value()
296 switch (ftr_bits->type) { in get_safe_value()
[all …]
/linux/arch/arm64/kernel/
H A Dproton-pack.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
20 #include <linux/arm-smccc.h>
28 #include <asm/debug-monitors.h>
72 * - Mitigated in hardware and advertised by ID_AA64PFR0_EL1.CSV2.
73 * - Mitigated in hardware and listed in our "safe list".
74 * - Mitigated in software by firmware.
75 * - Mitigated in software by a CPU-specific dance in the kernel and a
77 * - Vulnerable.
97 pr_info_once("spectre-v2 mitigation disabled by command line option\n"); in spectre_v2_mitigations_off()
[all …]

12