Lines Matching +full:el3 +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 - Linaro and Columbia University
448 [id - __MULTIPLE_CONTROL_BITS__] = \
574 KVM_BUG_ON(1, vcpu->kvm); in check_mdcr_hpmn()
585 [id - __COMPLEX_CONDITIONS__] = fn
607 * [63] RES0 - Must be zero, as lost on insertion in the xarray
657 * re-injected in the nested hypervisor.
1988 * read-side mappings, and only the write-side mappings that
2074 "(%d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d) (err=%d)\n", in print_nv_trap_error()
2075 type, tc->line, in print_nv_trap_error()
2076 sys_reg_Op0(tc->encoding), sys_reg_Op1(tc->encoding), in print_nv_trap_error()
2077 sys_reg_CRn(tc->encoding), sys_reg_CRm(tc->encoding), in print_nv_trap_error()
2078 sys_reg_Op2(tc->encoding), in print_nv_trap_error()
2079 sys_reg_Op0(tc->end), sys_reg_Op1(tc->end), in print_nv_trap_error()
2080 sys_reg_CRn(tc->end), sys_reg_CRm(tc->end), in print_nv_trap_error()
2081 sys_reg_Op2(tc->end), in print_nv_trap_error()
2161 if ((BIT(tc.bit) & rmasks->res0) && in aggregate_fgt()
2162 (!wmasks || (BIT(tc.bit) & wmasks->res0))) in aggregate_fgt()
2166 rmasks->mask |= BIT(tc.bit) & ~rmasks->res0; in aggregate_fgt()
2168 rmasks->nmask |= BIT(tc.bit) & ~rmasks->res0; in aggregate_fgt()
2172 wmasks->mask |= BIT(tc.bit) & ~wmasks->res0; in aggregate_fgt()
2174 wmasks->nmask |= BIT(tc.bit) & ~wmasks->res0; in aggregate_fgt()
2182 unsigned long duplicate = masks->mask & masks->nmask; in check_fgt_masks()
2183 u64 res0 = masks->res0; in check_fgt_masks()
2191 masks->str, i); in check_fgt_masks()
2194 ret = -EINVAL; in check_fgt_masks()
2197 masks->res0 = ~(masks->mask | masks->nmask); in check_fgt_masks()
2198 if (masks->res0 != res0) in check_fgt_masks()
2200 masks->str, masks->res0, res0); in check_fgt_masks()
2245 if (cgt->tc.val & BIT(63)) { in populate_nv_trap_config()
2247 ret = -EINVAL; in populate_nv_trap_config()
2250 for_each_encoding_in(enc, cgt->encoding, cgt->end) { in populate_nv_trap_config()
2252 xa_mk_value(cgt->tc.val), GFP_KERNEL); in populate_nv_trap_config()
2254 ret = -EINVAL; in populate_nv_trap_config()
2280 if (fgt->tc.fgt >= __NR_FGT_GROUP_IDS__) { in populate_nv_trap_config()
2281 ret = -EINVAL; in populate_nv_trap_config()
2285 for_each_encoding_in(enc, fgt->encoding, fgt->end) { in populate_nv_trap_config()
2289 ret = -EINVAL; in populate_nv_trap_config()
2293 tc.val |= fgt->tc.val; in populate_nv_trap_config()
2303 ret = -EINVAL; in populate_nv_trap_config()
2311 ret = -EINVAL; in populate_nv_trap_config()
2325 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; in populate_nv_trap_config()
2331 ret = -EINVAL; in populate_nv_trap_config()
2353 if (idx >= (BIT(TC_SRI_BITS) - 1)) { in populate_sysreg_config()
2354 kvm_err("sysreg %s (%d) out of range\n", sr->name, idx); in populate_sysreg_config()
2355 return -EINVAL; in populate_sysreg_config()
2358 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2); in populate_sysreg_config()
2363 sr->name, idx - 1, tc.sri); in populate_sysreg_config()
2364 return -EINVAL; in populate_sysreg_config()
2380 val = __vcpu_sys_reg(vcpu, tb->index); in get_behaviour()
2381 if ((val & tb->mask) == tb->value) in get_behaviour()
2382 b |= tb->behaviour; in get_behaviour()
2394 case __RESERVED__ ... __MULTIPLE_CONTROL_BITS__ - 1: in __compute_trap_behaviour()
2398 case __MULTIPLE_CONTROL_BITS__ ... __COMPLEX_CONDITIONS__ - 1: in __compute_trap_behaviour()
2400 cgids = coarse_control_combo[id - __MULTIPLE_CONTROL_BITS__]; in __compute_trap_behaviour()
2406 b |= ccc[id - __COMPLEX_CONDITIONS__](vcpu); in __compute_trap_behaviour()
2425 /* Only handle the VNCR-backed regs for now */ in kvm_get_sysreg_res0()
2429 masks = kvm->arch.sysreg_masks; in kvm_get_sysreg_res0()
2431 return masks->mask[sr - __VNCR_START__].res0; in kvm_get_sysreg_res0()
2437 struct kvm *kvm = vcpu->kvm; in check_fgt_bit()
2483 * for this sysreg, and that it cannot be re-injected into the in triage_sysreg_trap()
2495 (vcpu->kvm->arch.fgu[tc.fgt] & BIT(tc.bit))) { in triage_sysreg_trap()
2596 *sr_index = tc.sri - 1; in triage_sysreg_trap()
2642 * - trying to return to EL3 in kvm_check_illegal_exception_return()
2643 * - trying to return to an illegal M value in kvm_check_illegal_exception_return()
2644 * - trying to return to a 32bit EL in kvm_check_illegal_exception_return()
2645 * - trying to return to EL1 with HCR_EL2.TGE set in kvm_check_illegal_exception_return()
2689 if (kvm_has_pauth(vcpu->kvm, FPACCOMBINE) && !(spsr & PSR_IL_BIT)) { in kvm_emulate_nested_eret()
2749 kvm_err("Unexpected call to %s for the non-nesting configuration\n", in kvm_inject_nested()
2751 return -EINVAL; in kvm_inject_nested()
2815 * - Current exception level is EL2, and in kvm_inject_nested_irq()
2816 * - virtual HCR_EL2.TGE == 0 in kvm_inject_nested_irq()
2817 * - virtual HCR_EL2.IMO == 0 in kvm_inject_nested_irq()
2819 * See Table D1-17 "Physical interrupt target and masking when EL3 is in kvm_inject_nested_irq()