| /linux/drivers/mtd/nand/ |
| H A D | ecc-mtk.c | 3 * MTK ECC controller driver.
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline int mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
145 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
148 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
151 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
152 if (dec & ecc->sectors) { in mtk_ecc_irq()
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| H A D | ecc-sw-bch.c | 3 * This file provides ECC correction for more than 1 bit per block of data,
15 #include <linux/mtd/nand-ecc-sw-bch.h>
18 * nand_ecc_sw_bch_calculate - Calculate the ECC corresponding to a data block
21 * @code: Output buffer with ECC
26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
44 * @read_ecc: ECC bytes from the chip
45 * @calc_ecc: ECC calculated from the raw data
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
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| H A D | Kconfig | 12 menu "ECC engine support"
19 bool "Software Hamming ECC engine"
31 bool "NAND ECC Smart Media byte order"
35 Software ECC according to the Smart Media Specification.
39 bool "Software BCH ECC engine"
46 ECC codes. They are used with NAND devices requiring more than 1 bit
50 bool "Macronix external hardware ECC engine"
54 This enables support for the hardware ECC engine from Macronix.
57 tristate "Mediatek hardware ECC engine"
62 This enables support for the hardware ECC engine from Mediatek.
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| /linux/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_ecc.c | 3 * JZ47xx ECC common code
19 * ingenic_ecc_calculate() - calculate ECC for a data buffer
20 * @ecc: ECC device.
21 * @params: ECC parameters.
23 * @ecc_code: output buffer with ECC.
25 * Return: 0 on success, -ETIMEDOUT if timed out while waiting for ECC
28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
37 * @ecc: ECC device.
38 * @params: ECC parameters.
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| H A D | jz4740_ecc.c | 3 * JZ4740 ECC controller driver
45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
52 /* Initialize and enable ECC hardware */ in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
57 if (calc_ecc) /* calculate ECC from data */ in jz4740_ecc_reset()
59 else /* correct data from ECC */ in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
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| H A D | ingenic_ecc.h | 17 * struct ingenic_ecc_params - ECC parameters
18 * @size: data bytes per ECC step.
19 * @bytes: ECC bytes per step.
20 * @strength: number of correctable bits per ECC step.
29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 static inline int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
46 static inline int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
53 static inline void ingenic_ecc_release(struct ingenic_ecc *ecc) in ingenic_ecc_release() argument
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| /linux/drivers/dma/ti/ |
| H A D | edma.c | 219 struct edma_cc *ecc; member
300 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
302 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
305 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
307 __raw_writel(val, ecc->base + offset); in edma_write()
310 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
313 unsigned val = edma_read(ecc, offset); in edma_modify()
317 edma_write(ecc, offset, val); in edma_modify()
320 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
322 unsigned val = edma_read(ecc, offset); in edma_or()
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| /linux/drivers/mtd/nand/raw/ |
| H A D | nand_micron.c | 15 * corrected by on-die ECC and should be rewritten.
20 * On chips with 8-bit ECC and additional bit can be used to distinguish
66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
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| H A D | lpc32xx_slc.c | 56 #define SLCCTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
63 #define SLCCFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
64 #define SLCCFG_ECC_EN (1 << 3) /* ECC enable bit */
108 /* ECC line party fetch macro */
113 * DMA requires storage space for the DMA local buffer and the hardware ECC
120 /* Number of bytes used for ECC stored in NAND per 256 bytes */
134 * NAND ECC Layout for small page NAND devices
167 .ecc = lpc32xx_ooblayout_ecc,
229 * DMA and CPU addresses of ECC work area and data buffer
325 * Prepares SLC for transfers with H/W ECC enabled
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| H A D | omap_elm.c | 98 * @bch_type: Type of BCH ecc
99 * @ecc_steps: ECC steps to assign to config
100 * @ecc_step_size: ECC step size to assign to config
101 * @ecc_syndrome_size: ECC syndrome size to assign to config
113 /* ELM cannot detect ECC errors for chunks > 1KB */ in elm_config()
115 dev_err(dev, "unsupported config ecc-size=%d\n", ecc_step_size); in elm_config()
120 dev_err(dev, "unsupported config ecc-step=%d\n", ecc_steps); in elm_config()
160 * @ecc: buffer with calculated ecc
162 * Load syndrome fragment registers with calculated ecc in reverse order.
165 struct elm_errorvec *err_vec, u8 *ecc) in elm_load_syndrome() argument
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| H A D | mtk_nand.c | 19 #include <linux/mtd/nand-ecc-mtk.h>
146 struct mtk_ecc *ecc; member
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
211 return chip->ecc.size + mtk_nand->spare_per_sector; in mtk_data_len()
225 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; in mtk_oob_ptr()
335 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
341 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
347 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
364 if (chip->ecc.size == 1024) in mtk_nfc_hw_runtime_config()
383 nfc->ecc_cfg.strength = chip->ecc.strength; in mtk_nfc_hw_runtime_config()
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| H A D | stm32_fmc2_nand.c | 28 /* ECC step size */
43 /* Max ECC buffer length */
326 /* Configure ECC algorithm (default configuration is Hamming) */ in stm32_fmc2_nfc_setup()
329 if (chip->ecc.strength == FMC2_ECC_BCH8) { in stm32_fmc2_nfc_setup()
332 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { in stm32_fmc2_nfc_setup()
341 /* Set ECC sector size */ in stm32_fmc2_nfc_setup()
397 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
403 dev_err(nfc->dev, "ECC DMA engine slave config failed\n"); in stm32_fmc2_nfc_select_chip()
407 /* Calculate ECC length needed for one sector */ in stm32_fmc2_nfc_select_chip()
408 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
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| H A D | nuvoton-ma35d1-nand-controller.c | 73 /* Define for the BCH hardware ECC engine */
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
143 .ecc = ma35_ooblayout_ecc,
248 /* Protect redundant 3 bytes and disable ECC engine */ in ma35_nand_hwecc_init()
253 if (chip->ecc.strength != 0) { in ma35_nand_hwecc_init()
254 chip->ecc.steps = mtd->writesize / chip->ecc.size; in ma35_nand_hwecc_init()
255 nvtnand->eccstatus = (chip->ecc.steps < 4) ? 1 : chip->ecc.steps / 4; in ma35_nand_hwecc_init()
258 switch (chip->ecc.strength) { in ma35_nand_hwecc_init()
260 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH8; in ma35_nand_hwecc_init()
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| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | rockchip,nand-controller.yaml | 66 nand-ecc-mode:
69 nand-ecc-step-size:
72 nand-ecc-strength:
75 The ECC configurations that can be supported are as follows.
76 NFC v600 ECC 16, 24, 40, 60
79 NFC v622 ECC 16, 24, 40, 60
82 NFC v800 ECC 16
85 NFC v900 ECC 16, 40, 60, 70
96 The NFC driver need this information to select ECC
100 rockchip,boot-ecc-strength:
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| H A D | hisi504-nand.txt | 11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
20 The following ECC strength and step size are currently supported:
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| H A D | mediatek,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mediatek,nand-ecc-engine.yaml#
7 title: MediaTek(MTK) SoCs NAND ECC engine
13 MTK NAND ECC engine can cowork with MTK raw NAND and SPI NAND controller.
18 - mediatek,mt2701-ecc
19 - mediatek,mt2712-ecc
20 - mediatek,mt7622-ecc
21 - mediatek,mt7986-ecc
25 - description: Base physical address and size of ECC.
29 - description: ECC interrupt
56 bch: ecc@1100e000 {
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| H A D | mediatek,mtk-nfc.yaml | 37 ecc-engine:
38 description: device-tree node of the required ECC engine.
48 nand-ecc-mode:
63 nand-ecc-step-size:
65 nand-ecc-strength:
78 nand-ecc-step-size:
80 nand-ecc-strength:
93 nand-ecc-step-size:
95 nand-ecc-strength:
104 - ecc-engine
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| H A D | mxicy,nand-ecc-engine.yaml | 4 $id: http://devicetree.org/schemas/mtd/mxicy,nand-ecc-engine.yaml#
7 title: Macronix NAND ECC engine
14 const: mxicy,nand-ecc-engine-rev3
46 nand-ecc-engine = <&ecc_engine0>;
50 ecc_engine0: ecc@43c40000 {
51 compatible = "mxicy,nand-ecc-engine-rev3";
65 nand-ecc-engine = <&ecc_engine1>;
70 nand-ecc-engine = <&spi_controller1>;
74 ecc_engine1: ecc@43c40000 {
75 compatible = "mxicy,nand-ecc-engine-rev3";
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| H A D | denali,nand.yaml | 40 ecc: ECC circuit clock
44 - const: ecc
84 nand-ecc-strength:
88 nand-ecc-step-size:
101 nand-ecc-strength:
106 nand-ecc-step-size:
119 nand-ecc-strength:
123 nand-ecc-step-size:
143 clock-names = "nand", "nand_x", "ecc";
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| /linux/arch/arm/mach-socfpga/ |
| H A D | ocram.c | 21 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); in socfpga_init_ocram_ecc()
23 pr_err("Unable to find socfpga-ocram-ecc\n"); in socfpga_init_ocram_ecc()
30 pr_err("Unable to map OCRAM ecc regs.\n"); in socfpga_init_ocram_ecc()
34 /* Clear any pending OCRAM ECC interrupts, then enable ECC */ in socfpga_init_ocram_ecc()
58 /* ECC Manager Defines */
89 * This function uses the memory initialization block in the Arria10 ECC
90 * controller to initialize/clear the entire memory data and ECC data.
106 /* Clear any pending ECC interrupts */ in altr_init_memory_port()
125 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-ocram-ecc"); in socfpga_init_arria10_ocram_ecc()
127 pr_err("Unable to find socfpga-a10-ocram-ecc\n"); in socfpga_init_arria10_ocram_ecc()
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| H A D | l2_cache.c | 11 /* A10 System Manager L2 ECC Control register */
19 /* A10 System Manager L2 ECC IRQ Clear register */
28 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc"); in socfpga_init_l2_ecc()
30 pr_err("Unable to find socfpga-l2-ecc in dtb\n"); in socfpga_init_l2_ecc()
37 pr_err("Unable to find L2 ECC mapping in dtb\n"); in socfpga_init_l2_ecc()
41 /* Enable ECC */ in socfpga_init_l2_ecc()
52 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc"); in socfpga_init_arria10_l2_ecc()
54 pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n"); in socfpga_init_arria10_l2_ecc()
61 pr_err("Unable to find L2 ECC mapping in dtb\n"); in socfpga_init_arria10_l2_ecc()
66 pr_err("System Manager not mapped for L2 ECC\n"); in socfpga_init_arria10_l2_ecc()
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| /linux/Documentation/driver-api/ |
| H A D | mtdnand.rst | 357 Hardware ECC support
363 The nand driver supports three different types of hardware ECC.
367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
396 Transfer the ECC from the hardware to the buffer. If the option
402 In case of an ECC error this function is called for error detection
409 Hardware ECC with syndrome calculation
412 Many hardware ECC implementations provide Reed-Solomon codes and
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| /linux/arch/sparc/include/asm/ |
| H A D | chafsr.h | 33 /* Hardware corrected E-cache Tag ECC error */
38 /* SW handled correctable E-cache Tag ECC error */
43 /* Uncorrectable E-cache Tag ECC error */
48 /* Uncorrectable system bus data ECC error due to prefetch
64 * This bit is not set when multiple ECC errors happen within a single
65 * 64-byte system bus transaction. Only the first ECC error in a 16-byte
96 /* HW Corrected system bus MTAG ECC error */
101 /* Uncorrectable system bus MTAG ECC error */
106 /* HW Corrected system bus data ECC error for read of interrupt vector */
111 /* Uncorrectable system bus data ECC error for read of interrupt vector */
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| H A D | estate.h | 6 #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
7 #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
8 #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
9 #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
23 * for uncorrectable ECC errors and system errors.
25 * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
38 /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
39 * reads resulting in a hardware corrected data or MTAG ECC error will generate an
42 * This same trap will also be generated when a hardware corrected ECC error results
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| /linux/fs/ocfs2/ |
| H A D | blockcheck.c | 5 * Checksum and ECC codes for the OCFS2 userspace library.
326 mlog(ML_NOTICE, "ECC recovery count has wrapped\n"); in ocfs2_blockcheck_inc_recover()
338 * ocfs2_block_check structure describing the crc32 and the ecc.
353 u32 ecc; in ocfs2_block_check_compute() local
358 ecc = ocfs2_hamming_encode_block(data, blocksize); in ocfs2_block_check_compute()
361 * No ecc'd ocfs2 structure is larger than 4K, so ecc will be no in ocfs2_block_check_compute()
364 BUG_ON(ecc > USHRT_MAX); in ocfs2_block_check_compute()
367 bc->bc_ecc = cpu_to_le16((u16)ecc); in ocfs2_block_check_compute()
385 u32 crc, ecc; in ocfs2_block_check_validate() local
401 "CRC32 failed: stored: 0x%x, computed 0x%x. Applying ECC.\n", in ocfs2_block_check_validate()
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