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/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 …"PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every … 12 …"BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every c… 15 …"PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cy… 18 …"BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cyc… 21 …"PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts … 24 …"BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts e… 27 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and… 30 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and… 33 …due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there i… 36 …due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there i… [all …]
H A D	branch.json	18 …tor is retired. This event still counts when branch prediction is disabled due to the MMU being of… 21 …tor is retired. This event still counts when branch prediction is disabled due to the MMU being of… 24 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 27 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 30 …due to address mis-compare.This event counts when any indirect branch which can be predicted by th… 33 …due to address mis-compare.This event counts when any indirect branch which can be predicted by th… 36 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 39 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 42 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 45 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… [all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 …"PublicDescription": "No operation issued due to the frontend, cache miss. This event counts every… 24 …"BriefDescription": "No operation issued due to the frontend, cache miss. This event counts every … 27 …"PublicDescription": "No operation issued due to the frontend, TLB miss. This event counts every c… 30 …"BriefDescription": "No operation issued due to the frontend, TLB miss. This event counts every cy… 33 "PublicDescription": "No operation issued due to the frontend, pre-decode error", 36 "BriefDescription": "No operation issued due to the frontend, pre-decode error" 39 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is … 42 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is … 45 …due to the backend, address interlock. This event counts every cycle where the issue of an operati… 48 …due to the backend, address interlock. This event counts every cycle where the issue of an operati… [all …]
H A D	branch.json	18 …ict is retired. This event still counts when branch prediction is disabled due to the Memory Manag… 21 …ict is retired. This event still counts when branch prediction is disabled due to the Memory Manag… 24 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 27 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 30 …due to address miscompare. This event counts when any indirect branch that the BTAC can predict is… 33 …due to address miscompare. This event counts when any indirect branch that the BTAC can predict is… 36 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 39 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 42 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 45 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 6 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 11 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 12 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 17 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", 18 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only dema… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …or's data cache was reloaded from a localtion other than the local core's L2 due to a demand load", 36 …'s data cache was reloaded from a localtion other than the local core's L2 due to either only dema… [all …]
H A D	frontend.json	89 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 90 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 95 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 96 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 101 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction f… 102 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instru… 107 …as reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction f… 108 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either an instru… 113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an… 114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e… [all …]
H A D	marked.json	35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", 65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", 71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", 77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 95 …Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load", [all …]
H A D	other.json	77 …"BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interl… 95 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Tar… 101 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the BHT Direction P… 107 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Targ… 113 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address … 251 "BriefDescription": "Completion stall due to IFU", 257 "BriefDescription": "Completion stall due to CO q full", 263 "BriefDescription": "completion stall due to flush by own thread", 269 "BriefDescription": "Completion stall due to mem ECC delay", 275 "BriefDescription": "Completion stall due to nop", [all …]
H A D	translation.json	29 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 35 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …ry was loaded into the TLB from a localtion other than the local core's L2 due to a data side requ… 53 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side requ… 59 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requ… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side requ… 77 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side requ… 83 … Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side requ… [all …]
H A D	pipeline.json	29 "BriefDescription": "Completion stall due to a Branch Unit", 53 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 54 …"PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict" 59 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 65 "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 66 "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory" 77 "BriefDescription": "Completion stall due to LSU reject ERAT miss", 83 "BriefDescription": "Completion stall due to a long latency fixed point instruction", 89 "BriefDescription": "Completion stall due to FXU", 95 "BriefDescription": "completion stall due to hwsync", [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen3/
H A D	other.json	22 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 28 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 34 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 40 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 58 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 64 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A D	marked.json	20 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requ… 25 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load" 35 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction f… 55 "BriefDescription": "Completion stall due to ntc flush" 60 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data si… 70 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data si… 80 …sor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction f… 85 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe… 95 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data si… 100 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requ… [all …]
H A D	translation.json	15 …che was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load" 25 …nto the TLB from another chip's memory on the same Node or Group (Distant) due to a data side requ… 35 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction si… 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 60 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load" 75 … either shared or modified data from another core's L2/L3 on the same chip due to a instruction si… 80 … was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction f… 95 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load" [all …]
H A D	pipeline.json	30 …ded either shared or modified data from another core's L2/L3 on the same chip due to a marked load" 35 …into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data si… 40 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requ… 80 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data si… 90 …he was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load" 95 …nto the TLB with Modified (M) data from another core's L2 on the same chip due to a data side requ… 115 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data si… 145 …"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from beyond … 150 "BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch" 155 "BriefDescription": "Ict empty for this thread due to Icache Miss" [all …]
H A D	other.json	40 "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue" 45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load" 50 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side requ… 55 …A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Directio… 95 …he processor's Instruction cache was reloaded from the local chip's Memory due to an instruction f… 145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load" 180 "BriefDescription": "Dispatch Hold: Due to TLBIE" 205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load" 225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load" 230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load" [all …]
H A D	frontend.json	5 …nto the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction si… 15 …try was loaded into the TLB from a location other than the local core's L3 due to a instruction si… 50 …s reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load" 55 …The processor's data cache was reloaded from local core's L3 without conflict due to a demand load" 95 …as reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load" 110 "BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)" 115 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction si… 150 …ocessor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load" 155 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load" 170 …oad either shared or modified data from another core's L2/L3 on the same chip due to a marked load" [all …]
H A D	cache.json	15 …"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (divisi… 20 …"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution p… 25 …n cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" 40 … either shared or modified data from another core's L2/L3 on the same chip due to an instruction f… 50 …he was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction f… 55 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f… 70 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data si… 80 …nto the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data si… 85 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 100 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction f…
/freebsd/contrib/ntp/ntpd/
H A D	ntpd-opts.h	172 # warning undefining IPV4 due to option name conflict 176 # warning undefining IPV6 due to option name conflict 180 # warning undefining AUTHREQ due to option name conflict 184 # warning undefining AUTHNOREQ due to option name conflict 188 # warning undefining BCASTSYNC due to option name conflict 192 # warning undefining CONFIGFILE due to option name conflict 196 # warning undefining DEBUG_LEVEL due to option name conflict 200 # warning undefining SET_DEBUG_LEVEL due to option name conflict 204 # warning undefining DRIFTFILE due to option name conflict 208 # warning undefining PANICGATE due t [all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/goldmontplus/
H A D	virtual-memory.json	3 "BriefDescription": "Page walk completed due to a demand load to a 1GB page", 10 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 15 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page", 22 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 27 "BriefDescription": "Page walk completed due to a demand load to a 4K page", 34 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 39 "BriefDescription": "Page walks outstanding due to a demand load every cycle.", 46 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat… 51 "BriefDescription": "Page walk completed due to a demand data store to a 1GB page", 58 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… [all …]
/freebsd/lib/libc/isc/
H A D	ev_timers.c	181 struct timespec due, in evSetTimer() argument 189 "evSetTimer(ctx %p, func %p, uap %p, due %ld.%09ld, inter %ld.%09ld)\n", in evSetTimer() 191 (long)due.tv_sec, due.tv_nsec, in evSetTimer() 198 if (due.tv_nsec >= BILLION) in evSetTimer() 204 if (due.tv_sec < 0 \|\| due.tv_nsec < 0 \|\| due.tv_nsec >= BILLION) in evSetTimer() 211 /* due={0,0} is a magic cookie meaning "now." */ in evSetTimer() 212 if (due.tv_sec == (time_t)0 && due.tv_nsec == 0L) in evSetTimer() 213 due = evNowTime(); in evSetTimer() 219 id->due = due; in evSetTimer() 299 struct timespec due, in evResetTimer() argument [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen2/
H A D	other.json	28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 82 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load… 25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 31 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 43 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 55 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 60 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 67 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
/freebsd/contrib/ntp/util/
H A D	ntp-keygen-opts.h	161 # warning undefining IMBITS due to option name conflict 165 # warning undefining CERTIFICATE due to option name conflict 169 # warning undefining CIPHER due to option name conflict 173 # warning undefining DEBUG_LEVEL due to option name conflict 177 # warning undefining SET_DEBUG_LEVEL due to option name conflict 181 # warning undefining ID_KEY due to option name conflict 185 # warning undefining GQ_PARAMS due to option name conflict 189 # warning undefining HOST_KEY due to option name conflict 193 # warning undefining IFFKEY due to option name conflict 197 # warning undefining IDENT due t [all...]
/freebsd/lib/libpmc/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 14 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to load… 25 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 31 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 36 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 43 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 48 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 55 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 72 …"BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directo… 79 …"PublicDescription": "Counts the number of page walks due to storse that miss the PDE (Page Direct… [all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/icelake/
H A D	memory.json	27 …"BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categor… 38 …"BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as in… 44 …"PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events… 49 …"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., … 55 …"PublicDescription": "Counts the number of times an HLE execution aborted due to various memory ev… 60 …"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions a… 66 …"PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly in… 93 "BriefDescription": "Number of machine clears due to memory ordering conflicts.", 380 …"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 catego… 386 …"PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previ… [all …]

12 3 4 5 6 7 8 9 10 >>...97