Lines Matching full:due
40 "BriefDescription": "Dispatch held due to Issue q full. Includes issue queue and branch queue"
45 …ssor's data cache was reloaded from a location other than the local core's L3 due to a marked load"
50 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side requ…
55 …A Conditional Branch that resolved to taken was mispredicted as not taken (due to the BHT Directio…
95 …he processor's Instruction cache was reloaded from the local chip's Memory due to an instruction f…
145 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a demand load"
180 "BriefDescription": "Dispatch Hold: Due to TLBIE"
205 … to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
225 …cles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load"
230 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load"
255 …r's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load"
320 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load"
350 …s to reload from local core's L3 without dispatch conflicts hit on Mepf state due to a marked load"
375 "BriefDescription": "Completion stall due to cache miss resolving missed the L3"
385 …dified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
425 "BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch"
435 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load"
470 …"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing f…
495 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
510 … into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data si…
565 …from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
585 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Tar…
600 "BriefDescription": "LS0 Erat miss due to prefetch"
630 …ocessor's data cache was reloaded from local core's L3 with dispatch conflict due to a demand load"
640 …n": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load"
660 … or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other th…
695 "BriefDescription": "LS1 Erat miss due to prefetch"
735 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load"
810 … "Duration in cycles to reload from a location other than the local core's L2 due to a marked load"
840 …s reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
845 … or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address colli…
865 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to pattern cache predi…
870 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked …
905 …"BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a m…
910 …cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load"
935 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Targ…
960 "BriefDescription": "L2 I cache demand request due to branch Mispredict ( 15 cycle path)"
965 …"BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an inter…
1015 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1055 …ied data from another core's L2/L3 on a different chip (remote or distant) due to a data side requ…
1060 …ycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load"
1105 …eloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to an instruction f…
1115 …"BriefDescription": "Ict empty for this thread due to dispatch hold on this thread due to Issue q …
1125 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction si…
1160 …All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address colli…
1180 …was reloaded from a memory location including L4 from local remote or distant due to a marked load"
1195 …n": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load"
1200 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load"
1205 …cles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load"
1210 …ied data from another core's L2/L3 on a different chip (remote or distant) due to an instruction f…
1215 …: "TM aborted because a self-induced conflict occurred in Suspended state, due to one of the follo…
1260 …"BriefDescription": "Ict empty for this thread due to dispatch holds because the History Buffer wa…
1305 …e was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load"
1315 …cles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load"
1320 …: "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction si…
1380 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address …
1410 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to reason …
1435 …into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction si…
1485 …eloaded with Modified (M) data from another core's ECO L3 on the same chip due to an instruction f…
1490 "BriefDescription": "CO dispatch failed due to all CO machines being busy"
1495 …The processor's data cache was reloaded from local core's L3 without conflict due to a marked load"
1525 …The processor's data cache was reloaded from local core's L2 without conflict due to a marked load"
1545 … to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load"
1550 …as reloaded with Modified (M) data from another core's L2 on the same chip due to an instruction f…
1560 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction si…
1570 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction si…
1580 …s reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load"
1635 …All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other th…
1665 "BriefDescription": "LS1 Erat miss due to prefetch"
1685 …nto the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction si…
1705 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side requ…
1710 …he was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load"
1815 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction si…
1845 …ssor's data cache was reloaded from a location other than the local core's L2 due to a marked load"
1895 …ed into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side requ…
1900 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1915 … another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
1945 …"BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a m…
1950 …ed into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data si…
1960 … "An ERAT miss was detected after a set-p hit. Erat tracker indicates fail due to tlbmiss and the …
1970 …es to reload from a memory location including L4 from local remote or distant due to a marked load"
2010 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data si…
2035 …try was loaded into the TLB from a location other than the local core's L2 due to a data side requ…
2055 …dified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
2060 … either shared or modified data from another core's L2/L3 on the same chip due to a data side requ…
2115 "BriefDescription": "Completion stall due to cache miss that resolves in local memory"
2180 "BriefDescription": "Prefetch Canceled due to page boundary"
2210 "BriefDescription": "LS0 Erat miss due to prefetch"
2220 …e was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load"
2230 "BriefDescription": "Prefetch Canceled due to icache hit"
2245 …"BriefDescription": "L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 …
2280 "BriefDescription": "Completion stall due to execution units (FXU/VSU/CRU)"
2325 …"BriefDescription": "Fetching is stopped due to an incoming instruction that will result in a flus…
2330 …"BriefDescription": "All D-side store dispatch attempts for this thread that failed due to address…