Home
last modified time | relevance | path

Searched +full:dual +full:- +full:expiration (Results 1 – 8 of 8) sorted by relevance

/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
19 expiration of the timeout interval, a WDT reset is generated.
22 - $ref: watchdog.yaml#
[all …]
/linux/arch/mips/ath25/
H A Dar5312_regs.h64 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
65 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
85 #define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
173 #define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
177 * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
215 * ARM SDRAM Controller -- just enough to determine memory size
/linux/drivers/net/wireless/ti/wlcore/
H A Dacx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
6 * Copyright (C) 2008-2010 Nokia Corporation
19 Host Interrupt Register (WiLink -> Host)
22 /* HW Initiated interrupt Watchdog timer expiration */
40 /* SW FW Initiated interrupt Watchdog timer expiration */
45 /* all possible interrupts - only appropriate ones will be masked in */
119 /* 0 - Always active*/
120 /* 1 - Power down mode: light / fast sleep*/
121 /* 2 - ELP mode: Deep / Max sleep*/
[all …]
/linux/LICENSES/dual/
H A DCDDL-1.01 Valid-License-Identifier: CDDL-1.0
2 SPDX-URL: https://spdx.org/licenses/CDDL-1.0.html
3 Usage-Guide:
4 Do NOT use. The CDDL-1.0 is not GPL2 compatible. It may only be used for
5 dual-licensed files where the other license is GPL2 compatible.
11 SPDX-License-Identifier: ($GPL-COMPATIBLE-ID OR CDDL-1.0)
13 License-Text:
90 hereby grants You a world-wide, royalty-free, non-exclusive
121 hereby grants You a world-wide, royalty-free, non-exclusive
269 NON-INFRINGING. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF
[all …]
H A DMPL-1.11 Valid-License-Identifier: MPL-1.1
2 SPDX-URL: https://spdx.org/licenses/MPL-1.1.html
3 Usage-Guide:
4 Do NOT use. The MPL-1.1 is not GPL2 compatible. It may only be used for
5 dual-licensed files where the other license is GPL2 compatible.
11 SPDX-License-Identifier: MPL-1.1
12 License-Text:
17 ---------------
81 appropriate decompression or de-archiving software is widely available
98 The Initial Developer hereby grants You a world-wide, royalty-free,
[all …]
/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
/linux/drivers/usb/musb/
H A Dtusb6010.c1 // SPDX-License-Identifier: GPL-2.0
3 * TUSB6010 USB 2.0 OTG Dual Role controller
9 * - Driver assumes that interface to external host (main CPU) is
27 #include <linux/dma-mapping.h>
51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
71 rev = musb->tusb_revision; in tusb_print_revision()
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]