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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
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H A Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
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H A Dqcom,mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
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H A Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mds
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H A Dqcom,sm8650-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8650-mdss
24 - description: Display AHB
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H A Dqcom,msm8998-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mds
[all...]
H A Dqcom,sm8150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
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H A Dqcom,sm6350-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
24 - description: Display AHB clock from gcc
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H A Dqcom,sm6375-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6375-mdss
24 - description: Display AHB clock from gcc
[all …]
H A Dqcom,sm6115-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mds
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H A Dqcom,sm7150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
[all …]
H A Dqcom,sm8450-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mds
[all...]
H A Dqcom,sm8250-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mds
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H A Dqcom,sm8550-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mds
[all...]
H A Dqcom,sc7180-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7180-mds
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/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DSI Controller
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12 - Jitao Shi <jitao.shi@mediatek.com>
15 The MediaTek DSI function block is a sink of the display subsystem and can
16 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
H A Dsamsung,mipi-dsim.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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H A Dbrcm,bcm-vc4.txt8 - compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
11 - compatible: Should be one of "brcm,bcm2835-pixelvalve0",
12 "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2"
13 - reg: Physical base address and length of the PV's registers
14 - interrupts: The interrupt number
15 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
18 - compatible: Should be "brcm,bcm2835-hvs"
19 - reg: Physical base address and length of the HVS's registers
20 - interrupts: The interrupt number
21 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
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H A Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
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H A Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/hisilicon/
H A Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
25 clock-names = "pclk";
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/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
5 - #address-cells: Should be <1>.
6 - #size-cells: Should be <0>.
7 - compatible: one of
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
11 "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
12 - reg: Represent the physical address range of the controller.
13 - interrupts: Represent the controller's interrupt to the CPU(s).
[all …]

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