Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8450-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display sf AXI
27 - description: Display core
35 interconnect-names:
39 "^display-controller@[0-9a-f]+$":
45 const: qcom,sm8450-dpu
47 "^displayport-controller@[0-9a-f]+$":
54 - const: qcom,sm8450-dp
55 - const: qcom,sm8350-dp
57 "^dsi@[0-9a-f]+$":
64 - const: qcom,sm8450-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
67 "^phy@[0-9a-f]+$":
73 const: qcom,sm8450-dsi-phy-5nm
76 - compatible
81 - |
82 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
83 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,sm8450.h>
87 #include <dt-bindings/power/qcom,rpmhpd.h>
89 display-subsystem@ae00000 {
90 compatible = "qcom,sm8450-mdss";
92 reg-names = "mdss";
97 interconnect-names = "mdp0-mem",
98 "mdp1-mem",
99 "cpu-cfg";
103 power-domains = <&dispcc MDSS_GDSC>;
109 clock-names = "iface", "bus", "nrt_bus", "core";
112 interrupt-controller;
113 #interrupt-cells = <1>;
117 #address-cells = <1>;
118 #size-cells = <1>;
121 display-controller@ae01000 {
122 compatible = "qcom,sm8450-dpu";
125 reg-names = "mdp", "vbif";
133 clock-names = "bus",
140 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
141 assigned-clock-rates = <19200000>;
143 operating-points-v2 = <&mdp_opp_table>;
144 power-domains = <&rpmhpd RPMHPD_MMCX>;
146 interrupt-parent = <&mdss>;
150 #address-cells = <1>;
151 #size-cells = <0>;
156 remote-endpoint = <&dsi0_in>;
163 remote-endpoint = <&dsi1_in>;
168 mdp_opp_table: opp-table {
169 compatible = "operating-points-v2";
171 opp-172000000{
172 opp-hz = /bits/ 64 <172000000>;
173 required-opps = <&rpmhpd_opp_low_svs_d1>;
176 opp-200000000 {
177 opp-hz = /bits/ 64 <200000000>;
178 required-opps = <&rpmhpd_opp_low_svs>;
181 opp-325000000 {
182 opp-hz = /bits/ 64 <325000000>;
183 required-opps = <&rpmhpd_opp_svs>;
186 opp-375000000 {
187 opp-hz = /bits/ 64 <375000000>;
188 required-opps = <&rpmhpd_opp_svs_l1>;
191 opp-500000000 {
192 opp-hz = /bits/ 64 <500000000>;
193 required-opps = <&rpmhpd_opp_nom>;
198 dsi@ae94000 {
199 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
201 reg-names = "dsi_ctrl";
203 interrupt-parent = <&mdss>;
212 clock-names = "byte",
219 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
221 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
223 operating-points-v2 = <&dsi_opp_table>;
224 power-domains = <&rpmhpd RPMHPD_MMCX>;
227 phy-names = "dsi";
229 #address-cells = <1>;
230 #size-cells = <0>;
233 #address-cells = <1>;
234 #size-cells = <0>;
239 remote-endpoint = <&dpu_intf1_out>;
250 dsi_opp_table: opp-table {
251 compatible = "operating-points-v2";
253 opp-160310000{
254 opp-hz = /bits/ 64 <160310000>;
255 required-opps = <&rpmhpd_opp_low_svs_d1>;
258 opp-187500000 {
259 opp-hz = /bits/ 64 <187500000>;
260 required-opps = <&rpmhpd_opp_low_svs>;
263 opp-300000000 {
264 opp-hz = /bits/ 64 <300000000>;
265 required-opps = <&rpmhpd_opp_svs>;
268 opp-358000000 {
269 opp-hz = /bits/ 64 <358000000>;
270 required-opps = <&rpmhpd_opp_svs_l1>;
276 compatible = "qcom,sm8450-dsi-phy-5nm";
280 reg-names = "dsi_phy",
284 #clock-cells = <1>;
285 #phy-cells = <0>;
289 clock-names = "iface", "ref";
290 vdds-supply = <&vreg_dsi_phy>;
293 dsi@ae96000 {
294 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
296 reg-names = "dsi_ctrl";
298 interrupt-parent = <&mdss>;
307 clock-names = "byte",
314 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
316 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
318 operating-points-v2 = <&dsi_opp_table>;
319 power-domains = <&rpmhpd RPMHPD_MMCX>;
322 phy-names = "dsi";
324 #address-cells = <1>;
325 #size-cells = <0>;
328 #address-cells = <1>;
329 #size-cells = <0>;
334 remote-endpoint = <&dpu_intf2_out>;
347 compatible = "qcom,sm8450-dsi-phy-5nm";
351 reg-names = "dsi_phy",
355 #clock-cells = <1>;
356 #phy-cells = <0>;
360 clock-names = "iface", "ref";
361 vdds-supply = <&vreg_dsi_phy>;