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/linux/drivers/pmdomain/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
100 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
108 #define CPR_INT_MIN BIT(1)
125 #define FUSE_REVISION_UNKNOWN (-1)
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
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/linux/drivers/soc/qcom/
H A Dspm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
175 .pmic_data[1] = 0x00030000,
185 .pmic_data[1] = 0x00030000,
245 .pmic_data[1] = 0x00A4001C,
256 static inline void spm_register_write(struct spm_driver_data *drv, in spm_register_write() argument
259 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
260 writel_relaxed(val, drv->reg_base + in spm_register_write()
261 drv->reg_data->reg_offset[reg]); in spm_register_write()
265 static inline void spm_register_write_sync(struct spm_driver_data *drv, in spm_register_write_sync() argument
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/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-drv.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
8 #include <linux/dma-mapping.h>
13 #include "iwl-drv.h"
14 #include "iwl-csr.h"
15 #include "iwl-debug.h"
16 #include "iwl-trans.h"
17 #include "iwl-op-mode.h"
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/linux/drivers/watchdog/
H A Dmena21_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
42 static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv) in a21_wdt_get_bootstatus() argument
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start() local
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
64 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_stop() local
66 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0); in a21_wdt_stop()
73 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_ping() local
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H A Dmenz69_wdt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for the MEN z069 IP-Core
25 #define MEN_Z069_WDT_COUNTER_MIN 1
36 struct men_z069_drv *drv = watchdog_get_drvdata(wdt); in men_z069_wdt_start() local
39 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
41 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_start()
48 struct men_z069_drv *drv = watchdog_get_drvdata(wdt); in men_z069_wdt_stop() local
51 val = readw(drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
53 writew(val, drv->base + MEN_Z069_WTR); in men_z069_wdt_stop()
60 struct men_z069_drv *drv = watchdog_get_drvdata(wdt); in men_z069_wdt_ping() local
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
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H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
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H A Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
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H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
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H A Dexynos3250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
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H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
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/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
85 #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
114 /* Mode switching SUB Device <-> Host */
116 #define EXYNOS_4x12_MODE_SWITCH_MASK 1
118 #define EXYNOS_4x12_MODE_SWITCH_HOST 1
159 return -EINVAL; in exynos4x12_rate_to_clk()
167 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_isol() local
171 switch (inst->cfg->id) { in exynos4x12_isol()
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H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
50 #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
88 #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
95 #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
115 #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
126 #define EXYNOS_5250_MODE_SWITCH_MASK 1
128 #define EXYNOS_5250_MODE_SWITCH_HOST 1
168 return -EINVAL; in exynos5250_rate_to_clk()
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/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
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H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
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H A Dexynos7885-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Exynos7885 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 etc0: etc0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
20 interrupt-controller;
21 #interrupt-cells = <2>;
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/linux/drivers/phy/renesas/
H A Dphy-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2 PHY driver
56 struct rcar_gen2_phy_driver *drv; member
79 struct rcar_gen2_channel *channel = phy->channel; in rcar_gen2_phy_init()
80 struct rcar_gen2_phy_driver *drv = channel->drv; in rcar_gen2_phy_init() local
88 * driver. Achieving this with cmpxcgh() should be SMP-safe. in rcar_gen2_phy_init()
90 if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1) in rcar_gen2_phy_init()
91 return -EBUSY; in rcar_gen2_phy_init()
93 clk_prepare_enable(drv->clk); in rcar_gen2_phy_init()
95 spin_lock_irqsave(&drv->lock, flags); in rcar_gen2_phy_init()
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
19 The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity
22 be written to from Linux. The structure of each DRV follows the same template
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
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/linux/sound/soc/intel/atom/
H A Dsst-atom-controls.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sst-atom-controls.c - Intel MID Platform driver DPCM ALSA controls for Mrfld
5 * Copyright (C) 2013-14 Intel Corp
20 #include "sst-mfld-platform.h"
21 #include "sst-atom-controls.h"
23 static int sst_fill_byte_control(struct sst_data *drv, in sst_fill_byte_control() argument
28 struct snd_sst_bytes_v2 *byte_data = drv->byte_stream; in sst_fill_byte_control()
30 byte_data->type = SST_CMD_BYTES_SET; in sst_fill_byte_control()
31 byte_data->ipc_msg = ipc_msg; in sst_fill_byte_control()
32 byte_data->block = block; in sst_fill_byte_control()
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/linux/drivers/edac/
H A Dqcom_edac.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/soc/qcom/llcc-qcom.h>
19 #define LLCC_ERP_PANIC_ON_UE 1
37 #define DB_ECC_ERROR BIT(1)
39 #define DRP_TRP_INT_CLEAR GENMASK(1, 0)
40 #define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
60 .name = "DRAM Single-bit",
67 .name = "DRAM Double-bit",
74 .name = "TRAM Single-bit",
81 .name = "TRAM Double-bit",
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/linux/drivers/media/pci/cx88/
H A Dcx88-mpeg.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/dma-mapping.h>
22 /* ------------------------------------------------------------------ */
36 if (debug + 1 > level) \
47 if (dev->core->board.mpeg & CX88_MPEG_DVB) in request_module_async()
48 request_module("cx88-dvb"); in request_module_async()
49 if (dev->core->board.mpeg & CX88_MPEG_BLACKBIRD) in request_module_async()
50 request_module("cx88-blackbird"); in request_module_async()
55 INIT_WORK(&dev->request_module_wk, request_module_async); in request_modules()
56 schedule_work(&dev->request_module_wk); in request_modules()
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