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/linux/drivers/pmdomain/qcom/
H A Dcpr.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
100 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
108 #define CPR_INT_MIN BIT(1)
125 #define FUSE_REVISION_UNKNOWN (-1)
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
[all …]
/linux/drivers/soc/qcom/
H A Dspm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
175 .pmic_data[1] = 0x00030000,
185 .pmic_data[1] = 0x00030000,
245 .pmic_data[1] = 0x00A4001C,
256 static inline void spm_register_write(struct spm_driver_data *drv, in spm_register_write() argument
259 if (drv->reg_data->reg_offset[reg]) in spm_register_write()
260 writel_relaxed(val, drv->reg_base + in spm_register_write()
261 drv->reg_data->reg_offset[reg]); in spm_register_write()
265 static inline void spm_register_write_sync(struct spm_driver_data *drv, in spm_register_write_sync() argument
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/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
63 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_enable() local
67 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 1); in hns_gmac_enable()
71 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 0); in hns_gmac_enable()
72 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 1); in hns_gmac_enable()
78 struct mac_driver *drv = (struct mac_driver *)mac_drv; in hns_gmac_disable() local
82 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_TX_EN_B, 0); in hns_gmac_disable()
86 dsaf_set_dev_bit(drv, GMAC_PCS_RX_EN_REG, 0, 1); in hns_gmac_disable()
87 dsaf_set_dev_bit(drv, GMAC_PORT_EN_REG, GMAC_PORT_RX_EN_B, 0); in hns_gmac_disable()
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H A Dhns_dsaf_xgmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2014-2015 Hisilicon Limited.
6 #include <linux/io-64-nonatomic-hi-lo.h>
87 *hns_xgmac_tx_enable - xgmac port tx enable
88 *@drv: mac driver
91 static void hns_xgmac_tx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_tx_enable() argument
93 dsaf_set_dev_bit(drv, XGMAC_MAC_ENABLE_REG, XGMAC_ENABLE_TX_B, !!value); in hns_xgmac_tx_enable()
97 *hns_xgmac_rx_enable - xgmac port rx enable
98 *@drv: mac driver
101 static void hns_xgmac_rx_enable(struct mac_driver *drv, u32 value) in hns_xgmac_rx_enable() argument
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/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-drv.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
8 #include <linux/dma-mapping.h>
13 #include "iwl-drv.h"
14 #include "iwl-csr.h"
15 #include "iwl-debug.h"
16 #include "iwl-trans.h"
17 #include "iwl-op-mode.h"
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/linux/drivers/watchdog/
H A Dmena21_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
42 static unsigned int a21_wdt_get_bootstatus(struct a21_wdt_drv *drv) in a21_wdt_get_bootstatus() argument
46 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST0]) ? (1 << 0) : 0; in a21_wdt_get_bootstatus()
47 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST1]) ? (1 << 1) : 0; in a21_wdt_get_bootstatus()
48 reset |= gpiod_get_value(drv->gpios[GPIO_WD_RST2]) ? (1 << 2) : 0; in a21_wdt_get_bootstatus()
55 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_start() local
57 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 1); in a21_wdt_start()
64 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_stop() local
66 gpiod_set_value(drv->gpios[GPIO_WD_ENAB], 0); in a21_wdt_stop()
73 struct a21_wdt_drv *drv = watchdog_get_drvdata(wdt); in a21_wdt_ping() local
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/linux/arch/arm/boot/dts/samsung/
H A Dexynos4x12-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
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H A Dexynos5250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5250 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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H A Ds5pv210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
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H A Dexynos4210-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
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H A Dexynos5420-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpy7: gpy7-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpx0: gpx0-gpio-bank {
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H A Dexynos3250-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos3250 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS4_PIN_DRV_ ##_drv>; \
23 pin- ## _pin { \
25 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
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H A Dexynos5260-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
23 gpa1: gpa1-gpio-bank {
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/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
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/linux/drivers/phy/samsung/
H A Dphy-exynos4x12-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
13 #include "phy-samsung-usb2.h"
85 #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
114 /* Mode switching SUB Device <-> Host */
116 #define EXYNOS_4x12_MODE_SWITCH_MASK 1
118 #define EXYNOS_4x12_MODE_SWITCH_HOST 1
159 return -EINVAL; in exynos4x12_rate_to_clk()
167 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos4x12_isol() local
171 switch (inst->cfg->id) { in exynos4x12_isol()
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H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
50 #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
88 #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
95 #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
115 #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
126 #define EXYNOS_5250_MODE_SWITCH_MASK 1
128 #define EXYNOS_5250_MODE_SWITCH_HOST 1
168 return -EINVAL; in exynos5250_rate_to_clk()
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/linux/drivers/cpuidle/
H A Ddriver.c2 * driver.c - driver support
4 * (C) 2006-2007 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
30 * __cpuidle_get_cpu_driver - return the cpuidle driver tied to a CPU.
42 * __cpuidle_unset_driver - unset per CPU driver variables.
43 * @drv: a valid pointer to a struct cpuidle_driver
46 * variable. If @drv is different from the registered driver, the corresponding
49 static inline void __cpuidle_unset_driver(struct cpuidle_driver *drv) in __cpuidle_unset_driver() argument
53 for_each_cpu(cpu, drv->cpumask) { in __cpuidle_unset_driver()
55 if (drv != __cpuidle_get_cpu_driver(cpu)) in __cpuidle_unset_driver()
63 * __cpuidle_set_driver - set per CPU driver variables for the given driver.
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H A Dcpuidle-psci.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "cpuidle-psci.h"
54 struct cpuidle_driver *drv, int idx, in __psci_enter_domain_idle_state() argument
58 u32 *states = data->psci_states; in __psci_enter_domain_idle_state()
59 struct device *pd_dev = data->dev; in __psci_enter_domain_idle_state()
65 return -1; in __psci_enter_domain_idle_state()
77 ret = psci_cpu_suspend_enter(state) ? -1 : idx; in __psci_enter_domain_idle_state()
92 struct cpuidle_driver *drv, int idx) in psci_enter_domain_idle_state() argument
94 return __psci_enter_domain_idle_state(dev, drv, idx, false); in psci_enter_domain_idle_state()
98 struct cpuidle_driver *drv, in psci_enter_s2idle_domain_idle_state() argument
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H A Dcpuidle.c2 * cpuidle.c - core cpuidle infrastructure
4 * (C) 2006-2007 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
11 #include "linux/percpu-defs.h"
49 off = 1; in disable_cpuidle()
52 bool cpuidle_not_available(struct cpuidle_driver *drv, in cpuidle_not_available() argument
55 return off || !initialized || !drv || !dev || !dev->enabled; in cpuidle_not_available()
59 * cpuidle_play_dead - cpu off-lining
66 struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev); in cpuidle_play_dead() local
69 if (!drv) in cpuidle_play_dead()
70 return -ENODEV; in cpuidle_play_dead()
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/linux/drivers/media/radio/
H A Dradio-isa.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <media/v4l2-device.h>
18 #include <media/v4l2-ioctl.h>
19 #include <media/v4l2-fh.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-event.h>
23 #include "radio-isa.h"
37 strscpy(v->driver, isa->drv->driver.driver.name, sizeof(v->driver)); in radio_isa_querycap()
38 strscpy(v->card, isa->drv->card, sizeof(v->card)); in radio_isa_querycap()
39 snprintf(v->bus_info, sizeof(v->bus_info), "ISA:%s", dev_name(isa->v4l2_dev.dev)); in radio_isa_querycap()
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/linux/drivers/phy/renesas/
H A Dphy-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2 PHY driver
56 struct rcar_gen2_phy_driver *drv; member
79 struct rcar_gen2_channel *channel = phy->channel; in rcar_gen2_phy_init()
80 struct rcar_gen2_phy_driver *drv = channel->drv; in rcar_gen2_phy_init() local
88 * driver. Achieving this with cmpxcgh() should be SMP-safe. in rcar_gen2_phy_init()
90 if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1) in rcar_gen2_phy_init()
91 return -EBUSY; in rcar_gen2_phy_init()
93 clk_prepare_enable(drv->clk); in rcar_gen2_phy_init()
95 spin_lock_irqsave(&drv->lock, flags); in rcar_gen2_phy_init()
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/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
32 gpa0: gpa0-gpio-bank {
33 gpio-controller;
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H A Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include "exynos-pinctrl.h"
15 gpa0: gpa0-gpio-bank {
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
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/linux/drivers/cpufreq/
H A Dqcom-cpufreq-nvmem.c1 // SPDX-License-Identifier: GPL-2.0
10 * defines the voltage and frequency value based on the msm-id in SMEM
12 * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
15 * operating-points-v2 table when it is parsed by the OPP framework.
23 #include <linux/nvmem-consumer.h>
33 #include <dt-bindings/arm/qcom,ids.h>
54 struct qcom_cpufreq_drv *drv);
74 struct qcom_cpufreq_drv *drv) in qcom_cpufreq_simple_get_version() argument
84 drv->versions = 1 << *speedbin; in qcom_cpufreq_simple_get_version()
132 case 1: in get_krait_bin_format_b()
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