Lines Matching +full:drv +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
27 #include <linux/nvmem-consumer.h>
29 /* Register Offsets for RB-CPR and Bit Definitions */
100 #define RBCPR_RESULT0_STEP_UP_SHIFT 1
108 #define CPR_INT_MIN BIT(1)
125 #define FUSE_REVISION_UNKNOWN (-1)
252 static bool cpr_is_allowed(struct cpr_drv *drv) in cpr_is_allowed() argument
254 return !drv->loop_disabled; in cpr_is_allowed()
257 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value) in cpr_write() argument
259 writel_relaxed(value, drv->base + offset); in cpr_write()
262 static u32 cpr_read(struct cpr_drv *drv, u32 offset) in cpr_read() argument
264 return readl_relaxed(drv->base + offset); in cpr_read()
268 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value) in cpr_masked_write() argument
272 val = readl_relaxed(drv->base + offset); in cpr_masked_write()
275 writel_relaxed(val, drv->base + offset); in cpr_masked_write()
278 static void cpr_irq_clr(struct cpr_drv *drv) in cpr_irq_clr() argument
280 cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL); in cpr_irq_clr()
283 static void cpr_irq_clr_nack(struct cpr_drv *drv) in cpr_irq_clr_nack() argument
285 cpr_irq_clr(drv); in cpr_irq_clr_nack()
286 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_irq_clr_nack()
289 static void cpr_irq_clr_ack(struct cpr_drv *drv) in cpr_irq_clr_ack() argument
291 cpr_irq_clr(drv); in cpr_irq_clr_ack()
292 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_irq_clr_ack()
295 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits) in cpr_irq_set() argument
297 cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits); in cpr_irq_set()
300 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value) in cpr_ctl_modify() argument
302 cpr_masked_write(drv, REG_RBCPR_CTL, mask, value); in cpr_ctl_modify()
305 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner) in cpr_ctl_enable() argument
308 const struct cpr_desc *desc = drv->desc; in cpr_ctl_enable()
311 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; in cpr_ctl_enable()
312 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; in cpr_ctl_enable()
314 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val); in cpr_ctl_enable()
315 cpr_masked_write(drv, REG_RBCPR_CTL, in cpr_ctl_enable()
318 corner->save_ctl); in cpr_ctl_enable()
319 cpr_irq_set(drv, corner->save_irq); in cpr_ctl_enable()
321 if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV) in cpr_ctl_enable()
325 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val); in cpr_ctl_enable()
328 static void cpr_ctl_disable(struct cpr_drv *drv) in cpr_ctl_disable() argument
330 cpr_irq_set(drv, 0); in cpr_ctl_disable()
331 cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN | in cpr_ctl_disable()
333 cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, in cpr_ctl_disable()
336 cpr_irq_clr(drv); in cpr_ctl_disable()
337 cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1); in cpr_ctl_disable()
338 cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1); in cpr_ctl_disable()
339 cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0); in cpr_ctl_disable()
342 static bool cpr_ctl_is_enabled(struct cpr_drv *drv) in cpr_ctl_is_enabled() argument
346 reg_val = cpr_read(drv, REG_RBCPR_CTL); in cpr_ctl_is_enabled()
350 static bool cpr_ctl_is_busy(struct cpr_drv *drv) in cpr_ctl_is_busy() argument
354 reg_val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_ctl_is_busy()
358 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner) in cpr_corner_save() argument
360 corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_corner_save()
361 corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0)); in cpr_corner_save()
364 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner) in cpr_corner_restore() argument
367 struct fuse_corner *fuse = corner->fuse_corner; in cpr_corner_restore()
368 const struct cpr_desc *desc = drv->desc; in cpr_corner_restore()
371 ro_sel = fuse->ring_osc_idx; in cpr_corner_restore()
372 gcnt = drv->gcnt; in cpr_corner_restore()
373 gcnt |= fuse->quot - corner->quot_adjust; in cpr_corner_restore()
376 step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT; in cpr_corner_restore()
377 step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK; in cpr_corner_restore()
378 cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot); in cpr_corner_restore()
382 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_corner_restore()
384 cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt); in cpr_corner_restore()
385 ctl = corner->save_ctl; in cpr_corner_restore()
386 cpr_write(drv, REG_RBCPR_CTL, ctl); in cpr_corner_restore()
387 irq = corner->save_irq; in cpr_corner_restore()
388 cpr_irq_set(drv, irq); in cpr_corner_restore()
389 dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt, in cpr_corner_restore()
400 for (f += 1; f <= end; f++) in cpr_set_acc()
401 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
403 for (f -= 1; f >= end; f--) in cpr_set_acc()
404 regmap_multi_reg_write(tcsr, f->accs, f->num_accs); in cpr_set_acc()
408 static int cpr_pre_voltage(struct cpr_drv *drv, in cpr_pre_voltage() argument
412 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_pre_voltage()
414 if (drv->tcsr && dir == DOWN) in cpr_pre_voltage()
415 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_pre_voltage()
420 static int cpr_post_voltage(struct cpr_drv *drv, in cpr_post_voltage() argument
424 struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner; in cpr_post_voltage()
426 if (drv->tcsr && dir == UP) in cpr_post_voltage()
427 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner); in cpr_post_voltage()
432 static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner, in cpr_scale_voltage() argument
436 struct fuse_corner *fuse_corner = corner->fuse_corner; in cpr_scale_voltage()
438 ret = cpr_pre_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
442 ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV); in cpr_scale_voltage()
444 dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n", in cpr_scale_voltage()
449 ret = cpr_post_voltage(drv, fuse_corner, dir); in cpr_scale_voltage()
456 static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv) in cpr_get_cur_perf_state() argument
458 return drv->corner ? drv->corner - drv->corners + 1 : 0; in cpr_get_cur_perf_state()
461 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir) in cpr_scale() argument
466 const struct cpr_desc *desc = drv->desc; in cpr_scale()
471 step_uV = regulator_get_linear_step(drv->vdd_apc); in cpr_scale()
473 return -EINVAL; in cpr_scale()
475 corner = drv->corner; in cpr_scale()
477 val = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_scale()
481 last_uV = corner->last_uV; in cpr_scale()
484 if (desc->clamp_timer_interval && in cpr_scale()
485 error_steps < desc->up_threshold) { in cpr_scale()
491 error_steps = max(desc->up_threshold, in cpr_scale()
492 desc->vdd_apc_step_up_limit); in cpr_scale()
495 if (last_uV >= corner->max_uV) { in cpr_scale()
496 cpr_irq_clr_nack(drv); in cpr_scale()
502 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
505 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP); in cpr_scale()
510 if (error_steps > desc->vdd_apc_step_up_limit) in cpr_scale()
511 error_steps = desc->vdd_apc_step_up_limit; in cpr_scale()
515 new_uV = min(new_uV, corner->max_uV); in cpr_scale()
517 dev_dbg(drv->dev, in cpr_scale()
518 "UP: -> new_uV: %d last_uV: %d perf state: %u\n", in cpr_scale()
519 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
521 if (desc->clamp_timer_interval && in cpr_scale()
522 error_steps < desc->down_threshold) { in cpr_scale()
528 error_steps = max(desc->down_threshold, in cpr_scale()
529 desc->vdd_apc_step_down_limit); in cpr_scale()
532 if (last_uV <= corner->min_uV) { in cpr_scale()
533 cpr_irq_clr_nack(drv); in cpr_scale()
539 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
542 cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN); in cpr_scale()
547 if (error_steps > desc->vdd_apc_step_down_limit) in cpr_scale()
548 error_steps = desc->vdd_apc_step_down_limit; in cpr_scale()
551 new_uV = last_uV - error_steps * step_uV; in cpr_scale()
552 new_uV = max(new_uV, corner->min_uV); in cpr_scale()
554 dev_dbg(drv->dev, in cpr_scale()
555 "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n", in cpr_scale()
556 new_uV, last_uV, cpr_get_cur_perf_state(drv)); in cpr_scale()
559 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_scale()
561 cpr_irq_clr_nack(drv); in cpr_scale()
564 drv->corner->last_uV = new_uV; in cpr_scale()
574 val = desc->up_threshold; in cpr_scale()
578 cpr_ctl_modify(drv, reg_mask, val); in cpr_scale()
580 /* Re-enable default interrupts */ in cpr_scale()
581 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_scale()
584 cpr_irq_clr_ack(drv); in cpr_scale()
591 struct cpr_drv *drv = dev; in cpr_irq_handler() local
592 const struct cpr_desc *desc = drv->desc; in cpr_irq_handler()
596 mutex_lock(&drv->lock); in cpr_irq_handler()
598 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
599 if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS) in cpr_irq_handler()
600 val = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_irq_handler()
602 dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val); in cpr_irq_handler()
604 if (!cpr_ctl_is_enabled(drv)) { in cpr_irq_handler()
605 dev_dbg(drv->dev, "CPR is disabled\n"); in cpr_irq_handler()
607 } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) { in cpr_irq_handler()
608 dev_dbg(drv->dev, "CPR measurement is not ready\n"); in cpr_irq_handler()
609 } else if (!cpr_is_allowed(drv)) { in cpr_irq_handler()
610 val = cpr_read(drv, REG_RBCPR_CTL); in cpr_irq_handler()
611 dev_err_ratelimited(drv->dev, in cpr_irq_handler()
621 cpr_scale(drv, UP); in cpr_irq_handler()
623 cpr_scale(drv, DOWN); in cpr_irq_handler()
625 cpr_irq_clr_nack(drv); in cpr_irq_handler()
627 cpr_irq_clr_nack(drv); in cpr_irq_handler()
630 dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n"); in cpr_irq_handler()
632 dev_dbg(drv->dev, in cpr_irq_handler()
637 cpr_corner_save(drv, drv->corner); in cpr_irq_handler()
640 mutex_unlock(&drv->lock); in cpr_irq_handler()
645 static int cpr_enable(struct cpr_drv *drv) in cpr_enable() argument
649 ret = regulator_enable(drv->vdd_apc); in cpr_enable()
653 mutex_lock(&drv->lock); in cpr_enable()
655 if (cpr_is_allowed(drv) && drv->corner) { in cpr_enable()
656 cpr_irq_clr(drv); in cpr_enable()
657 cpr_corner_restore(drv, drv->corner); in cpr_enable()
658 cpr_ctl_enable(drv, drv->corner); in cpr_enable()
661 mutex_unlock(&drv->lock); in cpr_enable()
666 static int cpr_disable(struct cpr_drv *drv) in cpr_disable() argument
668 mutex_lock(&drv->lock); in cpr_disable()
670 if (cpr_is_allowed(drv)) { in cpr_disable()
671 cpr_ctl_disable(drv); in cpr_disable()
672 cpr_irq_clr(drv); in cpr_disable()
675 mutex_unlock(&drv->lock); in cpr_disable()
677 return regulator_disable(drv->vdd_apc); in cpr_disable()
680 static int cpr_config(struct cpr_drv *drv) in cpr_config() argument
685 const struct cpr_desc *desc = drv->desc; in cpr_config()
688 cpr_write(drv, REG_RBIF_IRQ_EN(0), 0); in cpr_config()
689 cpr_write(drv, REG_RBCPR_CTL, 0); in cpr_config()
695 cpr_write(drv, REG_RBIF_LIMIT, val); in cpr_config()
696 cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT); in cpr_config()
703 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0); in cpr_config()
706 gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000; in cpr_config()
709 drv->gcnt = gcnt; in cpr_config()
712 val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000; in cpr_config()
713 cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val); in cpr_config()
714 dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val, in cpr_config()
715 desc->timer_delay_us); in cpr_config()
718 val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT; in cpr_config()
719 val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT; in cpr_config()
720 val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT; in cpr_config()
721 cpr_write(drv, REG_RBIF_TIMER_ADJUST, val); in cpr_config()
724 val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT; in cpr_config()
725 val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT; in cpr_config()
728 cpr_write(drv, REG_RBCPR_CTL, val); in cpr_config()
730 for (i = 0; i < drv->num_corners; i++) { in cpr_config()
731 corner = &drv->corners[i]; in cpr_config()
732 corner->save_ctl = val; in cpr_config()
733 corner->save_irq = CPR_INT_DEFAULT; in cpr_config()
736 cpr_irq_set(drv, CPR_INT_DEFAULT); in cpr_config()
738 val = cpr_read(drv, REG_RBCPR_VERSION); in cpr_config()
740 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS; in cpr_config()
748 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_set_performance_state() local
753 guard(mutex)(&drv->lock); in cpr_set_performance_state()
755 dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n", in cpr_set_performance_state()
756 __func__, state, cpr_get_cur_perf_state(drv)); in cpr_set_performance_state()
760 * Remove one since lowest performance state is 1. in cpr_set_performance_state()
762 corner = drv->corners + state - 1; in cpr_set_performance_state()
763 end = &drv->corners[drv->num_corners - 1]; in cpr_set_performance_state()
764 if (corner > end || corner < drv->corners) in cpr_set_performance_state()
765 return -EINVAL; in cpr_set_performance_state()
768 if (drv->corner > corner) in cpr_set_performance_state()
770 else if (drv->corner < corner) in cpr_set_performance_state()
775 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
776 new_uV = corner->last_uV; in cpr_set_performance_state()
778 new_uV = corner->uV; in cpr_set_performance_state()
780 if (cpr_is_allowed(drv)) in cpr_set_performance_state()
781 cpr_ctl_disable(drv); in cpr_set_performance_state()
783 ret = cpr_scale_voltage(drv, corner, new_uV, dir); in cpr_set_performance_state()
787 if (cpr_is_allowed(drv)) { in cpr_set_performance_state()
788 cpr_irq_clr(drv); in cpr_set_performance_state()
789 if (drv->corner != corner) in cpr_set_performance_state()
790 cpr_corner_restore(drv, corner); in cpr_set_performance_state()
791 cpr_ctl_enable(drv, corner); in cpr_set_performance_state()
794 drv->corner = corner; in cpr_set_performance_state()
800 cpr_populate_ring_osc_idx(struct cpr_drv *drv) in cpr_populate_ring_osc_idx() argument
802 struct fuse_corner *fuse = drv->fuse_corners; in cpr_populate_ring_osc_idx()
803 struct fuse_corner *end = fuse + drv->desc->num_fuse_corners; in cpr_populate_ring_osc_idx()
804 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx()
809 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); in cpr_populate_ring_osc_idx()
812 fuse->ring_osc_idx = data; in cpr_populate_ring_osc_idx()
822 struct cpr_drv *drv) in cpr_read_fuse_uV() argument
828 ret = nvmem_cell_read_variable_le_u32(drv->dev, init_v_efuse, &bits); in cpr_read_fuse_uV()
832 steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1); in cpr_read_fuse_uV()
834 if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1)) in cpr_read_fuse_uV()
835 steps = -steps; in cpr_read_fuse_uV()
837 step_size_uV = desc->cpr_fuses.init_voltage_step; in cpr_read_fuse_uV()
839 uV = fdata->ref_uV + steps * step_size_uV; in cpr_read_fuse_uV()
843 static int cpr_fuse_corner_init(struct cpr_drv *drv) in cpr_fuse_corner_init() argument
845 const struct cpr_desc *desc = drv->desc; in cpr_fuse_corner_init()
846 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init()
847 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_fuse_corner_init()
856 accs = acc_desc->settings; in cpr_fuse_corner_init()
858 step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_fuse_corner_init()
860 return -EINVAL; in cpr_fuse_corner_init()
863 fuse = drv->fuse_corners; in cpr_fuse_corner_init()
864 end = &fuse[desc->num_fuse_corners - 1]; in cpr_fuse_corner_init()
865 fdata = desc->cpr_fuses.fuse_corner_data; in cpr_fuse_corner_init()
873 fdata->min_uV = roundup(fdata->min_uV, step_volt); in cpr_fuse_corner_init()
874 fdata->max_uV = roundup(fdata->max_uV, step_volt); in cpr_fuse_corner_init()
877 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage, in cpr_fuse_corner_init()
878 step_volt, drv); in cpr_fuse_corner_init()
882 fuse->min_uV = fdata->min_uV; in cpr_fuse_corner_init()
883 fuse->max_uV = fdata->max_uV; in cpr_fuse_corner_init()
884 fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV); in cpr_fuse_corner_init()
893 end->max_uV = max(end->max_uV, end->uV); in cpr_fuse_corner_init()
897 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); in cpr_fuse_corner_init()
901 fuse->quot *= fdata->quot_scale; in cpr_fuse_corner_init()
902 fuse->quot += fdata->quot_offset; in cpr_fuse_corner_init()
903 fuse->quot += fdata->quot_adjust; in cpr_fuse_corner_init()
904 fuse->step_quot = desc->step_quot[fuse->ring_osc_idx]; in cpr_fuse_corner_init()
907 fuse->accs = accs; in cpr_fuse_corner_init()
908 fuse->num_accs = acc_desc->num_regs_per_fuse; in cpr_fuse_corner_init()
909 accs += acc_desc->num_regs_per_fuse; in cpr_fuse_corner_init()
916 for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) { in cpr_fuse_corner_init()
917 if (fuse->uV > fuse->max_uV) in cpr_fuse_corner_init()
918 fuse->uV = fuse->max_uV; in cpr_fuse_corner_init()
919 else if (fuse->uV < fuse->min_uV) in cpr_fuse_corner_init()
920 fuse->uV = fuse->min_uV; in cpr_fuse_corner_init()
922 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
923 fuse->min_uV, in cpr_fuse_corner_init()
924 fuse->min_uV); in cpr_fuse_corner_init()
926 dev_err(drv->dev, in cpr_fuse_corner_init()
928 fuse->min_uV, i); in cpr_fuse_corner_init()
929 return -EINVAL; in cpr_fuse_corner_init()
932 ret = regulator_is_supported_voltage(drv->vdd_apc, in cpr_fuse_corner_init()
933 fuse->max_uV, in cpr_fuse_corner_init()
934 fuse->max_uV); in cpr_fuse_corner_init()
936 dev_err(drv->dev, in cpr_fuse_corner_init()
938 fuse->max_uV, i); in cpr_fuse_corner_init()
939 return -EINVAL; in cpr_fuse_corner_init()
942 dev_dbg(drv->dev, in cpr_fuse_corner_init()
944 i, fuse->min_uV, fuse->uV, fuse->max_uV, in cpr_fuse_corner_init()
945 fuse->ring_osc_idx, fuse->quot, fuse->step_quot); in cpr_fuse_corner_init()
952 struct cpr_drv *drv, in cpr_calculate_scaling() argument
962 fuse = corner->fuse_corner; in cpr_calculate_scaling()
963 prev_fuse = fuse - 1; in cpr_calculate_scaling()
966 ret = nvmem_cell_read_variable_le_u32(drv->dev, quot_offset, "_diff); in cpr_calculate_scaling()
970 quot_diff *= fdata->quot_offset_scale; in cpr_calculate_scaling()
971 quot_diff += fdata->quot_offset_adjust; in cpr_calculate_scaling()
973 quot_diff = fuse->quot - prev_fuse->quot; in cpr_calculate_scaling()
976 freq_diff = fuse->max_freq - prev_fuse->max_freq; in cpr_calculate_scaling()
979 return min(scaling, fdata->max_quot_scale); in cpr_calculate_scaling()
990 fuse = corner->fuse_corner; in cpr_interpolate()
991 prev_fuse = fuse - 1; in cpr_interpolate()
993 f_high = fuse->max_freq; in cpr_interpolate()
994 f_low = prev_fuse->max_freq; in cpr_interpolate()
995 uV_high = fuse->uV; in cpr_interpolate()
996 uV_low = prev_fuse->uV; in cpr_interpolate()
997 f_diff = fuse->max_freq - corner->freq; in cpr_interpolate()
1004 if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq) in cpr_interpolate()
1005 return corner->uV; in cpr_interpolate()
1007 temp = f_diff * (uV_high - uV_low); in cpr_interpolate()
1008 temp = div64_ul(temp, f_high - f_low); in cpr_interpolate()
1014 temp_limit = f_diff * fdata->max_volt_scale; in cpr_interpolate()
1017 uV = uV_high - min(temp, temp_limit); in cpr_interpolate()
1027 if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner)) in cpr_get_fuse_corner()
1028 pr_err("%s: missing 'qcom,opp-fuse-level' property\n", in cpr_get_fuse_corner()
1052 of_parse_phandle(child_np, "required-opps", 0); in cpr_get_opp_hz_for_req()
1057 of_property_read_u64(child_np, "opp-hz", &rate); in cpr_get_opp_hz_for_req()
1065 static int cpr_corner_init(struct cpr_drv *drv) in cpr_corner_init() argument
1067 const struct cpr_desc *desc = drv->desc; in cpr_corner_init()
1068 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_corner_init()
1079 int step_volt = regulator_get_linear_step(drv->vdd_apc); in cpr_corner_init()
1083 return -EINVAL; in cpr_corner_init()
1085 corner = drv->corners; in cpr_corner_init()
1086 end = &corner[drv->num_corners - 1]; in cpr_corner_init()
1088 cdata = devm_kcalloc(drv->dev, drv->num_corners, in cpr_corner_init()
1092 return -ENOMEM; in cpr_corner_init()
1098 for (level = 1; level <= drv->num_corners; level++) { in cpr_corner_init()
1099 opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level); in cpr_corner_init()
1101 return -EINVAL; in cpr_corner_init()
1105 return -EINVAL; in cpr_corner_init()
1107 fnum = fc - 1; in cpr_corner_init()
1108 freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev); in cpr_corner_init()
1111 return -EINVAL; in cpr_corner_init()
1113 cdata[level - 1].fuse_corner = fnum; in cpr_corner_init()
1114 cdata[level - 1].freq = freq; in cpr_corner_init()
1116 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1117 dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n", in cpr_corner_init()
1118 freq, dev_pm_opp_get_level(opp) - 1, fnum); in cpr_corner_init()
1119 if (freq > fuse->max_freq) in cpr_corner_init()
1120 fuse->max_freq = freq; in cpr_corner_init()
1127 * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1)) in cpr_corner_init()
1128 * / (freq(corner_N) - freq(corner_N-1)), max_factor) in cpr_corner_init()
1131 * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1) in cpr_corner_init()
1133 * freq(corner_N-1): max frequency in MHz supported by fuse corner in cpr_corner_init()
1134 * (N - 1) in cpr_corner_init()
1140 * quot_adjust = (freq_max - freq_corner) * scaling / 1000 in cpr_corner_init()
1155 * +--------------- +---------------- in cpr_corner_init()
1156 * 0 1 2 3 4 5 6 0 1 2 3 4 5 6 in cpr_corner_init()
1165 fdata = &desc->cpr_fuses.fuse_corner_data[fnum]; in cpr_corner_init()
1167 fuse = &drv->fuse_corners[fnum]; in cpr_corner_init()
1169 prev_fuse = &drv->fuse_corners[fnum - 1]; in cpr_corner_init()
1173 corner->fuse_corner = fuse; in cpr_corner_init()
1174 corner->freq = cdata[i].freq; in cpr_corner_init()
1175 corner->uV = fuse->uV; in cpr_corner_init()
1177 if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) { in cpr_corner_init()
1178 scaling = cpr_calculate_scaling(quot_offset, drv, in cpr_corner_init()
1184 } else if (corner->freq == fuse->max_freq) { in cpr_corner_init()
1190 freq_diff = fuse->max_freq - corner->freq; in cpr_corner_init()
1192 corner->quot_adjust = scaling * freq_diff_mhz / 1000; in cpr_corner_init()
1194 corner->uV = cpr_interpolate(corner, step_volt, fdata); in cpr_corner_init()
1197 corner->max_uV = fuse->max_uV; in cpr_corner_init()
1198 corner->min_uV = fuse->min_uV; in cpr_corner_init()
1199 corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV); in cpr_corner_init()
1200 corner->last_uV = corner->uV; in cpr_corner_init()
1203 if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV) in cpr_corner_init()
1204 corner->max_uV = corner->uV; in cpr_corner_init()
1205 else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV) in cpr_corner_init()
1206 corner->max_uV = max(corner->min_uV, fuse->uV); in cpr_corner_init()
1208 dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i, in cpr_corner_init()
1209 corner->min_uV, corner->uV, corner->max_uV, in cpr_corner_init()
1210 fuse->quot - corner->quot_adjust); in cpr_corner_init()
1216 static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv) in cpr_get_fuses() argument
1218 const struct cpr_desc *desc = drv->desc; in cpr_get_fuses()
1222 fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners, in cpr_get_fuses()
1226 return ERR_PTR(-ENOMEM); in cpr_get_fuses()
1228 for (i = 0; i < desc->num_fuse_corners; i++) { in cpr_get_fuses()
1231 snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1); in cpr_get_fuses()
1232 fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1234 return ERR_PTR(-ENOMEM); in cpr_get_fuses()
1236 snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1); in cpr_get_fuses()
1237 fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1240 return ERR_PTR(-ENOMEM); in cpr_get_fuses()
1242 snprintf(tbuf, 32, "cpr_quotient%d", i + 1); in cpr_get_fuses()
1243 fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL); in cpr_get_fuses()
1245 return ERR_PTR(-ENOMEM); in cpr_get_fuses()
1247 snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1); in cpr_get_fuses()
1248 fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf, in cpr_get_fuses()
1251 return ERR_PTR(-ENOMEM); in cpr_get_fuses()
1257 static void cpr_set_loop_allowed(struct cpr_drv *drv) in cpr_set_loop_allowed() argument
1259 drv->loop_disabled = false; in cpr_set_loop_allowed()
1262 static int cpr_init_parameters(struct cpr_drv *drv) in cpr_init_parameters() argument
1264 const struct cpr_desc *desc = drv->desc; in cpr_init_parameters()
1267 clk = clk_get(drv->dev, "ref"); in cpr_init_parameters()
1271 drv->ref_clk_khz = clk_get_rate(clk) / 1000; in cpr_init_parameters()
1274 if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK || in cpr_init_parameters()
1275 desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK || in cpr_init_parameters()
1276 desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK || in cpr_init_parameters()
1277 desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK || in cpr_init_parameters()
1278 desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK || in cpr_init_parameters()
1279 desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK) in cpr_init_parameters()
1280 return -EINVAL; in cpr_init_parameters()
1282 dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n", in cpr_init_parameters()
1283 desc->up_threshold, desc->down_threshold); in cpr_init_parameters()
1288 static int cpr_find_initial_corner(struct cpr_drv *drv) in cpr_find_initial_corner() argument
1295 if (!drv->cpu_clk) { in cpr_find_initial_corner()
1296 dev_err(drv->dev, "cannot get rate from NULL clk\n"); in cpr_find_initial_corner()
1297 return -EINVAL; in cpr_find_initial_corner()
1300 end = &drv->corners[drv->num_corners - 1]; in cpr_find_initial_corner()
1301 rate = clk_get_rate(drv->cpu_clk); in cpr_find_initial_corner()
1314 for (iter = drv->corners; iter <= end; iter++) { in cpr_find_initial_corner()
1315 if (iter->freq > rate) in cpr_find_initial_corner()
1318 if (iter->freq == rate) { in cpr_find_initial_corner()
1319 drv->corner = iter; in cpr_find_initial_corner()
1322 if (iter->freq < rate) in cpr_find_initial_corner()
1323 drv->corner = iter; in cpr_find_initial_corner()
1326 if (!drv->corner) { in cpr_find_initial_corner()
1327 dev_err(drv->dev, "boot up corner not found\n"); in cpr_find_initial_corner()
1328 return -EINVAL; in cpr_find_initial_corner()
1331 dev_dbg(drv->dev, "boot up perf state: %u\n", i); in cpr_find_initial_corner()
1343 .up_threshold = 1,
1346 .gcnt_us = 1,
1347 .vdd_apc_step_up_limit = 1,
1348 .vdd_apc_step_down_limit = 1,
1361 .quot_scale = 1,
1366 /* fuse corner 1 */
1374 .quot_scale = 1,
1375 .quot_adjust = -20,
1387 .quot_scale = 1,
1419 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_off() local
1421 return cpr_disable(drv); in cpr_power_off()
1426 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_power_on() local
1428 return cpr_enable(drv); in cpr_power_on()
1434 struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd); in cpr_pd_attach_dev() local
1435 const struct acc_desc *acc_desc = drv->acc_desc; in cpr_pd_attach_dev()
1438 guard(mutex)(&drv->lock); in cpr_pd_attach_dev()
1440 dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev)); in cpr_pd_attach_dev()
1449 if (drv->attached_cpu_dev) in cpr_pd_attach_dev()
1461 drv->cpu_clk = devm_clk_get(dev, NULL); in cpr_pd_attach_dev()
1462 if (IS_ERR(drv->cpu_clk)) in cpr_pd_attach_dev()
1463 return dev_err_probe(drv->dev, PTR_ERR(drv->cpu_clk), in cpr_pd_attach_dev()
1466 drv->attached_cpu_dev = dev; in cpr_pd_attach_dev()
1468 dev_dbg(drv->dev, "using cpu clk from: %s\n", in cpr_pd_attach_dev()
1469 dev_name(drv->attached_cpu_dev)); in cpr_pd_attach_dev()
1479 ret = dev_pm_opp_get_opp_count(&drv->pd.dev); in cpr_pd_attach_dev()
1481 dev_err(drv->dev, "could not get OPP count\n"); in cpr_pd_attach_dev()
1484 drv->num_corners = ret; in cpr_pd_attach_dev()
1486 if (drv->num_corners < 2) { in cpr_pd_attach_dev()
1487 dev_err(drv->dev, "need at least 2 OPPs to use CPR\n"); in cpr_pd_attach_dev()
1488 return -EINVAL; in cpr_pd_attach_dev()
1491 drv->corners = devm_kcalloc(drv->dev, drv->num_corners, in cpr_pd_attach_dev()
1492 sizeof(*drv->corners), in cpr_pd_attach_dev()
1494 if (!drv->corners) in cpr_pd_attach_dev()
1495 return -ENOMEM; in cpr_pd_attach_dev()
1497 ret = cpr_corner_init(drv); in cpr_pd_attach_dev()
1501 cpr_set_loop_allowed(drv); in cpr_pd_attach_dev()
1503 ret = cpr_init_parameters(drv); in cpr_pd_attach_dev()
1508 ret = cpr_config(drv); in cpr_pd_attach_dev()
1512 ret = cpr_find_initial_corner(drv); in cpr_pd_attach_dev()
1516 if (acc_desc->config) in cpr_pd_attach_dev()
1517 regmap_multi_reg_write(drv->tcsr, acc_desc->config, in cpr_pd_attach_dev()
1518 acc_desc->num_regs_per_fuse); in cpr_pd_attach_dev()
1521 if (acc_desc->enable_mask) in cpr_pd_attach_dev()
1522 regmap_update_bits(drv->tcsr, acc_desc->enable_reg, in cpr_pd_attach_dev()
1523 acc_desc->enable_mask, in cpr_pd_attach_dev()
1524 acc_desc->enable_mask); in cpr_pd_attach_dev()
1526 dev_info(drv->dev, "driver initialized with %u OPPs\n", in cpr_pd_attach_dev()
1527 drv->num_corners); in cpr_pd_attach_dev()
1536 struct cpr_drv *drv = s->private; in cpr_debug_info_show() local
1540 corner = drv->corner; in cpr_debug_info_show()
1541 fuse_corner = corner->fuse_corner; in cpr_debug_info_show()
1544 corner->last_uV); in cpr_debug_info_show()
1546 ro_sel = fuse_corner->ring_osc_idx; in cpr_debug_info_show()
1547 gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel)); in cpr_debug_info_show()
1550 ctl = cpr_read(drv, REG_RBCPR_CTL); in cpr_debug_info_show()
1553 irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS); in cpr_debug_info_show()
1556 reg = cpr_read(drv, REG_RBCPR_RESULT_0); in cpr_debug_info_show()
1582 static void cpr_debugfs_init(struct cpr_drv *drv) in cpr_debugfs_init() argument
1584 drv->debugfs = debugfs_create_dir("qcom_cpr", NULL); in cpr_debugfs_init()
1586 debugfs_create_file("debug_info", 0444, drv->debugfs, in cpr_debugfs_init()
1587 drv, &cpr_debug_info_fops); in cpr_debugfs_init()
1592 struct device *dev = &pdev->dev; in cpr_probe()
1593 struct cpr_drv *drv; in cpr_probe() local
1600 if (!data || !data->cpr_desc || !data->acc_desc) in cpr_probe()
1601 return -EINVAL; in cpr_probe()
1603 drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL); in cpr_probe()
1604 if (!drv) in cpr_probe()
1605 return -ENOMEM; in cpr_probe()
1606 drv->dev = dev; in cpr_probe()
1607 drv->desc = data->cpr_desc; in cpr_probe()
1608 drv->acc_desc = data->acc_desc; in cpr_probe()
1610 drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners, in cpr_probe()
1611 sizeof(*drv->fuse_corners), in cpr_probe()
1613 if (!drv->fuse_corners) in cpr_probe()
1614 return -ENOMEM; in cpr_probe()
1616 np = of_parse_phandle(dev->of_node, "acc-syscon", 0); in cpr_probe()
1618 return -ENODEV; in cpr_probe()
1620 drv->tcsr = syscon_node_to_regmap(np); in cpr_probe()
1622 if (IS_ERR(drv->tcsr)) in cpr_probe()
1623 return PTR_ERR(drv->tcsr); in cpr_probe()
1625 drv->base = devm_platform_ioremap_resource(pdev, 0); in cpr_probe()
1626 if (IS_ERR(drv->base)) in cpr_probe()
1627 return PTR_ERR(drv->base); in cpr_probe()
1631 return -EINVAL; in cpr_probe()
1633 drv->vdd_apc = devm_regulator_get(dev, "vdd-apc"); in cpr_probe()
1634 if (IS_ERR(drv->vdd_apc)) in cpr_probe()
1635 return PTR_ERR(drv->vdd_apc); in cpr_probe()
1648 drv->cpr_fuses = cpr_get_fuses(drv); in cpr_probe()
1649 if (IS_ERR(drv->cpr_fuses)) in cpr_probe()
1650 return PTR_ERR(drv->cpr_fuses); in cpr_probe()
1652 ret = cpr_populate_ring_osc_idx(drv); in cpr_probe()
1656 ret = cpr_fuse_corner_init(drv); in cpr_probe()
1660 mutex_init(&drv->lock); in cpr_probe()
1665 "cpr", drv); in cpr_probe()
1669 drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name, in cpr_probe()
1671 if (!drv->pd.name) in cpr_probe()
1672 return -EINVAL; in cpr_probe()
1674 drv->pd.power_off = cpr_power_off; in cpr_probe()
1675 drv->pd.power_on = cpr_power_on; in cpr_probe()
1676 drv->pd.set_performance_state = cpr_set_performance_state; in cpr_probe()
1677 drv->pd.attach_dev = cpr_pd_attach_dev; in cpr_probe()
1679 ret = pm_genpd_init(&drv->pd, NULL, true); in cpr_probe()
1683 ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd); in cpr_probe()
1687 platform_set_drvdata(pdev, drv); in cpr_probe()
1688 cpr_debugfs_init(drv); in cpr_probe()
1693 pm_genpd_remove(&drv->pd); in cpr_probe()
1699 struct cpr_drv *drv = platform_get_drvdata(pdev); in cpr_remove() local
1701 if (cpr_is_allowed(drv)) { in cpr_remove()
1702 cpr_ctl_disable(drv); in cpr_remove()
1703 cpr_irq_set(drv, 0); in cpr_remove()
1706 of_genpd_del_provider(pdev->dev.of_node); in cpr_remove()
1707 pm_genpd_remove(&drv->pd); in cpr_remove()
1709 debugfs_remove_recursive(drv->debugfs); in cpr_remove()
1713 { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
1722 .name = "qcom-cpr",