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/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
[all …]
/linux/drivers/dpll/
H A Ddpll_netlink.c3 * Generic netlink for DPLL management framework
16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
[all …]
H A Ddpll_core.c3 * dpll_core.c - DPLL subsystem kernel-space interface implementation.
19 /* Mutex lock to protect DPLL subsystem devices and pins */
152 dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll,
162 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
175 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
177 ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL); in dpll_xa_ref_dpll_add()
188 xa_erase(xa_dplls, dpll->id); in dpll_xa_ref_dpll_add()
204 dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_add()
154 dpll_xa_ref_dpll_add(struct xarray * xa_dplls,struct dpll_device * dpll,const struct dpll_pin_ops * ops,void * priv,void * cookie) dpll_xa_ref_dpll_add() argument
208 dpll_xa_ref_dpll_del(struct xarray * xa_dplls,struct dpll_device * dpll,const struct dpll_pin_ops * ops,void * priv,void * cookie) dpll_xa_ref_dpll_del() argument
245 struct dpll_device *dpll; dpll_device_alloc() local
284 struct dpll_device *dpll, *ret = NULL; dpll_device_get() local
313 dpll_device_put(struct dpll_device * dpll) dpll_device_put() argument
329 dpll_device_registration_find(struct dpll_device * dpll,const struct dpll_device_ops * ops,void * priv) dpll_device_registration_find() argument
355 dpll_device_register(struct dpll_device * dpll,enum dpll_type type,const struct dpll_device_ops * ops,void * priv) dpll_device_register() argument
410 dpll_device_unregister(struct dpll_device * dpll,const struct dpll_device_ops * ops,void * priv) dpll_device_unregister() argument
609 __dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_register() argument
643 dpll_pin_register(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_register() argument
680 __dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv,void * cookie) __dpll_pin_unregister() argument
701 dpll_pin_unregister(struct dpll_device * dpll,struct dpll_pin * pin,const struct dpll_pin_ops * ops,void * priv) dpll_pin_unregister() argument
832 dpll_device_registration_first(struct dpll_device * dpll) dpll_device_registration_first() argument
842 dpll_priv(struct dpll_device * dpll) dpll_priv() argument
850 dpll_device_ops(struct dpll_device * dpll) dpll_device_ops() argument
869 dpll_pin_on_dpll_priv(struct dpll_device * dpll,struct dpll_pin * pin) dpll_pin_on_dpll_priv() argument
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H A Ddpll_core.h10 #include <linux/dpll.h>
18 * struct dpll_device - stores DPLL device internal data
19 * @id: unique id number for device given by dpll subsystem
21 * @clock_id: unique identifier (clock_id) of a dpll
23 * @type: type of a dpll
24 * @pin_refs: stores pins registered within a dpll
26 * @registration_list: list of registered ops and priv data of dpll owners
40 * struct dpll_pin - structure for a dpll pin
41 * @id: unique id number for pin given by dpll subsystem
66 * struct dpll_pin_ref - structure for referencing either dpll or pins
[all …]
H A DMakefile3 # Makefile for DPLL drivers.
6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
H A DKconfig3 # Generic DPLL drivers configuration
6 menu "DPLL device support"
8 config DPLL config
11 source "drivers/dpll/zl3073x/Kconfig"
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c7 #include <linux/dpll.h>
89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
90 * between SMA/U.FL pins/connectors and dpll device, best to give user access
186 * @dpll: pointer to dpll
187 * @dpll_priv: private data pointer passed on dpll registration
201 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
225 * @dpll: pointer to dpll
226 * @dpll_priv: private data pointer passed on dpll registration
239 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
242 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
[all …]
H A Dice_dpll.h24 * @pin: dpll pin structure
58 /** ice_dpll - store info required for DPLL control
59 * @dpll: pointer to dpll dev
61 * @dpll_idx: index of dpll on the NIC
64 * @ref_state: state of dpll reference signals
65 * @eec_mode: eec_mode dpll is configured for
66 * @phase_offset: phase offset of active pin vs dpll signal
67 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
69 * @dpll_state: current dpll sync state
70 * @prev_dpll_state: last dpll sync state
[all …]
/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c3 * OMAP DPLL clock support
137 * _register_dpll - low level registration of a DPLL clock
141 * Finalizes DPLL registration process. In case a failure (clk-ref or
207 * Initializes a DPLL x 2 clock from device tree data.
264 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
265 * @node: device node containing the DPLL info
266 * @ops: ops for the DPLL
267 * @ddt: DPLL data template to use
269 * Initializes a DPLL clock from device tree data.
314 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml3 name: dpll
5 doc: DPLL subsystem.
12 working modes a dpll can support, differentiates if and how dpll selects
18 doc: input can be only selected by sending a request to dpll
22 doc: highest prio input pin auto selected by dpll
28 provides information of dpll device lock status, valid values for
34 dpll was not yet locked to any valid input (or forced by setting
40 dpll is locked to a valid signal, but no holdover available
44 dpll is locked and holdover acquired
48 dpll is in holdover state - lost a valid lock or was forced
[all …]
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
30 dpll-types:
31 description: List of DPLL channel types, one per DPLL instance.
38 description: DPLL input pins
49 $ref: /schemas/dpll/dpll-pin.yaml
[all …]
H A Dmicrochip,zl30731.yaml4 $id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
7 title: Microchip Azurite DPLL device
13 Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14 provides up to 5 independent DPLL channels, up to 10 differential or
35 - $ref: /schemas/dpll/dpll-device.yaml#
46 dpll@70 {
49 dpll-types = "pps", "eec";
82 dpll@70 {
87 dpll-types = "pps";
H A Ddpll-pin.yaml4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
7 title: DPLL Pin
13 The DPLL pin is either a physical input or output pin that is provided
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
23 description: Hardware index of the DPLL pin.
/linux/drivers/dpll/zl3073x/
H A Ddpll.c8 #include <linux/dpll.h>
20 #include "dpll.h"
28 * struct zl3073x_dpll_pin - DPLL pin
29 * @list: this DPLL pin list entry
30 * @dpll: DPLL the pin is registered to
45 struct zl3073x_dpll *dpll; member
92 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get() argument
106 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
148 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
181 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_input_pin_ffo_get() argument
[all …]
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
/linux/include/linux/clk/
H A Dti.h29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47 * @max_rate: maximum clock rate for the DPLL
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c4 #include <linux/dpll.h>
7 /* This structure represents a reference to DPLL, one is created
11 struct dpll_device *dpll; member
144 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
161 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
198 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
300 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
[all …]
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
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