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/linux/drivers/dpll/
H A Ddpll_netlink.c3 * Generic netlink for DPLL management framework
16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
99 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_netdev_pin_handle_size()
102 const struct dpll_device_ops *ops = dpll_device_ops(dpll);
106 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_netdev_add_pin_handle()
116 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode()
110 dpll_msg_add_mode(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_mode() argument
127 dpll_msg_add_mode_supported(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_mode_supported() argument
159 dpll_msg_add_phase_offset_monitor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_phase_offset_monitor() argument
179 dpll_msg_add_freq_monitor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_freq_monitor() argument
200 dpll_msg_add_phase_offset_avg_factor(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_phase_offset_avg_factor() argument
220 dpll_msg_add_lock_status(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_lock_status() argument
244 dpll_msg_add_temp(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_temp() argument
263 dpll_msg_add_clock_quality_level(struct sk_buff * msg,struct dpll_device * dpll,struct netlink_ext_ack * extack) dpll_msg_add_clock_quality_level() argument
289 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_prio() local
311 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_on_dpll_state() local
333 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_direction() local
353 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_phase_adjust() local
376 struct dpll_device *dpll = ref->dpll; dpll_msg_add_phase_offset() local
399 struct dpll_device *dpll = ref->dpll; dpll_msg_add_ffo() local
429 struct dpll_device *dpll = ref->dpll; dpll_msg_add_measured_freq() local
460 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_freq() local
501 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_esync() local
547 struct dpll_device *dpll = ref->dpll; dpll_msg_add_pin_ref_sync() local
746 dpll_device_get_one(struct dpll_device * dpll,struct sk_buff * msg,struct netlink_ext_ack * extack) dpll_device_get_one() argument
790 dpll_device_event_send(enum dpll_cmd event,struct dpll_device * dpll) dpll_device_event_send() argument
820 dpll_device_create_ntf(struct dpll_device * dpll) dpll_device_create_ntf() argument
826 dpll_device_delete_ntf(struct dpll_device * dpll) dpll_device_delete_ntf() argument
840 __dpll_device_change_ntf(struct dpll_device * dpll) __dpll_device_change_ntf() argument
855 dpll_device_change_ntf(struct dpll_device * dpll) dpll_device_change_ntf() argument
948 dpll_mode_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_mode_set() argument
987 dpll_phase_offset_monitor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_phase_offset_monitor_set() argument
1012 dpll_phase_offset_avg_factor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_phase_offset_avg_factor_set() argument
1029 dpll_freq_monitor_set(struct dpll_device * dpll,struct nlattr * a,struct netlink_ext_ack * extack) dpll_freq_monitor_set() argument
1061 struct dpll_device *dpll; dpll_pin_freq_set() local
1126 struct dpll_device *dpll; dpll_pin_esync_set() local
1206 struct dpll_device *dpll; dpll_pin_ref_sync_state_set() local
1338 dpll_pin_state_set(struct dpll_device * dpll,struct dpll_pin * pin,enum dpll_pin_state state,struct netlink_ext_ack * extack) dpll_pin_state_set() argument
1366 dpll_pin_prio_set(struct dpll_device * dpll,struct dpll_pin * pin,u32 prio,struct netlink_ext_ack * extack) dpll_pin_prio_set() argument
1393 dpll_pin_direction_set(struct dpll_pin * pin,struct dpll_device * dpll,enum dpll_pin_direction direction,struct netlink_ext_ack * extack) dpll_pin_direction_set() argument
1427 struct dpll_device *dpll; dpll_pin_phase_adj_set() local
1506 struct dpll_device *dpll; dpll_pin_parent_device_set() local
1833 struct dpll_device *dpll_match = NULL, *dpll; dpll_device_find() local
1901 struct dpll_device *dpll; dpll_nl_device_id_get_doit() local
1933 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_get_doit() local
1959 dpll_set_from_nlattr(struct dpll_device * dpll,struct genl_info * info) dpll_set_from_nlattr() argument
1998 struct dpll_device *dpll = info->user_ptr[0]; dpll_nl_device_set_doit() local
2006 struct dpll_device *dpll; dpll_nl_device_get_dumpit() local
[all...]
H A DMakefile3 # Makefile for DPLL drivers.
6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c8 #include <linux/dpll.h>
99 * for pin control. For E810 NIC with dpll there is additional MUX-related logic in ice_dpll_is_sw_pin()
100 * between SMA/U.FL pins/connectors and dpll device, best to give user access in ice_dpll_is_sw_pin()
196 * @dpll: pointer to dpll
197 * @dpll_priv: private data pointer passed on dpll registration
211 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set()
235 * @dpll: pointer to dpll
236 * @dpll_priv: private data pointer passed on dpll registratio
202 ice_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,const u32 frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_frequency_set() argument
240 ice_dpll_input_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_input_frequency_set() argument
265 ice_dpll_output_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_output_frequency_set() argument
291 ice_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_frequency_get() argument
324 ice_dpll_input_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_input_frequency_get() argument
349 ice_dpll_output_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_output_frequency_get() argument
374 ice_dpll_sw_pin_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) ice_dpll_sw_pin_frequency_set() argument
414 ice_dpll_sw_pin_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) ice_dpll_sw_pin_frequency_get() argument
812 ice_dpll_hw_input_prio_set(struct ice_pf * pf,struct ice_dpll * dpll,struct ice_dpll_pin * pin,const u32 prio,struct netlink_ext_ack * extack) ice_dpll_hw_input_prio_set() argument
848 ice_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack) ice_dpll_lock_status_get() argument
877 ice_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack) ice_dpll_mode_get() argument
903 ice_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) ice_dpll_phase_offset_monitor_set() argument
934 ice_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) ice_dpll_phase_offset_monitor_get() argument
971 ice_dpll_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,bool enable,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_pin_state_set() argument
1014 ice_dpll_output_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_output_state_set() argument
1049 ice_dpll_input_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_input_state_set() argument
1078 ice_dpll_pin_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack,enum ice_dpll_pin_type pin_type) ice_dpll_pin_state_get() argument
1123 ice_dpll_output_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_output_state_get() argument
1149 ice_dpll_input_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_input_state_get() argument
1284 ice_dpll_ufl_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_ufl_pin_state_set() argument
1397 ice_dpll_sw_pin_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) ice_dpll_sw_pin_state_get() argument
1453 ice_dpll_sma_pin_state_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) ice_dpll_sma_pin_state_set() argument
1517 ice_dpll_input_prio_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) ice_dpll_input_prio_get() argument
1549 ice_dpll_input_prio_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) ice_dpll_input_prio_set() argument
1569 ice_dpll_sw_input_prio_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) ice_dpll_sw_input_prio_get() argument
1588 ice_dpll_sw_input_prio_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) ice_dpll_sw_input_prio_set() argument
1624 ice_dpll_input_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_input_direction() argument
1649 ice_dpll_output_direction(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_output_direction() argument
1676 ice_dpll_pin_sma_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack) ice_dpll_pin_sma_direction_set() argument
1714 ice_dpll_pin_sw_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) ice_dpll_pin_sw_direction_get() argument
1748 ice_dpll_pin_phase_adjust_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) ice_dpll_pin_phase_adjust_get() argument
1782 ice_dpll_pin_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack,enum ice_dpll_pin_type type) ice_dpll_pin_phase_adjust_set() argument
1851 ice_dpll_input_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_input_phase_adjust_set() argument
1879 ice_dpll_output_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_output_phase_adjust_set() argument
1907 ice_dpll_sw_phase_adjust_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) ice_dpll_sw_phase_adjust_get() argument
1942 ice_dpll_sw_phase_adjust_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) ice_dpll_sw_phase_adjust_set() argument
1986 ice_dpll_phase_offset_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack) ice_dpll_phase_offset_get() argument
2062 ice_dpll_output_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_output_esync_set() argument
2117 ice_dpll_output_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_output_esync_get() argument
2166 ice_dpll_input_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_input_esync_set() argument
2221 ice_dpll_input_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_input_esync_get() argument
2270 ice_dpll_sw_esync_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) ice_dpll_sw_esync_set() argument
2306 ice_dpll_sw_esync_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) ice_dpll_sw_esync_get() argument
3131 ice_dpll_unregister_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count) ice_dpll_unregister_pins() argument
3185 ice_dpll_register_pins(struct dpll_device * dpll,struct ice_dpll_pin * pins,const struct dpll_pin_ops * ops,int count) ice_dpll_register_pins() argument
[all...]
H A Dice_dpll.h49 * @pin: dpll pin structure
88 /** ice_dpll - store info required for DPLL control
89 * @dpll: pointer to dpll dev
92 * @dpll_idx: index of dpll on the NIC
95 * @ref_state: state of dpll reference signals
96 * @eec_mode: eec_mode dpll is configured for
97 * @phase_offset: phase offset of active pin vs dpll signal
98 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
100 * @dpll_state: current dpll syn
104 struct dpll_device *dpll; global() member
[all...]
/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c3 * OMAP DPLL clock support
137 * _register_dpll - low level registration of a DPLL clock
141 * Finalizes DPLL registration process. In case a failure (clk-ref or
207 * Initializes a DPLL x 2 clock from device tree data.
264 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
265 * @node: device node containing the DPLL info
266 * @ops: ops for the DPLL
267 * @ddt: DPLL data template to use
269 * Initializes a DPLL clock from device tree data.
314 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/linux/include/linux/
H A Ddpll.h10 #include <uapi/linux/dpll.h>
25 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
27 int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
29 int (*supported_modes_get)(const struct dpll_device *dpll,
32 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
36 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
38 int (*clock_quality_level_get)(const struct dpll_device *dpll,
42 int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
46 int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
50 int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
201 struct dpll_device *dpll; global() member
[all...]
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
30 dpll-types:
31 description: List of DPLL channel types, one per DPLL instance.
38 description: DPLL input pins
49 $ref: /schemas/dpll/dpll-pin.yaml
[all …]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c9 #include <linux/dpll.h>
22 #include "dpll.h"
30 * struct zl3073x_dpll_pin - DPLL pin
31 * @list: this DPLL pin list entry
32 * @dpll: DPLL the pin is registered to
49 struct zl3073x_dpll *dpll;
98 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get()
126 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get()
163 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set()
48 struct zl3073x_dpll *dpll; global() member
97 zl3073x_dpll_pin_direction_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack) zl3073x_dpll_pin_direction_get() argument
125 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_esync_get() argument
162 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_esync_set() argument
297 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * ffo,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_ffo_get() argument
310 zl3073x_dpll_input_pin_measured_freq_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * measured_freq,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_measured_freq_get() argument
325 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_frequency_get() argument
342 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_frequency_set() argument
389 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s64 * phase_offset,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_offset_get() argument
445 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_get() argument
478 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_phase_adjust_set() argument
550 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_get() argument
563 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state state,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_state_on_dpll_set() argument
649 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 * prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_get() argument
661 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u32 prio,struct netlink_ext_ack * extack) zl3073x_dpll_input_pin_prio_set() argument
692 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,struct dpll_pin_esync * esync,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_get() argument
750 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 freq,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_esync_set() argument
807 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_get() argument
822 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_frequency_set() argument
896 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 * phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_get() argument
919 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,s32 phase_adjust,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_phase_adjust_set() argument
943 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin * dpll_pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_output_pin_state_on_dpll_get() argument
955 zl3073x_dpll_temp_get(const struct dpll_device * dpll,void * dpll_priv,s32 * temp,struct netlink_ext_ack * extack) zl3073x_dpll_temp_get() argument
974 zl3073x_dpll_lock_status_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack) zl3073x_dpll_lock_status_get() argument
1018 zl3073x_dpll_supported_modes_get(const struct dpll_device * dpll,void * dpll_priv,unsigned long * modes,struct netlink_ext_ack * extack) zl3073x_dpll_supported_modes_get() argument
1041 zl3073x_dpll_mode_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode * mode,struct netlink_ext_ack * extack) zl3073x_dpll_mode_get() argument
1071 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device * dpll,void * dpll_priv,u32 * factor,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_avg_factor_get() argument
1083 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device * dpll,void * dpll_priv,u32 factor,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_avg_factor_set() argument
1117 zl3073x_dpll_mode_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_mode mode,struct netlink_ext_ack * extack) zl3073x_dpll_mode_set() argument
1179 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_get() argument
1195 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) zl3073x_dpll_phase_offset_monitor_set() argument
1208 zl3073x_dpll_freq_monitor_get(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state * state,struct netlink_ext_ack * extack) zl3073x_dpll_freq_monitor_get() argument
1224 zl3073x_dpll_freq_monitor_set(const struct dpll_device * dpll,void * dpll_priv,enum dpll_feature_state state,struct netlink_ext_ack * extack) zl3073x_dpll_freq_monitor_set() argument
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H A Ddpll.h6 #include <linux/dpll.h>
12 * struct zl3073x_dpll - ZL3073x DPLL sub-device structure
13 * @list: this DPLL list entry
15 * @id: DPLL index
18 * @ops: DPLL device operations for this instance
19 * @dpll_dev: pointer to registered DPLL device
21 * @lock_status: last saved DPLL lock status
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
H A Dprop.c113 /* Set package_label pointer in DPLL core properties to generated in zl3073x_prop_pin_package_label_set()
242 /* Look for pin type property and translate its value to DPLL in zl3073x_pin_props_get()
276 * DPLL core pin properties requires list of frequency ranges. in zl3073x_pin_props_get()
352 * zl3073x_prop_dpll_type_get - get DPLL channel type
354 * @index: DPLL channel index
356 * Return: DPLL type for given DPLL channel
364 /* Read dpll types property from firmware */ in zl3073x_prop_dpll_type_get()
365 count = device_property_read_string_array(zldev->dev, "dpll-types", in zl3073x_prop_dpll_type_get()
377 dev_info(zldev->dev, "Unknown DPLL type '%s', using default\n", in zl3073x_prop_dpll_type_get()
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
161 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
162 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
164 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
168 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
169 dpll |= in psb_intel_crtc_mode_set()
174 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
H A Dcdv_intel_display.c208 /* Unlike most Intel display engines, on Cedarview the DPLL registers
210 * DPLL reference clock is on in the DPLL control register, but before
211 * the DPLL is enabled in the DPLL control register.
262 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
679 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
681 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
682 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
/linux/include/linux/clk/
H A Dti.h29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47 * @max_rate: maximum clock rate for the DPLL
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c4 #include <linux/dpll.h>
7 /* This structure represents a reference to DPLL, one is created
11 struct dpll_device *dpll; member
146 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
163 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
200 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
259 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
270 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
288 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
302 const struct dpll_device *dpll, voi in mlx5_dpll_ffo_get() argument
[all...]
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
/linux/drivers/ata/
H A Dpata_hpt3x2n.c61 /* 66MHz DPLL clocks */
263 * We must use the DPLL for
299 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
372 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
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