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/linux/drivers/dpll/
H A Ddpll_netlink.c3 * Generic netlink for DPLL management framework
16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
92 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
95 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
99 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode()
109 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode_supported() argument
112 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode_supported()
120 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); in dpll_msg_add_mode_supported()
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H A Ddpll_core.c3 * dpll_core.c - DPLL subsystem kernel-space interface implementation.
19 /* Mutex lock to protect DPLL subsystem devices and pins */
154 dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_add() argument
164 if (ref->dpll != dpll) in dpll_xa_ref_dpll_add()
179 ref->dpll = dpll; in dpll_xa_ref_dpll_add()
181 ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL); in dpll_xa_ref_dpll_add()
192 xa_erase(xa_dplls, dpll->id); in dpll_xa_ref_dpll_add()
208 dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll, in dpll_xa_ref_dpll_del() argument
216 if (ref->dpll != dpll) in dpll_xa_ref_dpll_del()
245 struct dpll_device *dpll; in dpll_device_alloc() local
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H A Ddpll_core.h10 #include <linux/dpll.h>
18 * struct dpll_device - stores DPLL device internal data
19 * @id: unique id number for device given by dpll subsystem
21 * @clock_id: unique identifier (clock_id) of a dpll
23 * @type: type of a dpll
24 * @pin_refs: stores pins registered within a dpll
26 * @registration_list: list of registered ops and priv data of dpll owners
40 * struct dpll_pin - structure for a dpll pin
41 * @id: unique id number for pin given by dpll subsystem
65 * struct dpll_pin_ref - structure for referencing either dpll or pins
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H A DMakefile3 # Makefile for DPLL drivers.
6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c7 #include <linux/dpll.h>
113 * @dpll: pointer to dpll
114 * @dpll_priv: private data pointer passed on dpll registration
128 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
152 * @dpll: pointer to dpll
153 * @dpll_priv: private data pointer passed on dpll registration
166 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
169 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
177 * @dpll: pointer to dpll
178 * @dpll_priv: private data pointer passed on dpll registration
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H A Dice_dpll.h12 * @pin: dpll pin structure
37 /** ice_dpll - store info required for DPLL control
38 * @dpll: pointer to dpll dev
40 * @dpll_idx: index of dpll on the NIC
43 * @ref_state: state of dpll reference signals
44 * @eec_mode: eec_mode dpll is configured for
45 * @phase_offset: phase offset of active pin vs dpll signal
46 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
48 * @dpll_state: current dpll sync state
49 * @prev_dpll_state: last dpll sync state
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/linux/Documentation/driver-api/
H A Ddpll.rst4 The Linux kernel dpll subsystem
7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
22 The main purpose of dpll subsystem is to provide general interface
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
52 The number of pins per dpll vary, but usually multiple pins shall be
53 provided for a single dpll device.
68 In general, selected pin (the one which signal is driving the dpll
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/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
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H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
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H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
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H A Ddpll.c3 * OMAP DPLL clock support
143 * _register_dpll - low level registration of a DPLL clock
147 * Finalizes DPLL registration process. In case a failure (clk-ref or
213 * Initializes a DPLL x 2 clock from device tree data.
270 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
271 * @node: device node containing the DPLL info
272 * @ops: ops for the DPLL
273 * @ddt: DPLL data template to use
275 * Initializes a DPLL clock from device tree data.
320 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
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/linux/Documentation/netlink/specs/
H A Ddpll.yaml3 name: dpll
5 doc: DPLL subsystem.
12 working modes a dpll can support, differentiates if and how dpll selects
18 doc: input can be only selected by sending a request to dpll
22 doc: highest prio input pin auto selected by dpll
28 provides information of dpll device lock status, valid values for
34 dpll was not yet locked to any valid input (or forced by setting
40 dpll is locked to a valid signal, but no holdover available
44 dpll is locked and holdover acquired
48 dpll is in holdover state - lost a valid lock or was forced
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/linux/include/linux/
H A Ddpll.h10 #include <uapi/linux/dpll.h>
21 int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
23 int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
27 int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
29 int (*clock_quality_level_get)(const struct dpll_device *dpll,
37 const struct dpll_device *dpll, void *dpll_priv,
41 const struct dpll_device *dpll, void *dpll_priv,
44 const struct dpll_device *dpll, void *dpll_priv,
48 const struct dpll_device *dpll, void *dpll_priv,
57 const struct dpll_device *dpll,
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/linux/include/uapi/linux/
H A Ddpll.h3 /* Documentation/netlink/specs/dpll.yaml */
9 #define DPLL_FAMILY_NAME "dpll"
13 * enum dpll_mode - working modes a dpll can support, differentiates if and how
14 * dpll selects one of its inputs to syntonize with it, valid values for
16 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
17 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
29 * enum dpll_lock_status - provides information of dpll device lock status,
31 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
33 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
35 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
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H A Dcdv_intel_display.c207 /* Unlike most Intel display engines, on Cedarview the DPLL registers
209 * DPLL reference clock is on in the DPLL control register, but before
210 * the DPLL is enabled in the DPLL control register.
261 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
678 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
680 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
681 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
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/linux/include/linux/clk/
H A Dti.h29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47 * @max_rate: maximum clock rate for the DPLL
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Ddpll.c4 #include <linux/dpll.h>
7 /* This structure represents a reference to DPLL, one is created
11 struct dpll_device *dpll; member
144 mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv, in mlx5_dpll_device_lock_status_get() argument
161 static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll, in mlx5_dpll_device_mode_get() argument
198 static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll, in mlx5_dpll_clock_quality_level_get() argument
257 const struct dpll_device *dpll, in mlx5_dpll_pin_direction_get() argument
268 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_get() argument
286 const struct dpll_device *dpll, in mlx5_dpll_state_on_dpll_set() argument
300 const struct dpll_device *dpll, void *dpll_priv, in mlx5_dpll_ffo_get() argument
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/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
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/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
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/linux/drivers/ata/
H A Dpata_hpt3x2n.c61 /* 66MHz DPLL clocks */
263 * We must use the DPLL for
299 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
372 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
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