| /linux/Documentation/devicetree/bindings/dpll/ |
| H A D | dpll-device.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
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| H A D | microchip,zl30731.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Azurite DPLL device
10 - Ivan Vecera <ivecera@redhat.com>
13 Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14 provides up to 5 independent DPLL channels, up to 10 differential or
15 single-ended inputs and 10 differential or 20 single-ended outputs.
21 - microchip,zl30731
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| H A D | dpll-pin.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DPLL Pin
10 - Ivan Vecera <ivecera@redhat.com>
13 The DPLL pin is either a physical input or output pin that is provided
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
23 description: Hardware index of the DPLL pin.
26 connection-type:
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| /linux/Documentation/devicetree/bindings/clock/ti/ |
| H A D | dpll.txt | 1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
10 for the actual DPLL clock.
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
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| /linux/drivers/dpll/zl3073x/ |
| H A D | prop.c | 1 // SPDX-License-Identifier: GPL-2.0-only
16 * zl3073x_pin_check_freq - verify frequency for given pin
62 dev_warn(zldev->dev, in zl3073x_pin_check_freq()
69 * zl3073x_prop_pin_package_label_set - get package label for the pin
78 * REF<n> - differential input reference
79 * REF<n>P & REF<n>N - single-ende
338 const char *types[ZL3073X_MAX_CHANNELS]; zl3073x_prop_dpll_type_get() local
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| /linux/Documentation/netlink/specs/ |
| H A D | dpll.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
3 name: dpll
5 doc: DPLL subsystem.
8 -
12 working modes a dpll can support, differentiates if and how dpll selects
16 -
18 doc: input can be only selected by sending a request to dpll
20 -
22 doc: highest prio input pin auto selected by dpll
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| /linux/include/linux/clk/ |
| H A D | ti.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
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| /linux/arch/arm/mach-omap2/ |
| H A D | clkt2xxx_dpllcore.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * DPLL + CORE_CLK composite clock functions
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
15 * XXX The DPLL and CORE clocks should be split into two separate clock
16 * types.
30 #include "cm-regbits-24xx.h"
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
47 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
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| H A D | cm3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
12 #include <linux/types.h>
21 #include "cm-regbits-34xx.h"
78 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
86 * success or -EBUSY if the module doesn't enable in time.
96 return -EINVAL; in omap3xxx_cm_wait_module_ready()
98 cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1]; in omap3xxx_cm_wait_module_ready()
106 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; in omap3xxx_cm_wait_module_ready()
110 * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
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| H A D | cm2xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
12 #include <linux/types.h>
21 #include "cm-regbits-24xx.h"
75 * DPLL autoidle control
99 * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
115 idlest_offs = idlest_reg->offset & 0xff; in omap2xxx_cm_split_idlest_reg()
124 return -EINVAL; in omap2xxx_cm_split_idlest_reg()
126 offs = idlest_reg->offset; in omap2xxx_cm_split_idlest_reg()
138 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
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| H A D | sram.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
48 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
61 * to an 8-byte boundary.
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
74 new_ceil -= size; in omap_sram_push_address()
105 * The SRAM context is lost during off-idle and stack
115 * SRAM varies. The default accessible size for all device types is 2k. A GP
124 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | ti-phy.txt | 6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
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| /linux/drivers/dpll/ |
| H A D | dpll_nl.h | 1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* Do not edit directly, auto-generated from: */
3 /* Documentation/netlink/specs/dpll.yaml */
4 /* YNL-GE
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| /linux/include/uapi/linux/ |
| H A D | scc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 /* selection of hardware types */
14 #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
90 CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */
92 CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */
136 char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
141 int command; /* one of the KISS-Commands defined above */
142 unsigned param; /* KISS-Param */
150 io_port vector_latch; /* INTACK-Latch (#) */
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dpll.h>
53 * enum ice_dpll_pin_type - enumerate ice pin types:
71 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
83 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
88 * Check if the pin shall be controlled by SW - instead of providing raw access
89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
90 * between SMA/U.FL pins/connectors and dpll device, best to give user access
95 * * true - pin controlled by SW
96 * * false - pin not controlled by SW
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| H A D | ice_common.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_types.h | 3 * Copyright (c) 2007-2008 Intel Corporation
70 /* these are outputs from the chip - integrated only
88 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
104 * create the DMA scatter-gather list for each FB color plane. This sg
116 * in the rotated and remapped GTT view all no-CCS formats (up to 2
224 * state. This must be called _after_ display->get_pipe_config has
225 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
480 * When it rolls over re-auth has to be triggered.
488 * over re-Auth has to be triggered.
543 state of connector->polled in case hotplug storm detection changes it */
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| /linux/Documentation/networking/device_drivers/ethernet/intel/ |
| H A D | ice.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
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| /linux/include/linux/soc/ti/ |
| H A D | omap1-io.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <linux/types.h>
29 * ----------------------------------------------------------------------------
31 * ----------------------------------------------------------------------------
37 * ---------------------------------------------------------------------------
39 * ---------------------------------------------------------------------------
66 * ----------------------------------------------------------------------------
68 * ----------------------------------------------------------------------------
86 /* DPLL control registers */
97 * ----------------------------------------------------------------------------
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| /linux/drivers/clk/ti/ |
| H A D | clock.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Tero Kristo (t-kristo@ti.com)
67 /* DPLL flags */
133 /* Composite clock component types */
142 * struct ti_dt_clk - OMAP DT clock alias declarations
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| /linux/arch/arm/mach-omap1/ |
| H A D | clock_data.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock_data.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
10 * - Clocks that are only available on some chips should be marked with the
18 #include <linux/clk-provider.h>
21 #include <linux/soc/ti/omap1-io.h>
23 #include <asm/mach-types.h> /* for machine_is_* */
32 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
43 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
50 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
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| /linux/net/core/ |
| H A D | rtnetlink.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/types.h>
61 #include <linux/dpll.h>
98 tail->next = defer_kfree_skb_list; in rtnl_kfree_skbs()
146 struct sk_buff *next = head->next; in __rtnl_unlock()
192 mutex_lock(&net->rtnl_mutex); in __rtnl_net_lock()
200 mutex_unlock(&net->rtnl_mutex); in __rtnl_net_unlock()
246 return -1; in rtnl_net_cmp_locks()
252 return net_a < net_b ? -1 : 1; in rtnl_net_cmp_locks()
267 return rtnl_is_locked() && mutex_is_locked(&net->rtnl_mutex); in rtnl_net_is_locked()
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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