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/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
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H A Dmicrochip,zl30731.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Azurite DPLL device
10 - Ivan Vecera <ivecera@redhat.com>
13 Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14 provides up to 5 independent DPLL channels, up to 10 differential or
15 single-ended inputs and 10 differential or 20 single-ended outputs.
21 - microchip,zl30731
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H A Ddpll-pin.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-pin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DPLL Pin
10 - Ivan Vecera <ivecera@redhat.com>
13 The DPLL pin is either a physical input or output pin that is provided
14 by a DPLL( Digital Phase-Locked Loop) device. The pin is identified by
23 description: Hardware index of the DPLL pin.
26 connection-type:
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/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
9 sub-types, which effectively result in slightly different setup
10 for the actual DPLL clock.
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
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/linux/drivers/dpll/zl3073x/
H A Dprop.c1 // SPDX-License-Identifier: GPL-2.0-only
16 * zl3073x_pin_check_freq - verify frequency for given pin
62 dev_warn(zldev->dev, in zl3073x_pin_check_freq()
69 * zl3073x_prop_pin_package_label_set - get package label for the pin
78 * REF<n> - differential input reference
79 * REF<n>P & REF<n>N - single-ended input reference (P or N pin)
80 * OUT<n> - differential output
81 * OUT<n>P & OUT<n>N - single-ended output (P or N pin)
110 snprintf(props->package_label, sizeof(props->package_label), "%s%u%s", in zl3073x_prop_pin_package_label_set()
113 /* Set package_label pointer in DPLL core properties to generated in zl3073x_prop_pin_package_label_set()
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H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/types.h>
30 * struct zl3073x_ref - input reference invariant info
42 * struct zl3073x_out - output invariant info
54 * struct zl3073x_synth - synthesizer invariant info
56 * @dpll: ID of DPLL the synthesizer is driven by
61 u8 dpll; member
66 * struct zl3073x_dev - zl3073x device
89 /* DPLL channels */
140 /* P-pins ids are even while N-pins are odd */ in zl3073x_is_n_pin()
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H A Ddevlink.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/types.h>
11 #include "dpll.h"
15 * zl3073x_devlink_info_get - Devlink device info callback
92 return -EOPNOTSUPP; in zl3073x_devlink_reload_down()
95 list_for_each_entry(zldpll, &zldev->dplls, list) in zl3073x_devlink_reload_down()
114 return -EOPNOTSUPP; in zl3073x_devlink_reload_up()
122 if (zldev->clock_id != val.vu64) { in zl3073x_devlink_reload_up()
123 dev_dbg(zldev->dev, in zl3073x_devlink_reload_up()
125 zldev->clock_id = val.vu64; in zl3073x_devlink_reload_up()
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/linux/Documentation/driver-api/
H A Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
4 The Linux kernel dpll subsystem
7 DPLL chapter
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
22 The main purpose of dpll subsystem is to provide general interface
25 different types of outputs.
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
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/linux/include/uapi/linux/
H A Ddpll.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* Do not edit directly, auto-generated from: */
3 /* Documentation/netlink/specs/dpll.yaml */
4 /* YNL-GEN uapi header */
9 #define DPLL_FAMILY_NAME "dpll"
13 * enum dpll_mode - working modes a dpll can support, differentiates if and how
14 * dpll selects one of its inputs to syntonize with it, valid values for
16 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
17 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
25 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
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H A Dscc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
9 /* selection of hardware types */
14 #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
90 CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */
92 CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */
136 char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
141 int command; /* one of the KISS-Commands defined above */
142 unsigned param; /* KISS-Param */
150 io_port vector_latch; /* INTACK-Latch (#) */
/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
3 name: dpll
5 doc: DPLL subsystem.
8 -
12 working modes a dpll can support, differentiates if and how dpll selects
16 -
18 doc: input can be only selected by sending a request to dpll
20 -
22 doc: highest prio input pin auto selected by dpll
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/linux/include/linux/clk/
H A Dti.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14 * struct clk_omap_reg - OMAP register declaration
29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
43 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
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/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpllcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DPLL + CORE_CLK composite clock functions
5 * Copyright (C) 2005-2008 Texas Instruments, Inc.
6 * Copyright (C) 2004-2010 Nokia Corporation
9 * Richard Woodruff <r-woodruff2@ti.com>
15 * XXX The DPLL and CORE clocks should be split into two separate clock
16 * types.
30 #include "cm-regbits-24xx.h"
44 * omap2xxx_clk_get_core_rate - return the CORE_CLK rate
47 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
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H A Dcm3xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
12 #include <linux/types.h>
21 #include "cm-regbits-34xx.h"
78 * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
86 * success or -EBUSY if the module doesn't enable in time.
96 return -EINVAL; in omap3xxx_cm_wait_module_ready()
98 cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1]; in omap3xxx_cm_wait_module_ready()
106 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; in omap3xxx_cm_wait_module_ready()
110 * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
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H A Dcm2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
12 #include <linux/types.h>
21 #include "cm-regbits-24xx.h"
75 * DPLL autoidle control
99 * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
115 idlest_offs = idlest_reg->offset & 0xff; in omap2xxx_cm_split_idlest_reg()
124 return -EINVAL; in omap2xxx_cm_split_idlest_reg()
126 offs = idlest_reg->offset; in omap2xxx_cm_split_idlest_reg()
138 * omap2xxx_cm_wait_module_ready - wait for a module to leave idle or standby
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H A Dsram.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
48 #define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
61 * to an 8-byte boundary.
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip); in omap_sram_push_address()
74 new_ceil -= size; in omap_sram_push_address()
105 * The SRAM context is lost during off-idle and stack
115 * SRAM varies. The default accessible size for all device types is 2k. A GP
124 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */ in is_sram_locked()
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/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
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/linux/drivers/dpll/
H A Ddpll_nl.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* Do not edit directly, auto-generated from: */
3 /* Documentation/netlink/specs/dpll.yaml */
4 /* YNL-GEN kernel header */
12 #include <uapi/linux/dpll.h>
14 /* Common nested types */
H A Ddpll_nl.c1 // SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 /* Do not edit directly, auto-generated from: */
3 /* Documentation/netlink/specs/dpll.yaml */
4 /* YNL-GEN kernel source */
11 #include <uapi/linux/dpll.h>
13 /* Common nested types */
32 /* DPLL_CMD_DEVICE_ID_GET - do */
39 /* DPLL_CMD_DEVICE_GET - do */
44 /* DPLL_CMD_DEVICE_SET - do */
50 /* DPLL_CMD_PIN_ID_GET - do */
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/dpll.h>
53 * enum ice_dpll_pin_type - enumerate ice pin types:
71 [ICE_DPLL_PIN_TYPE_RCLK_INPUT] = "rclk-input",
83 * ice_dpll_is_sw_pin - check if given pin shall be controlled by SW
88 * Check if the pin shall be controlled by SW - instead of providing raw access
89 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
90 * between SMA/U.FL pins/connectors and dpll device, best to give user access
95 * * true - pin controlled by SW
96 * * false - pin not controlled by SW
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H A Dice_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Dice.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 2018-2021 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Important Notes
16 - Additional Features & Configurations
17 - Performance Optimization
28 This driver supports XDP (Express Data Path) and AF_XDP zero-copy. Note that
43 -------------------------------------------
54 1) Make sure that your system's physical memory is in a high-performance
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/linux/include/linux/soc/ti/
H A Domap1-io.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <linux/types.h>
29 * ----------------------------------------------------------------------------
31 * ----------------------------------------------------------------------------
37 * ---------------------------------------------------------------------------
39 * ---------------------------------------------------------------------------
66 * ----------------------------------------------------------------------------
68 * ----------------------------------------------------------------------------
86 /* DPLL control registers */
97 * ----------------------------------------------------------------------------
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/linux/drivers/clk/ti/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Tero Kristo (t-kristo@ti.com)
67 /* DPLL flags */
133 /* Composite clock component types */
142 * struct ti_dt_clk - OMAP DT clock alias declarations
/linux/arch/arm/mach-omap1/
H A Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
19 #include <linux/clk-provider.h>
20 #include <linux/soc/ti/omap1-io.h>
23 #include <asm/mach-types.h>
49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
50 return val & 1 << clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
67 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
70 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) in omap1_clk_allow_idle()
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