/linux/drivers/phy/rockchip/ |
H A D | phy-rockchip-dp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Rockchip DP PHY driver 6 * Author: Yakir Yang <ykk@@rock-chips.com> 13 #include <linux/phy/phy.h> 32 static int rockchip_set_phy_state(struct phy *phy, bool enable) in rockchip_set_phy_state() argument 34 struct rockchip_dp_phy *dp = phy_get_drvdata(phy); in rockchip_set_phy_state() local 38 ret = regmap_write(dp->grf, GRF_SOC_CON12, in rockchip_set_phy_state() 42 dev_err(dp->dev, "Can't enable PHY power %d\n", ret); in rockchip_set_phy_state() 46 ret = clk_prepare_enable(dp->phy_24m); in rockchip_set_phy_state() 48 clk_disable_unprepare(dp->phy_24m); in rockchip_set_phy_state() [all …]
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H A D | phy-rockchip-typec.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Chris Zhong <zyw@rock-chips.com> 5 * Kever Yang <kever.yang@rock-chips.com> 7 * The ROCKCHIP Type-C PHY has two PLL clocks. The first PLL clock 8 * is used for USB3, the second PLL clock is used for DP. This Type-C PHY has 9 * 3 working modes: USB3 only mode, DP only mode, and USB3+DP mode. 11 * PHY to switch mode between USB3 and USB3+DP, without disconnecting the USB 13 * In The DP only mode, only the DP PLL needs to be powered on, and the 4 lanes 14 * are all used for DP. 24 * 2. DP only mode: [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | qcom,sc8280xp-qmp-usb43dp-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP) 10 - Vinod Koul <vkoul@kernel.org> 13 The QMP PHY controller supports physical layer functionality for a number of 19 - qcom,sc7180-qmp-usb3-dp-phy 20 - qcom,sc7280-qmp-usb3-dp-phy 21 - qcom,sc8180x-qmp-usb3-dp-phy [all …]
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H A D | transmit-amplitude.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Common PHY and network PCS transmit amplitude property 10 Binding describing the peak-to-peak transmit amplitude for common PHYs 14 - Marek Behún <kabel@kernel.org> 17 tx-p2p-microvolt: 19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property 20 contains multiple values for various PHY modes, the [all …]
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H A D | phy-rockchip-typec.txt | 1 * ROCKCHIP type-c PHY 2 --------------------- 5 - compatible : must be "rockchip,rk3399-typec-phy" 6 - reg: Address and length of the usb phy control register set 7 - rockchip,grf : phandle to the syscon managing the "general 9 - clocks : phandle + clock specifier for the phy clocks 10 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref"; 11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or 13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000 14 - resets : a list of phandle + reset specifier pairs [all …]
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H A D | samsung,dp-video-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/samsung,dp-video-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung Exynos SoC DisplayPort PHY 10 - Krzysztof Kozlowski <krzk@kernel.org> 11 - Marek Szyprowski <m.szyprowski@samsung.com> 12 - Sylwester Nawrocki <s.nawrocki@samsung.com> 17 - samsung,exynos5250-dp-video-phy 18 - samsung,exynos5420-dp-video-phy [all …]
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H A D | rockchip,rk3288-dp-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip specific extensions to the Analogix Display Port PHY 10 - Heiko Stuebner <heiko@sntech.de> 14 const: rockchip,rk3288-dp-phy 19 clock-names: 22 "#phy-cells": 26 - compatible [all …]
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/linux/drivers/gpu/drm/xlnx/ |
H A D | zynqmp_dp.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 25 #include <linux/media-bus-format.h> 29 #include <linux/phy/phy.h> 40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); 47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)"); 182 /* PHY configuration and status registers */ 242 * struct zynqmp_dp_link_config - Common link config between source and sink [all …]
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/linux/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_link.c | 1 /* Copyright 2008-2013 Broadcom Corporation 8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL"). 32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy, 43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 205 (_phy)->def_md_devad, \ 211 (_phy)->def_md_devad, \ 217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy, 239 * bnx2x_check_lfa - This function checks if link reinitialization is required, 251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa() 254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa() [all …]
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/linux/drivers/phy/mediatek/ |
H A D | phy-mtk-dp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * MediaTek DisplayPort PHY driver 13 #include <linux/phy/phy.h> 85 static int mtk_dp_phy_init(struct phy *phy) in mtk_dp_phy_init() argument 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() 97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init() 99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init() 101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init() 103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init() 109 static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts) in mtk_dp_phy_configure() argument [all …]
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/linux/Documentation/devicetree/bindings/display/msm/ |
H A D | dp-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Kuogee Hsieh <quic_khsieh@quicinc.com> 19 - enum: 20 - qcom,sc7180-dp 21 - qcom,sc7280-dp 22 - qcom,sc7280-edp 23 - qcom,sc8180x-dp [all …]
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/linux/drivers/phy/samsung/ |
H A D | phy-exynos-dp-video.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Samsung Exynos SoC series Display Port PHY driver 15 #include <linux/phy/phy.h> 18 #include <linux/soc/samsung/exynos-regs-pmu.h> 29 static int exynos_dp_video_phy_power_on(struct phy *phy) in exynos_dp_video_phy_power_on() argument 31 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_on() 33 /* Disable power isolation on DP-PHY */ in exynos_dp_video_phy_power_on() 34 return regmap_update_bits(state->regs, state->drvdata->phy_ctrl_offset, in exynos_dp_video_phy_power_on() 38 static int exynos_dp_video_phy_power_off(struct phy *phy) in exynos_dp_video_phy_power_off() argument 40 struct exynos_dp_video_phy *state = phy_get_drvdata(phy); in exynos_dp_video_phy_power_off() [all …]
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/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | cdns,mhdp8546.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Swapnil Jakhade <sjakhade@cadence.com> 11 - Yuti Amonkar <yamonkar@cadence.com> 16 - cdns,mhdp8546 17 - ti,j721e-mhdp8546 22 - description: 23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). 25 included in the associated PHY. [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_link_encoder.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 54 SRI(DP_CONFIG, DP, id), \ 55 SRI(DP_DPHY_CNTL, DP, id), \ 56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 58 SRI(DP_DPHY_SYM0, DP, id), \ 59 SRI(DP_DPHY_SYM1, DP, id), \ 60 SRI(DP_DPHY_SYM2, DP, id), \ 61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 62 SRI(DP_LINK_CNTL, DP, id), \ [all …]
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H A D | dce_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 57 enc110->base.ctx 59 enc110->base.ctx->logger 62 (enc110->link_regs->reg) 65 (enc110->aux_regs->reg) 68 (enc110->hpd_regs->reg) 75 * ASIC-dependent, actual values for register programming 91 (reg + enc110->offsets.dig) 94 (reg + enc110->offsets.dp) 127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control() [all …]
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/linux/net/dsa/ |
H A D | port.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright (c) 2017 Savoir-faire Linux Inc. 22 * dsa_port_notify - Notify the switching fabric of changes to a port 23 * @dp: port on which change occurred 25 * @v: event-specific value. 29 * reconfigure themselves for cross-chip operations. Can also be used to 33 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument 35 return dsa_tree_notify(dp->ds->dst, e, v); in dsa_port_notify() 38 static void dsa_port_notify_bridge_fdb_flush(const struct dsa_port *dp, u16 vid) in dsa_port_notify_bridge_fdb_flush() argument 40 struct net_device *brport_dev = dsa_port_to_bridge_port(dp); in dsa_port_notify_bridge_fdb_flush() [all …]
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H A D | port.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 18 bool dsa_port_supports_hwtstamp(struct dsa_port *dp); 21 int dsa_port_set_state(struct dsa_port *dp, u8 state, bool do_fast_age); 22 int dsa_port_set_mst_state(struct dsa_port *dp, 25 int dsa_port_enable_rt(struct dsa_port *dp, struct phy_device *phy); 26 int dsa_port_enable(struct dsa_port *dp, struct phy_device *phy); 27 void dsa_port_disable_rt(struct dsa_port *dp); 28 void dsa_port_disable(struct dsa_port *dp); 29 int dsa_port_bridge_join(struct dsa_port *dp, struct net_device *br, 31 void dsa_port_pre_bridge_leave(struct dsa_port *dp, struct net_device *br); [all …]
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/linux/Documentation/devicetree/bindings/soc/samsung/ |
H A D | exynos-pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 18 - google,gs101-pmu 19 - samsung,exynos3250-pmu 20 - samsung,exynos4210-pmu 21 - samsung,exynos4212-pmu 22 - samsung,exynos4412-pmu [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
H A D | dcn10_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 37 enc10->base.ctx 39 enc10->base.ctx->logger 42 (enc10->link_regs->reg) 46 enc10->link_shift->field_name, enc10->link_mask->field_name 52 * ASIC-dependent, actual values for register programming 98 struct dc_bios *bp = enc10->base.ctx->dc_bios; in link_transmitter_control() 100 result = bp->funcs->transmitter_control(bp, cntl); in link_transmitter_control() 109 /* This register resides in DP back end block; in enable_phy_bypass_mode() 120 /* This register resides in DP back end block; in disable_prbs_symbols() [all …]
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/linux/Documentation/devicetree/bindings/display/samsung/ |
H A D | samsung,exynos5-dp.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Inki Dae <inki.dae@samsung.com> 11 - Seung-Woo Kim <sw0312.kim@samsung.com> 12 - Kyungmin Park <kyungmin.park@samsung.com> 13 - Krzysztof Kozlowski <krzk@kernel.org> 17 const: samsung,exynos5-dp 25 clock-names: [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | samsung,exynos5260-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chanwoo Choi <cw00.choi@samsung.com> 11 - Krzysztof Kozlowski <krzk@kernel.org> 12 - Sylwester Nawrocki <s.nawrocki@samsung.com> 13 - Tomasz Figa <tomasz.figa@gmail.com> 16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching 18 - "fin_pll" - PLL input clock from XXTI [all …]
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/linux/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * Header file for Analogix DP (Display Port) core interface driver. 165 struct phy *phy; member 179 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); 180 void analogix_dp_stop_video(struct analogix_dp_device *dp); 181 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); 182 void analogix_dp_init_analog_param(struct analogix_dp_device *dp); 183 void analogix_dp_init_interrupt(struct analogix_dp_device *dp); 184 void analogix_dp_reset(struct analogix_dp_device *dp); 185 void analogix_dp_swreset(struct analogix_dp_device *dp); [all …]
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/linux/drivers/power/supply/ |
H A D | isp1704_charger.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 * Copyright (C) 2012 - 2013 Pali Rohár <pali@kernel.org> 50 struct usb_phy *phy; member 63 return usb_phy_io_read(isp->phy, reg); in isp1704_read() 68 return usb_phy_io_write(isp->phy, val, reg); in isp1704_write() 73 gpiod_set_value(isp->enable_gpio, on); in isp1704_charger_set_power() 103 /* Enable strong pull-up on DP (1.5K) and reset */ in isp1704_charger_type() 138 /* Clear the DP and DM pull-down bits */ in isp1704_charger_verify() 142 /* Enable strong pull-up on DP (1.5K) and reset */ in isp1704_charger_verify() 149 /* Disable strong pull-up on DP (1.5K) */ in isp1704_charger_verify() [all …]
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/linux/drivers/net/dsa/qca/ |
H A D | qca8k-8xxx.c | 1 // SPDX-License-Identifier: GPL-2.0 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 10 #include <linux/phy.h> 47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo() 49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo() 62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi() 64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi() 75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo() 83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo() 95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi() [all …]
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/linux/Documentation/devicetree/bindings/display/xlnx/ |
H A D | xlnx,zynqmp-dpsub.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 +------------------------------------------------------------+ 15 +--------+ | +----------------+ +-----------+ | 16 | DPDMA | --->| | --> | Video | Video +-------------+ | 17 | 4x vid | | | | | Rendering | -+--> | | | +------+ 18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ [all …]
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