1 /* Copyright 2008-2013 Broadcom Corporation
8  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER			(I2C_WA_RETRY_CNT - 1)
205 		(_phy)->def_md_devad, \
211 		(_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239  * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 	struct bnx2x *bp = params->bp;  in bnx2x_check_lfa()
254 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
257 	/* NOTE: must be first condition checked -  in bnx2x_check_lfa()
261 		DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");  in bnx2x_check_lfa()
262 		REG_WR(bp, params->lfa_base +  in bnx2x_check_lfa()
269 	link_status = REG_RD(bp, params->shmem_base +  in bnx2x_check_lfa()
271 				      port_mb[params->port].link_status));  in bnx2x_check_lfa()
278 	if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)  in bnx2x_check_lfa()
282 	if (params->loopback_mode)  in bnx2x_check_lfa()
286 	if (!params->lfa_base)  in bnx2x_check_lfa()
289 	if (params->num_phys == 3) {  in bnx2x_check_lfa()
298 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
300 	req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);  in bnx2x_check_lfa()
302 		DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",  in bnx2x_check_lfa()
307 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
309 	req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);  in bnx2x_check_lfa()
311 		DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",  in bnx2x_check_lfa()
316 	saved_val = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
318 	req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);  in bnx2x_check_lfa()
320 		DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",  in bnx2x_check_lfa()
326 		cur_speed_cap_mask = REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
330 		if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {  in bnx2x_check_lfa()
331 			DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",  in bnx2x_check_lfa()
333 				       params->speed_cap_mask[cfg_idx]);  in bnx2x_check_lfa()
339 		REG_RD(bp, params->lfa_base +  in bnx2x_check_lfa()
343 	if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {  in bnx2x_check_lfa()
344 		DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",  in bnx2x_check_lfa()
345 			       cur_req_fc_auto_adv, params->req_fc_auto_adv);  in bnx2x_check_lfa()
349 	eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_check_lfa()
351 				     eee_status[params->port]));  in bnx2x_check_lfa()
354 	     (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||  in bnx2x_check_lfa()
356 	     (params->eee_mode & EEE_MODE_ADV_LPI))) {  in bnx2x_check_lfa()
357 		DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,  in bnx2x_check_lfa()
374 		DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);  in bnx2x_get_epio()
391 		DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);  in bnx2x_set_epio()
394 	DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);  in bnx2x_set_epio()
415 		bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);  in bnx2x_set_cfg_pin()
417 		u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;  in bnx2x_set_cfg_pin()
418 		u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;  in bnx2x_set_cfg_pin()
426 		return -EINVAL;  in bnx2x_get_cfg_pin()
428 		bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);  in bnx2x_get_cfg_pin()
430 		u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;  in bnx2x_get_cfg_pin()
431 		u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;  in bnx2x_get_cfg_pin()
443 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e2e3a0_disabled()
445 	DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");  in bnx2x_ets_e2e3a0_disabled()
447 	/* mapping between entry  priority to client number (0,1,2 -debug and  in bnx2x_ets_e2e3a0_disabled()
448 	 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)  in bnx2x_ets_e2e3a0_disabled()
451 	 * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000  in bnx2x_ets_e2e3a0_disabled()
456 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -  in bnx2x_ets_e2e3a0_disabled()
457 	 * COS0 entry, 4 - COS1 entry.  in bnx2x_ets_e2e3a0_disabled()
502 	if (vars->link_up) {  in bnx2x_ets_get_min_w_val_nig()
503 		if (vars->line_speed == SPEED_20000)  in bnx2x_ets_get_min_w_val_nig()
534 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
535 	const u8 port = params->port;  in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
572 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_nig_disabled()
573 	const u8 port = params->port;  in bnx2x_ets_e3b0_nig_disabled()
575 	/* Mapping between entry  priority to client number (0,1,2 -debug and  in bnx2x_ets_e3b0_nig_disabled()
576 	 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -  in bnx2x_ets_e3b0_nig_disabled()
577 	 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by  in bnx2x_ets_e3b0_nig_disabled()
607 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 -  in bnx2x_ets_e3b0_nig_disabled()
608 	 * COS0 entry, 4 - COS1 entry.  in bnx2x_ets_e3b0_nig_disabled()
622 	 * for here is note appropriate.In 2 port mode port0 only COS0-5  in bnx2x_ets_e3b0_nig_disabled()
624 	 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT  in bnx2x_ets_e3b0_nig_disabled()
656 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
659 	const u8 port = params->port;  in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
663 	/* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4  in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
664 	 * port mode port1 has COS0-2 that can be used for WFQ.  in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
688 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_pbf_disabled()
689 	const u8 port = params->port;  in bnx2x_ets_e3b0_pbf_disabled()
695 	/* Mapping between entry  priority to client number 0 - COS0  in bnx2x_ets_e3b0_pbf_disabled()
696 	 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.  in bnx2x_ets_e3b0_pbf_disabled()
697 	 * TODO_ETS - Should be done by reset value or init tool  in bnx2x_ets_e3b0_pbf_disabled()
706 	/* TODO_ETS - Should be done by reset value or init tool */  in bnx2x_ets_e3b0_pbf_disabled()
723 	/* In 2 port mode port0 has COS0-5 that can be used for WFQ.  in bnx2x_ets_e3b0_pbf_disabled()
724 	 * In 4 port mode port1 has COS0-2 that can be used for WFQ.  in bnx2x_ets_e3b0_pbf_disabled()
747 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_disabled()
750 		DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_disabled()
752 		return -EINVAL;  in bnx2x_ets_e3b0_disabled()
770 	struct bnx2x *bp = params->bp;  in bnx2x_ets_disabled()
778 		DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");  in bnx2x_ets_disabled()
779 		return -EINVAL;  in bnx2x_ets_disabled()
795 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_cli_map()
796 	const u8 port = params->port;  in bnx2x_ets_e3b0_cli_map()
834 	/* Calculate and set BW for this COS - use 1 instead of 0 for BW */  in bnx2x_ets_e3b0_set_cos_bw()
863 			return -EINVAL;  in bnx2x_ets_e3b0_set_cos_bw()
869 			return -EINVAL;  in bnx2x_ets_e3b0_set_cos_bw()
875 			return -EINVAL;  in bnx2x_ets_e3b0_set_cos_bw()
897 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_get_total_bw()
903 	for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {  in bnx2x_ets_e3b0_get_total_bw()
904 		if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {  in bnx2x_ets_e3b0_get_total_bw()
906 			if (!ets_params->cos[cos_idx].params.bw_params.bw) {  in bnx2x_ets_e3b0_get_total_bw()
907 				DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"  in bnx2x_ets_e3b0_get_total_bw()
912 				ets_params->cos[cos_idx].params.bw_params.bw  in bnx2x_ets_e3b0_get_total_bw()
916 				ets_params->cos[cos_idx].params.bw_params.bw;  in bnx2x_ets_e3b0_get_total_bw()
923 			DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_get_total_bw()
925 			return -EINVAL;  in bnx2x_ets_e3b0_get_total_bw()
927 		DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_get_total_bw()
957 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
958 	const u8 port = params->port;  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
963 		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
965 		return -EINVAL;  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
969 		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
972 		return -EINVAL;  in bnx2x_ets_e3b0_sp_pri_to_cos_set()
1038 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1040 	const u8 port = params->port;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1049 	u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1055 				DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1058 				return -EINVAL;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1069 				DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1073 				return -EINVAL;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1098 		DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1100 		return -EINVAL;  in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1132 	struct bnx2x *bp = params->bp;  in bnx2x_ets_e3b0_config()
1134 	const u8 port = params->port;  in bnx2x_ets_e3b0_config()
1146 		DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_config()
1148 		return -EINVAL;  in bnx2x_ets_e3b0_config()
1151 	if ((ets_params->num_of_cos > max_num_of_cos)) {  in bnx2x_ets_e3b0_config()
1152 		DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "  in bnx2x_ets_e3b0_config()
1154 		return -EINVAL;  in bnx2x_ets_e3b0_config()
1164 		DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_config()
1166 		return -EINVAL;  in bnx2x_ets_e3b0_config()
1176 	for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {  in bnx2x_ets_e3b0_config()
1177 		if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {  in bnx2x_ets_e3b0_config()
1185 				ets_params->cos[cos_entry].params.bw_params.bw,  in bnx2x_ets_e3b0_config()
1188 			ets_params->cos[cos_entry].state){  in bnx2x_ets_e3b0_config()
1194 				ets_params->cos[cos_entry].params.sp_params.pri,  in bnx2x_ets_e3b0_config()
1198 			DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_config()
1200 			return -EINVAL;  in bnx2x_ets_e3b0_config()
1203 			DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_config()
1214 		DP(NETIF_MSG_LINK,  in bnx2x_ets_e3b0_config()
1225 		DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");  in bnx2x_ets_e3b0_config()
1233 	struct bnx2x *bp = params->bp;  in bnx2x_ets_bw_limit_common()
1234 	DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");  in bnx2x_ets_bw_limit_common()
1244 	 *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010  in bnx2x_ets_bw_limit_common()
1259 	 * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0  in bnx2x_ets_bw_limit_common()
1260 	 * entry, 4 - COS1 entry.  in bnx2x_ets_bw_limit_common()
1278 	struct bnx2x *bp = params->bp;  in bnx2x_ets_bw_limit()
1283 	DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");  in bnx2x_ets_bw_limit()
1288 		DP(NETIF_MSG_LINK, "Total BW can't be zero\n");  in bnx2x_ets_bw_limit()
1309 	struct bnx2x *bp = params->bp;  in bnx2x_ets_strict()
1312 	DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");  in bnx2x_ets_strict()
1314 	 * as strict.  Bits 0,1,2 - debug and management entries,  in bnx2x_ets_strict()
1315 	 * 3 - COS0 entry, 4 - COS1 entry.  in bnx2x_ets_strict()
1333 	/* Mapping between entry  priority to client number (0,1,2 -debug and  in bnx2x_ets_strict()
1334 	 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)  in bnx2x_ets_strict()
1337 	 * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000  in bnx2x_ets_strict()
1338 	 * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000  in bnx2x_ets_strict()
1353 	struct bnx2x *bp = params->bp;  in bnx2x_update_pfc_xmac()
1358 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_update_pfc_xmac()
1366 	if (!(params->feature_config_flags &  in bnx2x_update_pfc_xmac()
1369 		/* RX flow control - Process pause frame in receive direction  in bnx2x_update_pfc_xmac()
1371 		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)  in bnx2x_update_pfc_xmac()
1374 		/* TX flow control - Send pause packet when buffer is full */  in bnx2x_update_pfc_xmac()
1375 		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)  in bnx2x_update_pfc_xmac()
1399 	       ((params->mac_addr[2] << 24) |  in bnx2x_update_pfc_xmac()
1400 		(params->mac_addr[3] << 16) |  in bnx2x_update_pfc_xmac()
1401 		(params->mac_addr[4] << 8) |  in bnx2x_update_pfc_xmac()
1402 		(params->mac_addr[5])));  in bnx2x_update_pfc_xmac()
1404 	       ((params->mac_addr[0] << 8) |  in bnx2x_update_pfc_xmac()
1405 		(params->mac_addr[1])));  in bnx2x_update_pfc_xmac()
1437 	DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",  in bnx2x_set_mdio_clk()
1447 	/* Set mdio clock per phy */  in bnx2x_set_mdio_emac_per_phy()
1448 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in bnx2x_set_mdio_emac_per_phy()
1450 		bnx2x_set_mdio_clk(bp, params->chip_id,  in bnx2x_set_mdio_emac_per_phy()
1451 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
1457 	/* Check 4-port override enabled */  in bnx2x_is_4_port_mode()
1460 		/* Return 4-port mode override value */  in bnx2x_is_4_port_mode()
1463 	/* Return 4-port mode from input pin */  in bnx2x_is_4_port_mode()
1471 	struct bnx2x *bp = params->bp;  in bnx2x_emac_init()
1472 	u8 port = params->port;  in bnx2x_emac_init()
1483 	/* init emac - use read-modify-write */  in bnx2x_emac_init()
1491 		DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);  in bnx2x_emac_init()
1493 			DP(NETIF_MSG_LINK, "EMAC timeout!\n");  in bnx2x_emac_init()
1496 		timeout--;  in bnx2x_emac_init()
1501 	val = ((params->mac_addr[0] << 8) |  in bnx2x_emac_init()
1502 		params->mac_addr[1]);  in bnx2x_emac_init()
1505 	val = ((params->mac_addr[2] << 24) |  in bnx2x_emac_init()
1506 	       (params->mac_addr[3] << 16) |  in bnx2x_emac_init()
1507 	       (params->mac_addr[4] << 8) |  in bnx2x_emac_init()
1508 		params->mac_addr[5]);  in bnx2x_emac_init()
1516 	struct bnx2x *bp = params->bp;  in bnx2x_set_xumac_nig()
1518 	REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,  in bnx2x_set_xumac_nig()
1520 	REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,  in bnx2x_set_xumac_nig()
1522 	REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :  in bnx2x_set_xumac_nig()
1528 	u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;  in bnx2x_set_umac_rxtx()
1530 	struct bnx2x *bp = params->bp;  in bnx2x_set_umac_rxtx()
1532 		   (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))  in bnx2x_set_umac_rxtx()
1549 	u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;  in bnx2x_umac_enable()
1550 	struct bnx2x *bp = params->bp;  in bnx2x_umac_enable()
1553 	       (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));  in bnx2x_umac_enable()
1557 	       (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));  in bnx2x_umac_enable()
1559 	DP(NETIF_MSG_LINK, "enabling UMAC\n");  in bnx2x_umac_enable()
1562 	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);  in bnx2x_umac_enable()
1568 	switch (vars->line_speed) {  in bnx2x_umac_enable()
1582 		DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",  in bnx2x_umac_enable()
1583 			       vars->line_speed);  in bnx2x_umac_enable()
1586 	if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_umac_enable()
1589 	if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))  in bnx2x_umac_enable()
1592 	if (vars->duplex == DUPLEX_HALF)  in bnx2x_umac_enable()
1599 	if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {  in bnx2x_umac_enable()
1600 		DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");  in bnx2x_umac_enable()
1610 	       ((params->mac_addr[2] << 24) |  in bnx2x_umac_enable()
1611 		(params->mac_addr[3] << 16) |  in bnx2x_umac_enable()
1612 		(params->mac_addr[4] << 8) |  in bnx2x_umac_enable()
1613 		(params->mac_addr[5])));  in bnx2x_umac_enable()
1615 	       ((params->mac_addr[0] << 8) |  in bnx2x_umac_enable()
1616 		(params->mac_addr[1])));  in bnx2x_umac_enable()
1633 	/* Maximum Frame Length (RW). Defines a 14-Bit maximum frame  in bnx2x_umac_enable()
1638 			    ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);  in bnx2x_umac_enable()
1639 	vars->mac_type = MAC_TYPE_UMAC;  in bnx2x_umac_enable()
1646 	struct bnx2x *bp = params->bp;  in bnx2x_xmac_init()
1649 	/* In 4-port mode, need to set the mode only once, so if XMAC is  in bnx2x_xmac_init()
1661 		DP(NETIF_MSG_LINK,  in bnx2x_xmac_init()
1662 		   "XMAC already out of reset in 4-port mode\n");  in bnx2x_xmac_init()
1674 		DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");  in bnx2x_xmac_init()
1685 			DP(NETIF_MSG_LINK,  in bnx2x_xmac_init()
1690 			DP(NETIF_MSG_LINK,  in bnx2x_xmac_init()
1708 	u8 port = params->port;  in bnx2x_set_xmac_rxtx()
1709 	struct bnx2x *bp = params->bp;  in bnx2x_set_xmac_rxtx()
1724 		DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);  in bnx2x_set_xmac_rxtx()
1738 	struct bnx2x *bp = params->bp;  in bnx2x_xmac_enable()
1739 	DP(NETIF_MSG_LINK, "enabling XMAC\n");  in bnx2x_xmac_enable()
1741 	xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_xmac_enable()
1743 	bnx2x_xmac_init(params, vars->line_speed);  in bnx2x_xmac_enable()
1752 	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);  in bnx2x_xmac_enable()
1757 	if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {  in bnx2x_xmac_enable()
1775 	if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {  in bnx2x_xmac_enable()
1776 		DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");  in bnx2x_xmac_enable()
1786 	/* Set MAC in XLGMII mode for dual-mode */  in bnx2x_xmac_enable()
1787 	if ((vars->line_speed == SPEED_20000) &&  in bnx2x_xmac_enable()
1788 	    (params->phy[INT_PHY].supported &  in bnx2x_xmac_enable()
1797 			    ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);  in bnx2x_xmac_enable()
1799 	vars->mac_type = MAC_TYPE_XMAC;  in bnx2x_xmac_enable()
1807 	struct bnx2x *bp = params->bp;  in bnx2x_emac_enable()
1808 	u8 port = params->port;  in bnx2x_emac_enable()
1812 	DP(NETIF_MSG_LINK, "enabling EMAC\n");  in bnx2x_emac_enable()
1822 	if (vars->phy_flags & PHY_XGXS_FLAG) {  in bnx2x_emac_enable()
1823 		u32 ser_lane = ((params->lane_config &  in bnx2x_emac_enable()
1827 		DP(NETIF_MSG_LINK, "XGXS\n");  in bnx2x_emac_enable()
1828 		/* select the master lanes (out of 0-3) */  in bnx2x_emac_enable()
1834 		DP(NETIF_MSG_LINK, "SerDes\n");  in bnx2x_emac_enable()
1851 	if (!(params->feature_config_flags &  in bnx2x_emac_enable()
1853 		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)  in bnx2x_emac_enable()
1858 		if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)  in bnx2x_emac_enable()
1879 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {  in bnx2x_emac_enable()
1880 		DP(NETIF_MSG_LINK, "PFC is enabled\n");  in bnx2x_emac_enable()
1923 	if ((params->feature_config_flags &  in bnx2x_emac_enable()
1925 	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_emac_enable()
1933 	vars->mac_type = MAC_TYPE_EMAC;  in bnx2x_emac_enable()
1941 	struct bnx2x *bp = params->bp;  in bnx2x_update_pfc_bmac1()
1942 	u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :  in bnx2x_update_pfc_bmac1()
1946 	if ((!(params->feature_config_flags &  in bnx2x_update_pfc_bmac1()
1948 		(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))  in bnx2x_update_pfc_bmac1()
1957 	if (!(params->feature_config_flags &  in bnx2x_update_pfc_bmac1()
1959 		(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_update_pfc_bmac1()
1974 	struct bnx2x *bp = params->bp;  in bnx2x_update_pfc_bmac2()
1975 	u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :  in bnx2x_update_pfc_bmac2()
1979 	if ((!(params->feature_config_flags &  in bnx2x_update_pfc_bmac2()
1981 		(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))  in bnx2x_update_pfc_bmac2()
1991 	if (!(params->feature_config_flags &  in bnx2x_update_pfc_bmac2()
1993 	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_update_pfc_bmac2()
1999 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {  in bnx2x_update_pfc_bmac2()
2000 		DP(NETIF_MSG_LINK, "PFC is enabled\n");  in bnx2x_update_pfc_bmac2()
2014 		DP(NETIF_MSG_LINK, "PFC is disabled\n");  in bnx2x_update_pfc_bmac2()
2023 	 * re-sending of PP packets amd enable automatic re-send of  in bnx2x_update_pfc_bmac2()
2024 	 * Per-Priroity Packet as long as pp_gen is asserted and  in bnx2x_update_pfc_bmac2()
2028 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)  in bnx2x_update_pfc_bmac2()
2029 		val |= (1<<16); /* enable automatic re-send */  in bnx2x_update_pfc_bmac2()
2040 		DP(NETIF_MSG_LINK, "enable bmac loopback\n");  in bnx2x_update_pfc_bmac2()
2043 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)  in bnx2x_update_pfc_bmac2()
2080 		return -EINVAL;  in bnx2x_pfc_nig_rx_priority_mask()
2085 		return -EINVAL;  in bnx2x_pfc_nig_rx_priority_mask()
2090 		return -EINVAL;  in bnx2x_pfc_nig_rx_priority_mask()
2101 	struct bnx2x *bp = params->bp;  in bnx2x_update_mng()
2103 	REG_WR(bp, params->shmem_base +  in bnx2x_update_mng()
2105 			port_mb[params->port].link_status), link_status);  in bnx2x_update_mng()
2110 	struct bnx2x *bp = params->bp;  in bnx2x_update_link_attr()
2113 		REG_WR(bp, params->shmem2_base +  in bnx2x_update_link_attr()
2115 				link_attr_sync[params->port]), link_attr);  in bnx2x_update_link_attr()
2125 	struct bnx2x *bp = params->bp;  in bnx2x_update_pfc_nig()
2126 	u8 port = params->port;  in bnx2x_update_pfc_nig()
2128 	int set_pfc = params->feature_config_flags &  in bnx2x_update_pfc_nig()
2130 	DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");  in bnx2x_update_pfc_nig()
2155 			llfc_out_en = nig_params->llfc_out_en;  in bnx2x_update_pfc_nig()
2156 			llfc_enable = nig_params->llfc_enable;  in bnx2x_update_pfc_nig()
2157 			pause_enable = nig_params->pause_enable;  in bnx2x_update_pfc_nig()
2158 		} else  /* Default non PFC mode - PAUSE */  in bnx2x_update_pfc_nig()
2195 		pkt_priority_to_cos = nig_params->pkt_priority_to_cos;  in bnx2x_update_pfc_nig()
2197 		for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)  in bnx2x_update_pfc_nig()
2199 		nig_params->rx_cos_priority_mask[i], port);  in bnx2x_update_pfc_nig()
2203 		       nig_params->llfc_high_priority_classes);  in bnx2x_update_pfc_nig()
2207 		       nig_params->llfc_low_priority_classes);  in bnx2x_update_pfc_nig()
2223 	struct bnx2x *bp = params->bp;  in bnx2x_update_pfc()
2224 	u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);  in bnx2x_update_pfc()
2226 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)  in bnx2x_update_pfc()
2227 		vars->link_status |= LINK_STATUS_PFC_ENABLED;  in bnx2x_update_pfc()
2229 		vars->link_status &= ~LINK_STATUS_PFC_ENABLED;  in bnx2x_update_pfc()
2231 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_update_pfc()
2236 	if (!vars->link_up)  in bnx2x_update_pfc()
2239 	DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");  in bnx2x_update_pfc()
2242 		if (vars->mac_type == MAC_TYPE_XMAC)  in bnx2x_update_pfc()
2247 		     (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))  in bnx2x_update_pfc()
2249 			DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");  in bnx2x_update_pfc()
2259 		if ((params->feature_config_flags &  in bnx2x_update_pfc()
2261 		    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_update_pfc()
2263 		REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);  in bnx2x_update_pfc()
2272 	struct bnx2x *bp = params->bp;  in bnx2x_bmac1_enable()
2273 	u8 port = params->port;  in bnx2x_bmac1_enable()
2279 	DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");  in bnx2x_bmac1_enable()
2288 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac1_enable()
2289 		       (params->mac_addr[3] << 16) |  in bnx2x_bmac1_enable()
2290 		       (params->mac_addr[4] << 8) |  in bnx2x_bmac1_enable()
2291 			params->mac_addr[5]);  in bnx2x_bmac1_enable()
2292 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac1_enable()
2293 			params->mac_addr[1]);  in bnx2x_bmac1_enable()
2300 		DP(NETIF_MSG_LINK, "enable bmac loopback\n");  in bnx2x_bmac1_enable()
2336 	struct bnx2x *bp = params->bp;  in bnx2x_bmac2_enable()
2337 	u8 port = params->port;  in bnx2x_bmac2_enable()
2342 	DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");  in bnx2x_bmac2_enable()
2349 	/* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */  in bnx2x_bmac2_enable()
2358 	wb_data[0] = ((params->mac_addr[2] << 24) |  in bnx2x_bmac2_enable()
2359 		       (params->mac_addr[3] << 16) |  in bnx2x_bmac2_enable()
2360 		       (params->mac_addr[4] << 8) |  in bnx2x_bmac2_enable()
2361 			params->mac_addr[5]);  in bnx2x_bmac2_enable()
2362 	wb_data[1] = ((params->mac_addr[0] << 8) |  in bnx2x_bmac2_enable()
2363 			params->mac_addr[1]);  in bnx2x_bmac2_enable()
2388 	wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2;  in bnx2x_bmac2_enable()
2402 	u8 port = params->port;  in bnx2x_bmac_enable()
2403 	struct bnx2x *bp = params->bp;  in bnx2x_bmac_enable()
2427 	if ((params->feature_config_flags &  in bnx2x_bmac_enable()
2429 	    (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))  in bnx2x_bmac_enable()
2438 	vars->mac_type = MAC_TYPE_BMAC;  in bnx2x_bmac_enable()
2471 	struct bnx2x *bp = params->bp;  in bnx2x_pbf_update()
2472 	u8 port = params->port;  in bnx2x_pbf_update()
2482 	DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);  in bnx2x_pbf_update()
2487 		count--;  in bnx2x_pbf_update()
2491 		DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",  in bnx2x_pbf_update()
2493 		return -EINVAL;  in bnx2x_pbf_update()
2505 		init_crd = 778;		/* (800-18-4) */  in bnx2x_pbf_update()
2516 			init_crd = thresh + 553 - 22;  in bnx2x_pbf_update()
2519 			DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",  in bnx2x_pbf_update()
2521 			return -EINVAL;  in bnx2x_pbf_update()
2525 	DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",  in bnx2x_pbf_update()
2539  * bnx2x_get_emac_base - retrive emac base address
2547  * phy has a default access mode, which could also be overridden
2549  * default phy configuration, or the nvram overrun
2589 				       struct bnx2x_phy *phy,  in bnx2x_cl22_write()  argument
2596 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_write()
2597 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_write()
2601 	tmp = ((phy->addr << 21) | (reg << 16) | val |  in bnx2x_cl22_write()
2604 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl22_write()
2609 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_write()
2616 		DP(NETIF_MSG_LINK, "write phy register failed\n");  in bnx2x_cl22_write()
2617 		rc = -EFAULT;  in bnx2x_cl22_write()
2619 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_write()
2624 				      struct bnx2x_phy *phy,  in bnx2x_cl22_read()  argument
2632 	mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);  in bnx2x_cl22_read()
2633 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,  in bnx2x_cl22_read()
2637 	val = ((phy->addr << 21) | (reg << 16) |  in bnx2x_cl22_read()
2640 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl22_read()
2645 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl22_read()
2653 		DP(NETIF_MSG_LINK, "read phy register failed\n");  in bnx2x_cl22_read()
2656 		rc = -EFAULT;  in bnx2x_cl22_read()
2658 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);  in bnx2x_cl22_read()
2665 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,  in bnx2x_cl45_read()  argument
2672 	if (phy->flags & FLAGS_MDC_MDIO_WA_G) {  in bnx2x_cl45_read()
2675 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_read()
2678 	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)  in bnx2x_cl45_read()
2679 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2682 	val = ((phy->addr << 21) | (devad << 16) | reg |  in bnx2x_cl45_read()
2685 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2690 		val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_read()
2697 		DP(NETIF_MSG_LINK, "read phy register failed\n");  in bnx2x_cl45_read()
2698 		netdev_err(bp->dev,  "MDC/MDIO access timeout\n");  in bnx2x_cl45_read()
2700 		rc = -EFAULT;  in bnx2x_cl45_read()
2703 		val = ((phy->addr << 21) | (devad << 16) |  in bnx2x_cl45_read()
2706 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);  in bnx2x_cl45_read()
2711 			val = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_read()
2719 			DP(NETIF_MSG_LINK, "read phy register failed\n");  in bnx2x_cl45_read()
2720 			netdev_err(bp->dev,  "MDC/MDIO access timeout\n");  in bnx2x_cl45_read()
2722 			rc = -EFAULT;  in bnx2x_cl45_read()
2726 	if (phy->flags & FLAGS_MDC_MDIO_WA) {  in bnx2x_cl45_read()
2727 		phy->flags ^= FLAGS_DUMMY_READ;  in bnx2x_cl45_read()
2728 		if (phy->flags & FLAGS_DUMMY_READ) {  in bnx2x_cl45_read()
2730 			bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);  in bnx2x_cl45_read()
2734 	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)  in bnx2x_cl45_read()
2735 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_read()
2740 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,  in bnx2x_cl45_write()  argument
2747 	if (phy->flags & FLAGS_MDC_MDIO_WA_G) {  in bnx2x_cl45_write()
2750 		bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);  in bnx2x_cl45_write()
2753 	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)  in bnx2x_cl45_write()
2754 		bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2758 	tmp = ((phy->addr << 21) | (devad << 16) | reg |  in bnx2x_cl45_write()
2761 	REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2766 		tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);  in bnx2x_cl45_write()
2773 		DP(NETIF_MSG_LINK, "write phy register failed\n");  in bnx2x_cl45_write()
2774 		netdev_err(bp->dev,  "MDC/MDIO access timeout\n");  in bnx2x_cl45_write()
2775 		rc = -EFAULT;  in bnx2x_cl45_write()
2778 		tmp = ((phy->addr << 21) | (devad << 16) | val |  in bnx2x_cl45_write()
2781 		REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);  in bnx2x_cl45_write()
2786 			tmp = REG_RD(bp, phy->mdio_ctrl +  in bnx2x_cl45_write()
2794 			DP(NETIF_MSG_LINK, "write phy register failed\n");  in bnx2x_cl45_write()
2795 			netdev_err(bp->dev,  "MDC/MDIO access timeout\n");  in bnx2x_cl45_write()
2796 			rc = -EFAULT;  in bnx2x_cl45_write()
2800 	if (phy->flags & FLAGS_MDC_MDIO_WA) {  in bnx2x_cl45_write()
2801 		phy->flags ^= FLAGS_DUMMY_READ;  in bnx2x_cl45_write()
2802 		if (phy->flags & FLAGS_DUMMY_READ) {  in bnx2x_cl45_write()
2804 			bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);  in bnx2x_cl45_write()
2807 	if (phy->flags & FLAGS_MDC_MDIO_WA_B0)  in bnx2x_cl45_write()
2808 		bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,  in bnx2x_cl45_write()
2818 	struct bnx2x *bp = params->bp;  in bnx2x_eee_has_cap()
2820 	if (REG_RD(bp, params->shmem2_base) <=  in bnx2x_eee_has_cap()
2821 		   offsetof(struct shmem2_region, eee_status[params->port]))  in bnx2x_eee_has_cap()
2870 	struct bnx2x *bp = params->bp;  in bnx2x_eee_calc_timer()
2872 	if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {  in bnx2x_eee_calc_timer()
2873 		if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {  in bnx2x_eee_calc_timer()
2874 			/* time value in eee_mode --> used directly*/  in bnx2x_eee_calc_timer()
2875 			eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;  in bnx2x_eee_calc_timer()
2877 			/* hsi value in eee_mode --> time */  in bnx2x_eee_calc_timer()
2878 			if (bnx2x_eee_nvram_to_time(params->eee_mode &  in bnx2x_eee_calc_timer()
2884 		/* hsi values in nvram --> time*/  in bnx2x_eee_calc_timer()
2885 		eee_mode = ((REG_RD(bp, params->shmem_base +  in bnx2x_eee_calc_timer()
2887 				    port_feature_config[params->port].  in bnx2x_eee_calc_timer()
2903 	struct bnx2x *bp = params->bp;  in bnx2x_eee_set_timers()
2908 		REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),  in bnx2x_eee_set_timers()
2910 	} else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&  in bnx2x_eee_set_timers()
2911 		   (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&  in bnx2x_eee_set_timers()
2912 		   (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {  in bnx2x_eee_set_timers()
2913 		DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");  in bnx2x_eee_set_timers()
2914 		return -EINVAL;  in bnx2x_eee_set_timers()
2917 	vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);  in bnx2x_eee_set_timers()
2918 	if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {  in bnx2x_eee_set_timers()
2919 		/* eee_idle in 1u --> eee_status in 16u */  in bnx2x_eee_set_timers()
2921 		vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |  in bnx2x_eee_set_timers()
2925 			return -EINVAL;  in bnx2x_eee_set_timers()
2926 		vars->eee_status |= eee_mode;  in bnx2x_eee_set_timers()
2935 	vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;  in bnx2x_eee_initial_config()
2937 	/* Propagate params' bits --> vars (for migration exposure) */  in bnx2x_eee_initial_config()
2938 	if (params->eee_mode & EEE_MODE_ENABLE_LPI)  in bnx2x_eee_initial_config()
2939 		vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;  in bnx2x_eee_initial_config()
2941 		vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;  in bnx2x_eee_initial_config()
2943 	if (params->eee_mode & EEE_MODE_ADV_LPI)  in bnx2x_eee_initial_config()
2944 		vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;  in bnx2x_eee_initial_config()
2946 		vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;  in bnx2x_eee_initial_config()
2951 static int bnx2x_eee_disable(struct bnx2x_phy *phy,  in bnx2x_eee_disable()  argument
2955 	struct bnx2x *bp = params->bp;  in bnx2x_eee_disable()
2958 	REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);  in bnx2x_eee_disable()
2960 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);  in bnx2x_eee_disable()
2962 	vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;  in bnx2x_eee_disable()
2967 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,  in bnx2x_eee_advertise()  argument
2971 	struct bnx2x *bp = params->bp;  in bnx2x_eee_advertise()
2975 	REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);  in bnx2x_eee_advertise()
2978 		DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");  in bnx2x_eee_advertise()
2982 		DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");  in bnx2x_eee_advertise()
2986 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);  in bnx2x_eee_advertise()
2988 	vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;  in bnx2x_eee_advertise()
2989 	vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);  in bnx2x_eee_advertise()
2996 	struct bnx2x *bp = params->bp;  in bnx2x_update_mng_eee()
2999 		REG_WR(bp, params->shmem2_base +  in bnx2x_update_mng_eee()
3001 				eee_status[params->port]), eee_status);  in bnx2x_update_mng_eee()
3004 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,  in bnx2x_eee_an_resolve()  argument
3008 	struct bnx2x *bp = params->bp;  in bnx2x_eee_an_resolve()
3013 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);  in bnx2x_eee_an_resolve()
3014 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);  in bnx2x_eee_an_resolve()
3019 			if (vars->line_speed == SPEED_100)  in bnx2x_eee_an_resolve()
3021 			DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");  in bnx2x_eee_an_resolve()
3027 			if (vars->line_speed == SPEED_1000)  in bnx2x_eee_an_resolve()
3029 			DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");  in bnx2x_eee_an_resolve()
3035 			if (vars->line_speed == SPEED_10000)  in bnx2x_eee_an_resolve()
3037 			DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");  in bnx2x_eee_an_resolve()
3041 	vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;  in bnx2x_eee_an_resolve()
3042 	vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);  in bnx2x_eee_an_resolve()
3045 		DP(NETIF_MSG_LINK, "EEE is active\n");  in bnx2x_eee_an_resolve()
3046 		vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;  in bnx2x_eee_an_resolve()
3059 	struct bnx2x *bp = params->bp;  in bnx2x_bsc_module_sel()
3060 	u8 port = params->port;  in bnx2x_bsc_module_sel()
3062 	board_cfg = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3070 	sfp_ctrl = REG_RD(bp, params->shmem_base +  in bnx2x_bsc_module_sel()
3075 	DP(NETIF_MSG_LINK, "Setting BSC switch\n");  in bnx2x_bsc_module_sel()
3093 		DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",  in bnx2x_bsc_read()
3095 		return -EINVAL;  in bnx2x_bsc_read()
3099 	xfer_cnt = 16 - lc_addr;  in bnx2x_bsc_read()
3121 		delta = ktime_get_ns() - t0;  in bnx2x_bsc_read()
3123 			DP(NETIF_MSG_LINK, "wr 0 byte timed out after %Lu ns\n",  in bnx2x_bsc_read()
3125 			rc = -EFAULT;  in bnx2x_bsc_read()
3131 	if (rc == -EFAULT)  in bnx2x_bsc_read()
3146 		delta = ktime_get_ns() - t0;  in bnx2x_bsc_read()
3148 			DP(NETIF_MSG_LINK, "rd op timed out after %Lu ns\n",  in bnx2x_bsc_read()
3150 			rc = -EFAULT;  in bnx2x_bsc_read()
3156 	if (rc == -EFAULT)  in bnx2x_bsc_read()
3171 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,  in bnx2x_cl45_read_or_write()  argument
3175 	bnx2x_cl45_read(bp, phy, devad, reg, &val);  in bnx2x_cl45_read_or_write()
3176 	bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);  in bnx2x_cl45_read_or_write()
3180 				      struct bnx2x_phy *phy,  in bnx2x_cl45_read_and_write()  argument
3184 	bnx2x_cl45_read(bp, phy, devad, reg, &val);  in bnx2x_cl45_read_and_write()
3185 	bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);  in bnx2x_cl45_read_and_write()
3192 	/* Probe for the phy according to the given phy_addr, and execute  in bnx2x_phy_read()
3195 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in bnx2x_phy_read()
3196 		if (params->phy[phy_index].addr == phy_addr) {  in bnx2x_phy_read()
3197 			return bnx2x_cl45_read(params->bp,  in bnx2x_phy_read()
3198 					       &params->phy[phy_index], devad,  in bnx2x_phy_read()
3202 	return -EINVAL;  in bnx2x_phy_read()
3209 	/* Probe for the phy according to the given phy_addr, and execute  in bnx2x_phy_write()
3212 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in bnx2x_phy_write()
3213 		if (params->phy[phy_index].addr == phy_addr) {  in bnx2x_phy_write()
3214 			return bnx2x_cl45_write(params->bp,  in bnx2x_phy_write()
3215 						&params->phy[phy_index], devad,  in bnx2x_phy_write()
3219 	return -EINVAL;  in bnx2x_phy_write()
3221 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,  in bnx2x_get_warpcore_lane()  argument
3225 	struct bnx2x *bp = params->bp;  in bnx2x_get_warpcore_lane()
3230 	port = params->port;  in bnx2x_get_warpcore_lane()
3256 	} else { /* Two port mode - no port swap */  in bnx2x_get_warpcore_lane()
3276 			      struct bnx2x_phy *phy)  in bnx2x_set_aer_mmd()  argument
3280 	struct bnx2x *bp = params->bp;  in bnx2x_set_aer_mmd()
3281 	ser_lane = ((params->lane_config &  in bnx2x_set_aer_mmd()
3285 	offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?  in bnx2x_set_aer_mmd()
3286 		(phy->addr + ser_lane) : 0;  in bnx2x_set_aer_mmd()
3289 		aer_val = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_set_aer_mmd()
3290 		/* In Dual-lane mode, two lanes are joined together,  in bnx2x_set_aer_mmd()
3296 		if (phy->flags & FLAGS_WC_DUAL_MODE)  in bnx2x_set_aer_mmd()
3299 		aer_val = 0x3800 + offset - 1;  in bnx2x_set_aer_mmd()
3303 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_set_aer_mmd()
3309 /*			Internal phy section			  */
3330 	DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");  in bnx2x_serdes_deassert()
3345 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,  in bnx2x_xgxs_specific_func()  argument
3349 	struct bnx2x *bp = params->bp;  in bnx2x_xgxs_specific_func()
3353 		REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);  in bnx2x_xgxs_specific_func()
3354 		REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,  in bnx2x_xgxs_specific_func()
3355 		       phy->def_md_devad);  in bnx2x_xgxs_specific_func()
3362 	struct bnx2x *bp = params->bp;  in bnx2x_xgxs_deassert()
3365 	DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");  in bnx2x_xgxs_deassert()
3366 	port = params->port;  in bnx2x_xgxs_deassert()
3374 	bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,  in bnx2x_xgxs_deassert()
3378 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,  in bnx2x_calc_ieee_aneg_adv()  argument
3381 	struct bnx2x *bp = params->bp;  in bnx2x_calc_ieee_aneg_adv()
3384 	 * 28B-3 of the 802.3ab-1999 spec  in bnx2x_calc_ieee_aneg_adv()
3387 	switch (phy->req_flow_ctrl) {  in bnx2x_calc_ieee_aneg_adv()
3389 		switch (params->req_fc_auto_adv) {  in bnx2x_calc_ieee_aneg_adv()
3416 	DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);  in bnx2x_calc_ieee_aneg_adv()
3422 	struct bnx2x *bp = params->bp;  in set_phy_vars()
3424 	u8 phy_config_swapped = params->multi_phy_config &  in set_phy_vars()
3426 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in set_phy_vars()
3436 		params->phy[actual_phy_idx].req_flow_ctrl =  in set_phy_vars()
3437 			params->req_flow_ctrl[link_cfg_idx];  in set_phy_vars()
3439 		params->phy[actual_phy_idx].req_line_speed =  in set_phy_vars()
3440 			params->req_line_speed[link_cfg_idx];  in set_phy_vars()
3442 		params->phy[actual_phy_idx].speed_cap_mask =  in set_phy_vars()
3443 			params->speed_cap_mask[link_cfg_idx];  in set_phy_vars()
3445 		params->phy[actual_phy_idx].req_duplex =  in set_phy_vars()
3446 			params->req_duplex[link_cfg_idx];  in set_phy_vars()
3448 		if (params->req_line_speed[link_cfg_idx] ==  in set_phy_vars()
3450 			vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;  in set_phy_vars()
3452 		DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"  in set_phy_vars()
3454 			   params->phy[actual_phy_idx].req_flow_ctrl,  in set_phy_vars()
3455 			   params->phy[actual_phy_idx].req_line_speed,  in set_phy_vars()
3456 			   params->phy[actual_phy_idx].speed_cap_mask);  in set_phy_vars()
3461 				    struct bnx2x_phy *phy,  in bnx2x_ext_phy_set_pause()  argument
3465 	struct bnx2x *bp = params->bp;  in bnx2x_ext_phy_set_pause()
3467 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);  in bnx2x_ext_phy_set_pause()
3471 	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */  in bnx2x_ext_phy_set_pause()
3472 	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in bnx2x_ext_phy_set_pause()
3473 	if ((vars->ieee_fc &  in bnx2x_ext_phy_set_pause()
3478 	if ((vars->ieee_fc &  in bnx2x_ext_phy_set_pause()
3483 	DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);  in bnx2x_ext_phy_set_pause()
3484 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);  in bnx2x_ext_phy_set_pause()
3487 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,  in bnx2x_pause_resolve()  argument
3492 	struct bnx2x *bp = params->bp;  in bnx2x_pause_resolve()
3496 		DP(NETIF_MSG_LINK, "Flow Control: TX only\n");  in bnx2x_pause_resolve()
3497 		vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;  in bnx2x_pause_resolve()
3501 		DP(NETIF_MSG_LINK, "Flow Control: RX only\n");  in bnx2x_pause_resolve()
3502 		vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;  in bnx2x_pause_resolve()
3513 		if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {  in bnx2x_pause_resolve()
3514 			DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");  in bnx2x_pause_resolve()
3515 			vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;  in bnx2x_pause_resolve()
3517 			DP(NETIF_MSG_LINK, "Flow Control: RX only\n");  in bnx2x_pause_resolve()
3518 			vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;  in bnx2x_pause_resolve()
3523 		DP(NETIF_MSG_LINK, "Flow Control: None\n");  in bnx2x_pause_resolve()
3524 		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_pause_resolve()
3528 		vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;  in bnx2x_pause_resolve()
3530 		vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;  in bnx2x_pause_resolve()
3534 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,  in bnx2x_ext_phy_update_adv_fc()  argument
3541 	struct bnx2x *bp = params->bp;  in bnx2x_ext_phy_update_adv_fc()
3542 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {  in bnx2x_ext_phy_update_adv_fc()
3543 		bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);  in bnx2x_ext_phy_update_adv_fc()
3544 		bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);  in bnx2x_ext_phy_update_adv_fc()
3547 		u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_ext_phy_update_adv_fc()
3549 		bnx2x_cl45_read(bp, phy,  in bnx2x_ext_phy_update_adv_fc()
3556 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_ext_phy_update_adv_fc()
3558 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_ext_phy_update_adv_fc()
3561 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_ext_phy_update_adv_fc()
3563 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_ext_phy_update_adv_fc()
3573 		bnx2x_cl45_read(bp, phy,  in bnx2x_ext_phy_update_adv_fc()
3576 		bnx2x_cl45_read(bp, phy,  in bnx2x_ext_phy_update_adv_fc()
3584 	DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);  in bnx2x_ext_phy_update_adv_fc()
3585 	bnx2x_pause_resolve(phy, params, vars, pause_result);  in bnx2x_ext_phy_update_adv_fc()
3589 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,  in bnx2x_ext_phy_resolve_fc()  argument
3594 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_ext_phy_resolve_fc()
3595 	if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {  in bnx2x_ext_phy_resolve_fc()
3596 		/* Update the advertised flow-controled of LD/LP in AN */  in bnx2x_ext_phy_resolve_fc()
3597 		if (phy->req_line_speed == SPEED_AUTO_NEG)  in bnx2x_ext_phy_resolve_fc()
3598 			bnx2x_ext_phy_update_adv_fc(phy, params, vars);  in bnx2x_ext_phy_resolve_fc()
3599 		/* But set the flow-control result as the requested one */  in bnx2x_ext_phy_resolve_fc()
3600 		vars->flow_ctrl = phy->req_flow_ctrl;  in bnx2x_ext_phy_resolve_fc()
3601 	} else if (phy->req_line_speed != SPEED_AUTO_NEG)  in bnx2x_ext_phy_resolve_fc()
3602 		vars->flow_ctrl = params->req_fc_auto_adv;  in bnx2x_ext_phy_resolve_fc()
3603 	else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {  in bnx2x_ext_phy_resolve_fc()
3605 		bnx2x_ext_phy_update_adv_fc(phy, params, vars);  in bnx2x_ext_phy_resolve_fc()
3615  * phy init is done purely in phy_init stage.
3628 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,  in bnx2x_warpcore_enable_AN_KR2()  argument
3632 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_enable_AN_KR2()
3635 		/* Step 1 - Program the TX/RX alignment markers */  in bnx2x_warpcore_enable_AN_KR2()
3642 		/* Step 2 - Configure the NP registers */  in bnx2x_warpcore_enable_AN_KR2()
3653 	DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");  in bnx2x_warpcore_enable_AN_KR2()
3655 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR2()
3659 		bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,  in bnx2x_warpcore_enable_AN_KR2()
3662 	/* Start KR2 work-around timer which handles BCM8073 link-parner */  in bnx2x_warpcore_enable_AN_KR2()
3663 	params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;  in bnx2x_warpcore_enable_AN_KR2()
3664 	bnx2x_update_link_attr(params, params->link_attr_sync);  in bnx2x_warpcore_enable_AN_KR2()
3669 			      struct bnx2x_phy *phy)  in bnx2x_disable_kr2()  argument
3671 	struct bnx2x *bp = params->bp;  in bnx2x_disable_kr2()
3674 		/* Step 1 - Program the TX/RX alignment markers */  in bnx2x_disable_kr2()
3691 	DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");  in bnx2x_disable_kr2()
3694 		bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,  in bnx2x_disable_kr2()
3696 	params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;  in bnx2x_disable_kr2()
3697 	bnx2x_update_link_attr(params, params->link_attr_sync);  in bnx2x_disable_kr2()
3699 	vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;  in bnx2x_disable_kr2()
3702 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,  in bnx2x_warpcore_set_lpi_passthrough()  argument
3705 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_lpi_passthrough()
3707 	DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");  in bnx2x_warpcore_set_lpi_passthrough()
3708 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_lpi_passthrough()
3710 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_lpi_passthrough()
3714 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,  in bnx2x_warpcore_restart_AN_KR()  argument
3718 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_restart_AN_KR()
3719 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_restart_AN_KR()
3720 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_restart_AN_KR()
3722 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_restart_AN_KR()
3726 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_restart_AN_KR()
3729 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,  in bnx2x_warpcore_enable_AN_KR()  argument
3734 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_enable_AN_KR()
3740 		/* Disable Autoneg: re-enable it after adv is done. */  in bnx2x_warpcore_enable_AN_KR()
3745 	DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");  in bnx2x_warpcore_enable_AN_KR()
3748 		bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,  in bnx2x_warpcore_enable_AN_KR()
3751 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3755 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3759 	if (((vars->line_speed == SPEED_AUTO_NEG) &&  in bnx2x_warpcore_enable_AN_KR()
3760 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||  in bnx2x_warpcore_enable_AN_KR()
3761 	    (vars->line_speed == SPEED_1000)) {  in bnx2x_warpcore_enable_AN_KR()
3766 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);  in bnx2x_warpcore_enable_AN_KR()
3767 		DP(NETIF_MSG_LINK, "Advertize 1G\n");  in bnx2x_warpcore_enable_AN_KR()
3769 	if (((vars->line_speed == SPEED_AUTO_NEG) &&  in bnx2x_warpcore_enable_AN_KR()
3770 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||  in bnx2x_warpcore_enable_AN_KR()
3771 	    (vars->line_speed ==  SPEED_10000)) {  in bnx2x_warpcore_enable_AN_KR()
3775 		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_enable_AN_KR()
3778 		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3780 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_enable_AN_KR()
3781 		DP(NETIF_MSG_LINK, "Advertize 10G\n");  in bnx2x_warpcore_enable_AN_KR()
3785 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_enable_AN_KR()
3786 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3790 	if (phy->flags & FLAGS_WC_DUAL_MODE)  in bnx2x_warpcore_enable_AN_KR()
3791 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3794 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3797 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3802 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3806 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3812 	if (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3814 			    port_hw_config[params->port].default_cfg)) &  in bnx2x_warpcore_enable_AN_KR()
3816 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3819 		DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");  in bnx2x_warpcore_enable_AN_KR()
3823 	bnx2x_ext_phy_set_pause(params, phy, vars);  in bnx2x_warpcore_enable_AN_KR()
3824 	vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;  in bnx2x_warpcore_enable_AN_KR()
3825 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3828 	/* Over 1G - AN local device user page 1 */  in bnx2x_warpcore_enable_AN_KR()
3829 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3832 	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_warpcore_enable_AN_KR()
3833 	     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||  in bnx2x_warpcore_enable_AN_KR()
3834 	    (phy->req_line_speed == SPEED_20000)) {  in bnx2x_warpcore_enable_AN_KR()
3836 		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_enable_AN_KR()
3839 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3843 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3845 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_enable_AN_KR()
3847 		bnx2x_warpcore_enable_AN_KR2(phy, params, vars);  in bnx2x_warpcore_enable_AN_KR()
3849 		/* Enable Auto-Detect to support 1G over CL37 as well */  in bnx2x_warpcore_enable_AN_KR()
3850 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3852 		wc_lane_config = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_enable_AN_KR()
3855 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3858 		 * parallel-detect loop when CL73 and CL37 are enabled.  in bnx2x_warpcore_enable_AN_KR()
3870 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_enable_AN_KR()
3874 		bnx2x_disable_kr2(params, vars, phy);  in bnx2x_warpcore_enable_AN_KR()
3878 	bnx2x_warpcore_restart_AN_KR(phy, params);  in bnx2x_warpcore_enable_AN_KR()
3881 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,  in bnx2x_warpcore_set_10G_KR()  argument
3885 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_10G_KR()
3901 		bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,  in bnx2x_warpcore_set_10G_KR()
3904 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_KR()
3906 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_set_10G_KR()
3909 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3912 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3915 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3918 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3921 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_set_10G_KR()
3923 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3926 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3930 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3934 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3938 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3942 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3944 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_KR()
3949 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,  in bnx2x_warpcore_set_10G_XFI()  argument
3953 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_10G_XFI()
3959 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3963 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3967 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);  in bnx2x_warpcore_set_10G_XFI()
3969 	/* Disable 100FX Enable and Auto-Detect */  in bnx2x_warpcore_set_10G_XFI()
3970 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3974 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3977 	/* Set Block address to Remote PHY & Clear forced_speed[5] */  in bnx2x_warpcore_set_10G_XFI()
3978 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3981 	/* Turn off auto-detect & fiber mode */  in bnx2x_warpcore_set_10G_XFI()
3982 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3987 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3989 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
3994 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4004 		cfg_tap_val = REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_set_10G_XFI()
4006 					      port_hw_config[params->port].  in bnx2x_warpcore_set_10G_XFI()
4050 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4054 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_10G_XFI()
4055 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4058 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4063 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4066 	/* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */  in bnx2x_warpcore_set_10G_XFI()
4067 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4070 	bnx2x_warpcore_set_lpi_passthrough(phy, params);  in bnx2x_warpcore_set_10G_XFI()
4073 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4077 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4081 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_10G_XFI()
4085 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,  in bnx2x_warpcore_set_20G_force_KR2()  argument
4089 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_20G_force_KR2()
4091 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_set_20G_force_KR2()
4095 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4098 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_set_20G_force_KR2()
4100 	bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4102 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4105 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4109 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4113 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4116 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4119 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4123 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4125 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4129 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_set_20G_force_KR2()
4132 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_force_KR2()
4135 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_set_20G_force_KR2()
4139 					 struct bnx2x_phy *phy,  in bnx2x_warpcore_set_20G_DXGXS()  argument
4143 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4147 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4150 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4153 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4156 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4159 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4162 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4165 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4168 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4171 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4175 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4179 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4183 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4187 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_20G_DXGXS()
4192 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,  in bnx2x_warpcore_set_sgmii_speed()  argument
4197 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_sgmii_speed()
4200 	/* Clear XFI clock comp in non-10G single lane mode. */  in bnx2x_warpcore_set_sgmii_speed()
4201 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4204 	bnx2x_warpcore_set_lpi_passthrough(phy, params);  in bnx2x_warpcore_set_sgmii_speed()
4206 	if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {  in bnx2x_warpcore_set_sgmii_speed()
4208 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4211 		DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");  in bnx2x_warpcore_set_sgmii_speed()
4213 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4216 		switch (phy->req_line_speed) {  in bnx2x_warpcore_set_sgmii_speed()
4226 			DP(NETIF_MSG_LINK,  in bnx2x_warpcore_set_sgmii_speed()
4227 			   "Speed not supported: 0x%x\n", phy->req_line_speed);  in bnx2x_warpcore_set_sgmii_speed()
4231 		if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_warpcore_set_sgmii_speed()
4234 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4237 		DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",  in bnx2x_warpcore_set_sgmii_speed()
4238 			       phy->req_line_speed);  in bnx2x_warpcore_set_sgmii_speed()
4239 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4241 		DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);  in bnx2x_warpcore_set_sgmii_speed()
4245 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4252 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4257 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4259 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4263 	/* Re-enable parallel detect */  in bnx2x_warpcore_set_sgmii_speed()
4264 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4269 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_sgmii_speed()
4275 				      struct bnx2x_phy *phy,  in bnx2x_warpcore_reset_lane()  argument
4280 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_reset_lane()
4286 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_reset_lane()
4288 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_reset_lane()
4292 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,  in bnx2x_warpcore_clear_regs()  argument
4296 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_clear_regs()
4315 	bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_clear_regs()
4319 		bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,  in bnx2x_warpcore_clear_regs()
4322 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_clear_regs()
4323 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_clear_regs()
4351 			DP(NETIF_MSG_LINK,  in bnx2x_get_mod_abs_int_cfg()
4354 			return -EINVAL;  in bnx2x_get_mod_abs_int_cfg()
4357 		*gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;  in bnx2x_get_mod_abs_int_cfg()
4358 		*gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;  in bnx2x_get_mod_abs_int_cfg()
4367 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,  in bnx2x_is_sfp_module_plugged()  argument
4370 	struct bnx2x *bp = params->bp;  in bnx2x_is_sfp_module_plugged()
4373 	if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,  in bnx2x_is_sfp_module_plugged()
4374 				      params->shmem_base, params->port,  in bnx2x_is_sfp_module_plugged()
4385 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,  in bnx2x_warpcore_get_sigdet()  argument
4389 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_get_sigdet()
4391 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_get_sigdet()
4393 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,  in bnx2x_warpcore_get_sigdet()
4399 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,  in bnx2x_warpcore_config_runtime()  argument
4403 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_config_runtime()
4407 	vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;  in bnx2x_warpcore_config_runtime()
4409 	if (!vars->turn_to_run_wc_rt)  in bnx2x_warpcore_config_runtime()
4412 	if (vars->rx_tx_asic_rst) {  in bnx2x_warpcore_config_runtime()
4413 		u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_runtime()
4414 		serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_runtime()
4416 				port_hw_config[params->port].default_cfg)) &  in bnx2x_warpcore_config_runtime()
4422 			bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,  in bnx2x_warpcore_config_runtime()
4429 				vars->rx_tx_asic_rst = 0;  in bnx2x_warpcore_config_runtime()
4432 				bnx2x_warpcore_reset_lane(bp, phy, 1);  in bnx2x_warpcore_config_runtime()
4433 				bnx2x_warpcore_reset_lane(bp, phy, 0);  in bnx2x_warpcore_config_runtime()
4436 				bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_config_runtime()
4439 				vars->rx_tx_asic_rst--;  in bnx2x_warpcore_config_runtime()
4440 				DP(NETIF_MSG_LINK, "0x%x retry left\n",  in bnx2x_warpcore_config_runtime()
4441 				vars->rx_tx_asic_rst);  in bnx2x_warpcore_config_runtime()
4449 	} /*params->rx_tx_asic_rst*/  in bnx2x_warpcore_config_runtime()
4452 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,  in bnx2x_warpcore_config_sfi()  argument
4455 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_sfi()
4456 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_config_sfi()
4457 	bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_sfi()
4458 	if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==  in bnx2x_warpcore_config_sfi()
4460 	    (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {  in bnx2x_warpcore_config_sfi()
4461 		DP(NETIF_MSG_LINK, "Setting 10G SFI\n");  in bnx2x_warpcore_config_sfi()
4462 		bnx2x_warpcore_set_10G_XFI(phy, params, 0);  in bnx2x_warpcore_config_sfi()
4464 		DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");  in bnx2x_warpcore_config_sfi()
4465 		bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);  in bnx2x_warpcore_config_sfi()
4470 					 struct bnx2x_phy *phy,  in bnx2x_sfp_e3_set_transmitter()  argument
4473 	struct bnx2x *bp = params->bp;  in bnx2x_sfp_e3_set_transmitter()
4475 	u8 port = params->port;  in bnx2x_sfp_e3_set_transmitter()
4477 	cfg_pin = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e3_set_transmitter()
4482 	DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);  in bnx2x_sfp_e3_set_transmitter()
4486 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)  in bnx2x_sfp_e3_set_transmitter()
4490 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,  in bnx2x_warpcore_config_init()  argument
4494 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_config_init()
4497 	u16 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_config_init()
4498 	serdes_net_if = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_config_init()
4500 				  port_hw_config[params->port].default_cfg)) &  in bnx2x_warpcore_config_init()
4502 	DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "  in bnx2x_warpcore_config_init()
4504 		       vars->line_speed, serdes_net_if);  in bnx2x_warpcore_config_init()
4505 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_config_init()
4506 	bnx2x_warpcore_reset_lane(bp, phy, 1);  in bnx2x_warpcore_config_init()
4507 	vars->phy_flags |= PHY_XGXS_FLAG;  in bnx2x_warpcore_config_init()
4509 	    (phy->req_line_speed &&  in bnx2x_warpcore_config_init()
4510 	     ((phy->req_line_speed == SPEED_100) ||  in bnx2x_warpcore_config_init()
4511 	      (phy->req_line_speed == SPEED_10)))) {  in bnx2x_warpcore_config_init()
4512 		vars->phy_flags |= PHY_SGMII_FLAG;  in bnx2x_warpcore_config_init()
4513 		DP(NETIF_MSG_LINK, "Setting SGMII mode\n");  in bnx2x_warpcore_config_init()
4514 		bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4515 		bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);  in bnx2x_warpcore_config_init()
4520 			if (params->loopback_mode != LOOPBACK_EXT)  in bnx2x_warpcore_config_init()
4521 				bnx2x_warpcore_enable_AN_KR(phy, params, vars);  in bnx2x_warpcore_config_init()
4523 				DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");  in bnx2x_warpcore_config_init()
4524 				bnx2x_warpcore_set_10G_KR(phy, params, vars);  in bnx2x_warpcore_config_init()
4529 			bnx2x_warpcore_clear_regs(phy, params, lane);  in bnx2x_warpcore_config_init()
4530 			if (vars->line_speed == SPEED_10000) {  in bnx2x_warpcore_config_init()
4531 				DP(NETIF_MSG_LINK, "Setting 10G XFI\n");  in bnx2x_warpcore_config_init()
4532 				bnx2x_warpcore_set_10G_XFI(phy, params, 1);  in bnx2x_warpcore_config_init()
4535 					DP(NETIF_MSG_LINK, "1G Fiber\n");  in bnx2x_warpcore_config_init()
4538 					DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");  in bnx2x_warpcore_config_init()
4541 				bnx2x_warpcore_set_sgmii_speed(phy,  in bnx2x_warpcore_config_init()
4554 			if ((params->loopback_mode == LOOPBACK_NONE) ||  in bnx2x_warpcore_config_init()
4555 			    (params->loopback_mode == LOOPBACK_EXT)) {  in bnx2x_warpcore_config_init()
4556 				if (bnx2x_is_sfp_module_plugged(phy, params))  in bnx2x_warpcore_config_init()
4557 					bnx2x_sfp_module_detection(phy, params);  in bnx2x_warpcore_config_init()
4560 								     phy, 1);  in bnx2x_warpcore_config_init()
4563 			bnx2x_warpcore_config_sfi(phy, params);  in bnx2x_warpcore_config_init()
4567 			if (vars->line_speed != SPEED_20000) {  in bnx2x_warpcore_config_init()
4568 				DP(NETIF_MSG_LINK, "Speed not supported yet\n");  in bnx2x_warpcore_config_init()
4571 			DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");  in bnx2x_warpcore_config_init()
4572 			bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);  in bnx2x_warpcore_config_init()
4575 			bnx2x_sfp_module_detection(phy, params);  in bnx2x_warpcore_config_init()
4578 			if (!params->loopback_mode) {  in bnx2x_warpcore_config_init()
4579 				bnx2x_warpcore_enable_AN_KR(phy, params, vars);  in bnx2x_warpcore_config_init()
4581 				DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");  in bnx2x_warpcore_config_init()
4582 				bnx2x_warpcore_set_20G_force_KR2(phy, params);  in bnx2x_warpcore_config_init()
4586 			DP(NETIF_MSG_LINK,  in bnx2x_warpcore_config_init()
4594 	bnx2x_warpcore_reset_lane(bp, phy, 0);  in bnx2x_warpcore_config_init()
4595 	DP(NETIF_MSG_LINK, "Exit config init\n");  in bnx2x_warpcore_config_init()
4598 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,  in bnx2x_warpcore_link_reset()  argument
4601 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_link_reset()
4603 	bnx2x_sfp_e3_set_transmitter(params, phy, 0);  in bnx2x_warpcore_link_reset()
4605 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_link_reset()
4607 	bnx2x_warpcore_reset_lane(bp, phy, 1);  in bnx2x_warpcore_link_reset()
4611 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4614 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4617 	/* Update those 1-copy registers */  in bnx2x_warpcore_link_reset()
4618 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_warpcore_link_reset()
4620 	/* Enable 1G MDIO (1-copy) */  in bnx2x_warpcore_link_reset()
4621 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4625 	bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4627 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_link_reset()
4629 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4632 	if (phy->flags & FLAGS_WC_DUAL_MODE)  in bnx2x_warpcore_link_reset()
4634 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4637 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4641 	if (phy->flags & FLAGS_WC_DUAL_MODE) {  in bnx2x_warpcore_link_reset()
4646 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_link_reset()
4649 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_warpcore_link_reset()
4653 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,  in bnx2x_set_warpcore_loopback()  argument
4656 	struct bnx2x *bp = params->bp;  in bnx2x_set_warpcore_loopback()
4659 	DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",  in bnx2x_set_warpcore_loopback()
4660 		       params->loopback_mode, phy->req_line_speed);  in bnx2x_set_warpcore_loopback()
4662 	if (phy->req_line_speed < SPEED_10000 ||  in bnx2x_set_warpcore_loopback()
4663 	    phy->supported & SUPPORTED_20000baseKR2_Full) {  in bnx2x_set_warpcore_loopback()
4664 		/* 10/100/1000/20G-KR2 */  in bnx2x_set_warpcore_loopback()
4666 		/* Update those 1-copy registers */  in bnx2x_set_warpcore_loopback()
4667 		CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_set_warpcore_loopback()
4669 		/* Enable 1G MDIO (1-copy) */  in bnx2x_set_warpcore_loopback()
4670 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_set_warpcore_loopback()
4673 		/* Set 1G loopback based on lane (1-copy) */  in bnx2x_set_warpcore_loopback()
4674 		lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_set_warpcore_loopback()
4675 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_set_warpcore_loopback()
4678 		if (phy->flags & FLAGS_WC_DUAL_MODE)  in bnx2x_set_warpcore_loopback()
4680 		bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_set_warpcore_loopback()
4684 		/* Switch back to 4-copy registers */  in bnx2x_set_warpcore_loopback()
4685 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_set_warpcore_loopback()
4687 		/* 10G / 20G-DXGXS */  in bnx2x_set_warpcore_loopback()
4688 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_set_warpcore_loopback()
4691 		bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_set_warpcore_loopback()
4701 	struct bnx2x *bp = params->bp;  in bnx2x_sync_link()
4703 	if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)  in bnx2x_sync_link()
4704 		vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;  in bnx2x_sync_link()
4705 	vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);  in bnx2x_sync_link()
4706 	if (vars->link_up) {  in bnx2x_sync_link()
4707 		DP(NETIF_MSG_LINK, "phy link up\n");  in bnx2x_sync_link()
4709 		vars->phy_link_up = 1;  in bnx2x_sync_link()
4710 		vars->duplex = DUPLEX_FULL;  in bnx2x_sync_link()
4711 		switch (vars->link_status &  in bnx2x_sync_link()
4714 			vars->duplex = DUPLEX_HALF;  in bnx2x_sync_link()
4717 			vars->line_speed = SPEED_10;  in bnx2x_sync_link()
4721 			vars->duplex = DUPLEX_HALF;  in bnx2x_sync_link()
4725 			vars->line_speed = SPEED_100;  in bnx2x_sync_link()
4729 			vars->duplex = DUPLEX_HALF;  in bnx2x_sync_link()
4732 			vars->line_speed = SPEED_1000;  in bnx2x_sync_link()
4736 			vars->duplex = DUPLEX_HALF;  in bnx2x_sync_link()
4739 			vars->line_speed = SPEED_2500;  in bnx2x_sync_link()
4743 			vars->line_speed = SPEED_10000;  in bnx2x_sync_link()
4746 			vars->line_speed = SPEED_20000;  in bnx2x_sync_link()
4751 		vars->flow_ctrl = 0;  in bnx2x_sync_link()
4752 		if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)  in bnx2x_sync_link()
4753 			vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;  in bnx2x_sync_link()
4755 		if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)  in bnx2x_sync_link()
4756 			vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;  in bnx2x_sync_link()
4758 		if (!vars->flow_ctrl)  in bnx2x_sync_link()
4759 			vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_sync_link()
4761 		if (vars->line_speed &&  in bnx2x_sync_link()
4762 		    ((vars->line_speed == SPEED_10) ||  in bnx2x_sync_link()
4763 		     (vars->line_speed == SPEED_100))) {  in bnx2x_sync_link()
4764 			vars->phy_flags |= PHY_SGMII_FLAG;  in bnx2x_sync_link()
4766 			vars->phy_flags &= ~PHY_SGMII_FLAG;  in bnx2x_sync_link()
4768 		if (vars->line_speed &&  in bnx2x_sync_link()
4770 		    (vars->line_speed == SPEED_1000))  in bnx2x_sync_link()
4771 			vars->phy_flags |= PHY_SGMII_FLAG;  in bnx2x_sync_link()
4773 		link_10g_plus = (vars->line_speed >= SPEED_10000);  in bnx2x_sync_link()
4777 				vars->mac_type = MAC_TYPE_XMAC;  in bnx2x_sync_link()
4779 				vars->mac_type = MAC_TYPE_BMAC;  in bnx2x_sync_link()
4782 				vars->mac_type = MAC_TYPE_UMAC;  in bnx2x_sync_link()
4784 				vars->mac_type = MAC_TYPE_EMAC;  in bnx2x_sync_link()
4787 		DP(NETIF_MSG_LINK, "phy link down\n");  in bnx2x_sync_link()
4789 		vars->phy_link_up = 0;  in bnx2x_sync_link()
4791 		vars->line_speed = 0;  in bnx2x_sync_link()
4792 		vars->duplex = DUPLEX_FULL;  in bnx2x_sync_link()
4793 		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_sync_link()
4796 		vars->mac_type = MAC_TYPE_NONE;  in bnx2x_sync_link()
4797 		if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)  in bnx2x_sync_link()
4798 			vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;  in bnx2x_sync_link()
4799 		if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)  in bnx2x_sync_link()
4800 			vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;  in bnx2x_sync_link()
4807 	struct bnx2x *bp = params->bp;  in bnx2x_link_status_update()
4808 	u8 port = params->port;  in bnx2x_link_status_update()
4810 	/* Update PHY configuration */  in bnx2x_link_status_update()
4813 	vars->link_status = REG_RD(bp, params->shmem_base +  in bnx2x_link_status_update()
4818 	if (params->loopback_mode != LOOPBACK_NONE &&  in bnx2x_link_status_update()
4819 	    params->loopback_mode != LOOPBACK_EXT)  in bnx2x_link_status_update()
4820 		vars->link_status |= LINK_STATUS_LINK_UP;  in bnx2x_link_status_update()
4823 		vars->eee_status = REG_RD(bp, params->shmem2_base +  in bnx2x_link_status_update()
4825 						   eee_status[params->port]));  in bnx2x_link_status_update()
4827 	vars->phy_flags = PHY_XGXS_FLAG;  in bnx2x_link_status_update()
4830 	sync_offset = params->shmem_base +  in bnx2x_link_status_update()
4835 	params->phy[INT_PHY].media_type =  in bnx2x_link_status_update()
4838 	params->phy[EXT_PHY1].media_type =  in bnx2x_link_status_update()
4841 	params->phy[EXT_PHY2].media_type =  in bnx2x_link_status_update()
4844 	DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);  in bnx2x_link_status_update()
4847 	sync_offset = params->shmem_base +  in bnx2x_link_status_update()
4851 	vars->aeu_int_mask = REG_RD(bp, sync_offset);  in bnx2x_link_status_update()
4854 	if (vars->link_status & LINK_STATUS_PFC_ENABLED)  in bnx2x_link_status_update()
4855 		params->feature_config_flags |=  in bnx2x_link_status_update()
4858 		params->feature_config_flags &=  in bnx2x_link_status_update()
4862 		params->link_attr_sync = SHMEM2_RD(bp,  in bnx2x_link_status_update()
4863 						 link_attr_sync[params->port]);  in bnx2x_link_status_update()
4865 	DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",  in bnx2x_link_status_update()
4866 		 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);  in bnx2x_link_status_update()
4867 	DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",  in bnx2x_link_status_update()
4868 		 vars->line_speed, vars->duplex, vars->flow_ctrl);  in bnx2x_link_status_update()
4872 				struct bnx2x_phy *phy)  in bnx2x_set_master_ln()  argument
4874 	struct bnx2x *bp = params->bp;  in bnx2x_set_master_ln()
4876 	ser_lane = ((params->lane_config &  in bnx2x_set_master_ln()
4881 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_master_ln()
4886 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_master_ln()
4893 			       struct bnx2x_phy *phy,  in bnx2x_reset_unicore()  argument
4896 	struct bnx2x *bp = params->bp;  in bnx2x_reset_unicore()
4899 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_reset_unicore()
4904 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_reset_unicore()
4910 		bnx2x_set_serdes_access(bp, params->port);  in bnx2x_reset_unicore()
4917 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_reset_unicore()
4928 	netdev_err(bp->dev,  "Warning: PHY was not initialized,"  in bnx2x_reset_unicore()
4930 			 params->port);  in bnx2x_reset_unicore()
4931 	DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");  in bnx2x_reset_unicore()
4932 	return -EINVAL;  in bnx2x_reset_unicore()
4937 				 struct bnx2x_phy *phy)  in bnx2x_set_swap_lanes()  argument
4939 	struct bnx2x *bp = params->bp;  in bnx2x_set_swap_lanes()
4945 	rx_lane_swap = ((params->lane_config &  in bnx2x_set_swap_lanes()
4948 	tx_lane_swap = ((params->lane_config &  in bnx2x_set_swap_lanes()
4953 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_swap_lanes()
4960 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_swap_lanes()
4966 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_swap_lanes()
4972 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_swap_lanes()
4978 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,  in bnx2x_set_parallel_detection()  argument
4981 	struct bnx2x *bp = params->bp;  in bnx2x_set_parallel_detection()
4983 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
4987 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)  in bnx2x_set_parallel_detection()
4991 	DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",  in bnx2x_set_parallel_detection()
4992 		phy->speed_cap_mask, control2);  in bnx2x_set_parallel_detection()
4993 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
4998 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&  in bnx2x_set_parallel_detection()
4999 	     (phy->speed_cap_mask &  in bnx2x_set_parallel_detection()
5001 		DP(NETIF_MSG_LINK, "XGXS\n");  in bnx2x_set_parallel_detection()
5003 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
5008 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
5017 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
5023 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_parallel_detection()
5031 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,  in bnx2x_set_autoneg()  argument
5036 	struct bnx2x *bp = params->bp;  in bnx2x_set_autoneg()
5040 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5045 	if (vars->line_speed == SPEED_AUTO_NEG)  in bnx2x_set_autoneg()
5051 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5057 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5063 	if (vars->line_speed == SPEED_AUTO_NEG)  in bnx2x_set_autoneg()
5068 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5073 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5077 	if (vars->line_speed == SPEED_AUTO_NEG) {  in bnx2x_set_autoneg()
5086 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5093 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5099 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5107 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5111 		if (phy->speed_cap_mask &  in bnx2x_set_autoneg()
5114 		if (phy->speed_cap_mask &  in bnx2x_set_autoneg()
5118 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5129 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_autoneg()
5135 static void bnx2x_program_serdes(struct bnx2x_phy *phy,  in bnx2x_program_serdes()  argument
5139 	struct bnx2x *bp = params->bp;  in bnx2x_program_serdes()
5143 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_program_serdes()
5149 	if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_program_serdes()
5151 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_program_serdes()
5156 	 *  - needed only if the speed is greater than 1G (2.5G or 10G)  in bnx2x_program_serdes()
5158 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_program_serdes()
5162 	DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);  in bnx2x_program_serdes()
5167 	if (!((vars->line_speed == SPEED_1000) ||  in bnx2x_program_serdes()
5168 	      (vars->line_speed == SPEED_100) ||  in bnx2x_program_serdes()
5169 	      (vars->line_speed == SPEED_10))) {  in bnx2x_program_serdes()
5173 		if (vars->line_speed == SPEED_10000)  in bnx2x_program_serdes()
5178 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_program_serdes()
5184 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,  in bnx2x_set_brcm_cl37_advertisement()  argument
5187 	struct bnx2x *bp = params->bp;  in bnx2x_set_brcm_cl37_advertisement()
5191 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)  in bnx2x_set_brcm_cl37_advertisement()
5193 	if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)  in bnx2x_set_brcm_cl37_advertisement()
5195 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_brcm_cl37_advertisement()
5199 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_brcm_cl37_advertisement()
5204 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,  in bnx2x_set_ieee_aneg_advertisement()  argument
5208 	struct bnx2x *bp = params->bp;  in bnx2x_set_ieee_aneg_advertisement()
5212 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_ieee_aneg_advertisement()
5215 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_ieee_aneg_advertisement()
5220 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_ieee_aneg_advertisement()
5225 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,  in bnx2x_restart_autoneg()  argument
5229 	struct bnx2x *bp = params->bp;  in bnx2x_restart_autoneg()
5232 	DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");  in bnx2x_restart_autoneg()
5236 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_restart_autoneg()
5241 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_restart_autoneg()
5249 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_restart_autoneg()
5253 		DP(NETIF_MSG_LINK,  in bnx2x_restart_autoneg()
5256 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_restart_autoneg()
5265 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,  in bnx2x_initialize_sgmii_process()  argument
5269 	struct bnx2x *bp = params->bp;  in bnx2x_initialize_sgmii_process()
5274 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_initialize_sgmii_process()
5283 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_initialize_sgmii_process()
5289 	if (!(vars->line_speed == SPEED_AUTO_NEG)) {  in bnx2x_initialize_sgmii_process()
5293 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_initialize_sgmii_process()
5301 		switch (vars->line_speed) {  in bnx2x_initialize_sgmii_process()
5315 			DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",  in bnx2x_initialize_sgmii_process()
5316 				  vars->line_speed);  in bnx2x_initialize_sgmii_process()
5321 		if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_initialize_sgmii_process()
5324 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_initialize_sgmii_process()
5331 		bnx2x_restart_autoneg(phy, params, 0);  in bnx2x_initialize_sgmii_process()
5337 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,  in bnx2x_direct_parallel_detect_used()  argument
5340 	struct bnx2x *bp = params->bp;  in bnx2x_direct_parallel_detect_used()
5342 	if (phy->req_line_speed != SPEED_AUTO_NEG)  in bnx2x_direct_parallel_detect_used()
5344 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_direct_parallel_detect_used()
5348 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_direct_parallel_detect_used()
5353 		DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",  in bnx2x_direct_parallel_detect_used()
5354 			 params->port);  in bnx2x_direct_parallel_detect_used()
5358 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_direct_parallel_detect_used()
5364 		DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",  in bnx2x_direct_parallel_detect_used()
5365 			 params->port);  in bnx2x_direct_parallel_detect_used()
5371 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,  in bnx2x_update_adv_fc()  argument
5379 	struct bnx2x *bp = params->bp;  in bnx2x_update_adv_fc()
5386 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_update_adv_fc()
5390 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_update_adv_fc()
5398 		DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);  in bnx2x_update_adv_fc()
5400 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_update_adv_fc()
5404 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_update_adv_fc()
5412 		DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);  in bnx2x_update_adv_fc()
5414 	bnx2x_pause_resolve(phy, params, vars, pause_result);  in bnx2x_update_adv_fc()
5418 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,  in bnx2x_flow_ctrl_resolve()  argument
5423 	struct bnx2x *bp = params->bp;  in bnx2x_flow_ctrl_resolve()
5424 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_flow_ctrl_resolve()
5427 	if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {  in bnx2x_flow_ctrl_resolve()
5428 		/* Update the advertised flow-controled of LD/LP in AN */  in bnx2x_flow_ctrl_resolve()
5429 		if (phy->req_line_speed == SPEED_AUTO_NEG)  in bnx2x_flow_ctrl_resolve()
5430 			bnx2x_update_adv_fc(phy, params, vars, gp_status);  in bnx2x_flow_ctrl_resolve()
5431 		/* But set the flow-control result as the requested one */  in bnx2x_flow_ctrl_resolve()
5432 		vars->flow_ctrl = phy->req_flow_ctrl;  in bnx2x_flow_ctrl_resolve()
5433 	} else if (phy->req_line_speed != SPEED_AUTO_NEG)  in bnx2x_flow_ctrl_resolve()
5434 		vars->flow_ctrl = params->req_fc_auto_adv;  in bnx2x_flow_ctrl_resolve()
5436 		 (!(vars->phy_flags & PHY_SGMII_FLAG))) {  in bnx2x_flow_ctrl_resolve()
5437 		if (bnx2x_direct_parallel_detect_used(phy, params)) {  in bnx2x_flow_ctrl_resolve()
5438 			vars->flow_ctrl = params->req_fc_auto_adv;  in bnx2x_flow_ctrl_resolve()
5441 		bnx2x_update_adv_fc(phy, params, vars, gp_status);  in bnx2x_flow_ctrl_resolve()
5443 	DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);  in bnx2x_flow_ctrl_resolve()
5446 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,  in bnx2x_check_fallback_to_cl37()  argument
5449 	struct bnx2x *bp = params->bp;  in bnx2x_check_fallback_to_cl37()
5451 	DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");  in bnx2x_check_fallback_to_cl37()
5453 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_check_fallback_to_cl37()
5459 		DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."  in bnx2x_check_fallback_to_cl37()
5461 		CL22_WR_OVER_CL45(bp, phy,  in bnx2x_check_fallback_to_cl37()
5468 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_check_fallback_to_cl37()
5477 		DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "  in bnx2x_check_fallback_to_cl37()
5484 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_check_fallback_to_cl37()
5493 		DP(NETIF_MSG_LINK, "No CL37 FSM were received. "  in bnx2x_check_fallback_to_cl37()
5501 	 * restart cl37 auto-neg  in bnx2x_check_fallback_to_cl37()
5505 	CL22_WR_OVER_CL45(bp, phy,  in bnx2x_check_fallback_to_cl37()
5510 	bnx2x_restart_autoneg(phy, params, 0);  in bnx2x_check_fallback_to_cl37()
5511 	DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");  in bnx2x_check_fallback_to_cl37()
5514 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,  in bnx2x_xgxs_an_resolve()  argument
5520 		vars->link_status |=  in bnx2x_xgxs_an_resolve()
5523 	if (bnx2x_direct_parallel_detect_used(phy, params))  in bnx2x_xgxs_an_resolve()
5524 		vars->link_status |=  in bnx2x_xgxs_an_resolve()
5527 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,  in bnx2x_get_link_speed_duplex()  argument
5534 	struct bnx2x *bp = params->bp;  in bnx2x_get_link_speed_duplex()
5535 	if (phy->req_line_speed == SPEED_AUTO_NEG)  in bnx2x_get_link_speed_duplex()
5536 		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;  in bnx2x_get_link_speed_duplex()
5538 		DP(NETIF_MSG_LINK, "phy link up\n");  in bnx2x_get_link_speed_duplex()
5540 		vars->phy_link_up = 1;  in bnx2x_get_link_speed_duplex()
5541 		vars->link_status |= LINK_STATUS_LINK_UP;  in bnx2x_get_link_speed_duplex()
5545 			vars->line_speed = SPEED_10;  in bnx2x_get_link_speed_duplex()
5547 				vars->link_status |= LINK_10TFD;  in bnx2x_get_link_speed_duplex()
5549 				vars->link_status |= LINK_10THD;  in bnx2x_get_link_speed_duplex()
5553 			vars->line_speed = SPEED_100;  in bnx2x_get_link_speed_duplex()
5555 				vars->link_status |= LINK_100TXFD;  in bnx2x_get_link_speed_duplex()
5557 				vars->link_status |= LINK_100TXHD;  in bnx2x_get_link_speed_duplex()
5562 			vars->line_speed = SPEED_1000;  in bnx2x_get_link_speed_duplex()
5564 				vars->link_status |= LINK_1000TFD;  in bnx2x_get_link_speed_duplex()
5566 				vars->link_status |= LINK_1000THD;  in bnx2x_get_link_speed_duplex()
5570 			vars->line_speed = SPEED_2500;  in bnx2x_get_link_speed_duplex()
5572 				vars->link_status |= LINK_2500TFD;  in bnx2x_get_link_speed_duplex()
5574 				vars->link_status |= LINK_2500THD;  in bnx2x_get_link_speed_duplex()
5579 			DP(NETIF_MSG_LINK,  in bnx2x_get_link_speed_duplex()
5582 			return -EINVAL;  in bnx2x_get_link_speed_duplex()
5590 			vars->line_speed = SPEED_10000;  in bnx2x_get_link_speed_duplex()
5591 			vars->link_status |= LINK_10GTFD;  in bnx2x_get_link_speed_duplex()
5595 			vars->line_speed = SPEED_20000;  in bnx2x_get_link_speed_duplex()
5596 			vars->link_status |= LINK_20GTFD;  in bnx2x_get_link_speed_duplex()
5599 			DP(NETIF_MSG_LINK,  in bnx2x_get_link_speed_duplex()
5602 			return -EINVAL;  in bnx2x_get_link_speed_duplex()
5605 		DP(NETIF_MSG_LINK, "phy link down\n");  in bnx2x_get_link_speed_duplex()
5607 		vars->phy_link_up = 0;  in bnx2x_get_link_speed_duplex()
5609 		vars->duplex = DUPLEX_FULL;  in bnx2x_get_link_speed_duplex()
5610 		vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_get_link_speed_duplex()
5611 		vars->mac_type = MAC_TYPE_NONE;  in bnx2x_get_link_speed_duplex()
5613 	DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",  in bnx2x_get_link_speed_duplex()
5614 		    vars->phy_link_up, vars->line_speed);  in bnx2x_get_link_speed_duplex()
5618 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,  in bnx2x_link_settings_status()  argument
5622 	struct bnx2x *bp = params->bp;  in bnx2x_link_settings_status()
5628 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_link_settings_status()
5637 	DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",  in bnx2x_link_settings_status()
5639 	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,  in bnx2x_link_settings_status()
5641 	if (rc == -EINVAL)  in bnx2x_link_settings_status()
5646 			vars->duplex = duplex;  in bnx2x_link_settings_status()
5647 			bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);  in bnx2x_link_settings_status()
5648 			if (phy->req_line_speed == SPEED_AUTO_NEG)  in bnx2x_link_settings_status()
5649 				bnx2x_xgxs_an_resolve(phy, params, vars,  in bnx2x_link_settings_status()
5653 		if ((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_link_settings_status()
5656 			bnx2x_check_fallback_to_cl37(phy, params);  in bnx2x_link_settings_status()
5662 	    (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {  in bnx2x_link_settings_status()
5665 		CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,  in bnx2x_link_settings_status()
5669 			vars->link_status |=  in bnx2x_link_settings_status()
5673 			vars->link_status |=  in bnx2x_link_settings_status()
5676 		CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,  in bnx2x_link_settings_status()
5680 			vars->link_status |=  in bnx2x_link_settings_status()
5683 			vars->link_status |=  in bnx2x_link_settings_status()
5687 	DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in bnx2x_link_settings_status()
5688 		   vars->duplex, vars->flow_ctrl, vars->link_status);  in bnx2x_link_settings_status()
5692 static u8 bnx2x_warpcore_read_status(struct bnx2x_phy *phy,  in bnx2x_warpcore_read_status()  argument
5696 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_read_status()
5700 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_read_status()
5702 	if ((params->loopback_mode) &&  in bnx2x_warpcore_read_status()
5703 	    (phy->flags & FLAGS_WC_DUAL_MODE)) {  in bnx2x_warpcore_read_status()
5704 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5706 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5709 	} else if ((phy->req_line_speed > SPEED_10000) &&  in bnx2x_warpcore_read_status()
5710 		(phy->supported & SUPPORTED_20000baseMLD2_Full)) {  in bnx2x_warpcore_read_status()
5712 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5714 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5716 		DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",  in bnx2x_warpcore_read_status()
5720 			bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_warpcore_read_status()
5722 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5725 		DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);  in bnx2x_warpcore_read_status()
5731 		if (phy->supported & SUPPORTED_20000baseKR2_Full) {  in bnx2x_warpcore_read_status()
5733 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_read_status()
5735 			bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_read_status()
5741 			if (phy->req_line_speed == SPEED_AUTO_NEG) {  in bnx2x_warpcore_read_status()
5743 				bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5747 					vars->link_status |=  in bnx2x_warpcore_read_status()
5751 				bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5755 					vars->link_status |=  in bnx2x_warpcore_read_status()
5758 			bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_warpcore_read_status()
5759 			vars->duplex = duplex;  in bnx2x_warpcore_read_status()
5763 	if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&  in bnx2x_warpcore_read_status()
5767 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_warpcore_read_status()
5771 			vars->link_status |=  in bnx2x_warpcore_read_status()
5775 			vars->link_status |=  in bnx2x_warpcore_read_status()
5778 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5782 			vars->link_status |=  in bnx2x_warpcore_read_status()
5785 			vars->link_status |=  in bnx2x_warpcore_read_status()
5792 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5795 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_read_status()
5798 	DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);  in bnx2x_warpcore_read_status()
5805 	rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,  in bnx2x_warpcore_read_status()
5809 	if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&  in bnx2x_warpcore_read_status()
5810 	    (!(phy->flags & FLAGS_WC_DUAL_MODE)))  in bnx2x_warpcore_read_status()
5811 		vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;  in bnx2x_warpcore_read_status()
5813 	DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",  in bnx2x_warpcore_read_status()
5814 		   vars->duplex, vars->flow_ctrl, vars->link_status);  in bnx2x_warpcore_read_status()
5819 	struct bnx2x *bp = params->bp;  in bnx2x_set_gmii_tx_driver()
5820 	struct bnx2x_phy *phy = &params->phy[INT_PHY];  in bnx2x_set_gmii_tx_driver()  local
5826 	CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_gmii_tx_driver()
5839 	      bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {  in bnx2x_set_gmii_tx_driver()
5840 		CL22_RD_OVER_CL45(bp, phy,  in bnx2x_set_gmii_tx_driver()
5849 			CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_gmii_tx_driver()
5859 	struct bnx2x *bp = params->bp;  in bnx2x_emac_program()
5860 	u8 port = params->port;  in bnx2x_emac_program()
5863 	DP(NETIF_MSG_LINK, "setting link speed & duplex\n");  in bnx2x_emac_program()
5869 	switch (vars->line_speed) {  in bnx2x_emac_program()
5888 		DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",  in bnx2x_emac_program()
5889 			   vars->line_speed);  in bnx2x_emac_program()
5890 		return -EINVAL;  in bnx2x_emac_program()
5893 	if (vars->duplex == DUPLEX_HALF)  in bnx2x_emac_program()
5899 	bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);  in bnx2x_emac_program()
5903 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,  in bnx2x_set_preemphasis()  argument
5908 	struct bnx2x *bp = params->bp;  in bnx2x_set_preemphasis()
5911 	      bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {  in bnx2x_set_preemphasis()
5912 			CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_preemphasis()
5915 					  phy->rx_preemphasis[i]);  in bnx2x_set_preemphasis()
5919 		      bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {  in bnx2x_set_preemphasis()
5920 			CL22_WR_OVER_CL45(bp, phy,  in bnx2x_set_preemphasis()
5923 					  phy->tx_preemphasis[i]);  in bnx2x_set_preemphasis()
5927 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,  in bnx2x_xgxs_config_init()  argument
5931 	struct bnx2x *bp = params->bp;  in bnx2x_xgxs_config_init()
5933 			  (params->loopback_mode == LOOPBACK_XGXS));  in bnx2x_xgxs_config_init()
5934 	if (!(vars->phy_flags & PHY_SGMII_FLAG)) {  in bnx2x_xgxs_config_init()
5936 		    (params->feature_config_flags &  in bnx2x_xgxs_config_init()
5938 			bnx2x_set_preemphasis(phy, params);  in bnx2x_xgxs_config_init()
5941 		if (vars->line_speed != SPEED_AUTO_NEG ||  in bnx2x_xgxs_config_init()
5943 		     params->loopback_mode == LOOPBACK_EXT)) {  in bnx2x_xgxs_config_init()
5944 			DP(NETIF_MSG_LINK, "not SGMII, no AN\n");  in bnx2x_xgxs_config_init()
5947 			bnx2x_set_autoneg(phy, params, vars, 0);  in bnx2x_xgxs_config_init()
5950 			bnx2x_program_serdes(phy, params, vars);  in bnx2x_xgxs_config_init()
5953 			DP(NETIF_MSG_LINK, "not SGMII, AN\n");  in bnx2x_xgxs_config_init()
5956 			bnx2x_set_brcm_cl37_advertisement(phy, params);  in bnx2x_xgxs_config_init()
5959 			bnx2x_set_ieee_aneg_advertisement(phy, params,  in bnx2x_xgxs_config_init()
5960 							  vars->ieee_fc);  in bnx2x_xgxs_config_init()
5963 			bnx2x_set_autoneg(phy, params, vars, enable_cl73);  in bnx2x_xgxs_config_init()
5966 			bnx2x_restart_autoneg(phy, params, enable_cl73);  in bnx2x_xgxs_config_init()
5970 		DP(NETIF_MSG_LINK, "SGMII\n");  in bnx2x_xgxs_config_init()
5972 		bnx2x_initialize_sgmii_process(phy, params, vars);  in bnx2x_xgxs_config_init()
5976 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,  in bnx2x_prepare_xgxs()  argument
5981 	vars->phy_flags |= PHY_XGXS_FLAG;  in bnx2x_prepare_xgxs()
5982 	if ((phy->req_line_speed &&  in bnx2x_prepare_xgxs()
5983 	     ((phy->req_line_speed == SPEED_100) ||  in bnx2x_prepare_xgxs()
5984 	      (phy->req_line_speed == SPEED_10))) ||  in bnx2x_prepare_xgxs()
5985 	    (!phy->req_line_speed &&  in bnx2x_prepare_xgxs()
5986 	     (phy->speed_cap_mask >=  in bnx2x_prepare_xgxs()
5988 	     (phy->speed_cap_mask <  in bnx2x_prepare_xgxs()
5990 	    (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))  in bnx2x_prepare_xgxs()
5991 		vars->phy_flags |= PHY_SGMII_FLAG;  in bnx2x_prepare_xgxs()
5993 		vars->phy_flags &= ~PHY_SGMII_FLAG;  in bnx2x_prepare_xgxs()
5995 	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in bnx2x_prepare_xgxs()
5996 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_prepare_xgxs()
5997 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in bnx2x_prepare_xgxs()
5998 		bnx2x_set_master_ln(params, phy);  in bnx2x_prepare_xgxs()
6000 	rc = bnx2x_reset_unicore(params, phy, 0);  in bnx2x_prepare_xgxs()
6005 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_prepare_xgxs()
6007 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {  in bnx2x_prepare_xgxs()
6008 		bnx2x_set_master_ln(params, phy);  in bnx2x_prepare_xgxs()
6009 		bnx2x_set_swap_lanes(params, phy);  in bnx2x_prepare_xgxs()
6016 				     struct bnx2x_phy *phy,  in bnx2x_wait_reset_complete()  argument
6022 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)  in bnx2x_wait_reset_complete()
6023 			bnx2x_cl22_read(bp, phy,  in bnx2x_wait_reset_complete()
6026 			bnx2x_cl45_read(bp, phy,  in bnx2x_wait_reset_complete()
6035 		netdev_err(bp->dev,  "Warning: PHY was not initialized,"  in bnx2x_wait_reset_complete()
6037 			 params->port);  in bnx2x_wait_reset_complete()
6038 	DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);  in bnx2x_wait_reset_complete()
6044 	u8 port = params->port;  in bnx2x_link_int_enable()
6046 	struct bnx2x *bp = params->bp;  in bnx2x_link_int_enable()
6053 	} else if (params->switch_cfg == SWITCH_CFG_10G) {  in bnx2x_link_int_enable()
6056 		DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");  in bnx2x_link_int_enable()
6058 			params->phy[INT_PHY].type !=  in bnx2x_link_int_enable()
6061 			DP(NETIF_MSG_LINK, "enabled external phy int\n");  in bnx2x_link_int_enable()
6066 		DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");  in bnx2x_link_int_enable()
6068 			params->phy[INT_PHY].type !=  in bnx2x_link_int_enable()
6071 			DP(NETIF_MSG_LINK, "enabled external phy int\n");  in bnx2x_link_int_enable()
6078 	DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,  in bnx2x_link_int_enable()
6079 		 (params->switch_cfg == SWITCH_CFG_10G),  in bnx2x_link_int_enable()
6081 	DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",  in bnx2x_link_int_enable()
6085 	DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",  in bnx2x_link_int_enable()
6095 	/* Disable the MI INT ( external phy int ) by writing 1 to the  in bnx2x_rearm_latch_signal()
6096 	 * status register. Link down indication is high-active-signal,  in bnx2x_rearm_latch_signal()
6102 	DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);  in bnx2x_rearm_latch_signal()
6103 	/* Handle only those with latched-signal=up.*/  in bnx2x_rearm_latch_signal()
6117 		/* For all latched-signal=up : Re-Arm Latch signals */  in bnx2x_rearm_latch_signal()
6121 	/* For all latched-signal=up,Write original_signal to status */  in bnx2x_rearm_latch_signal()
6127 	struct bnx2x *bp = params->bp;  in bnx2x_link_int_ack()
6128 	u8 port = params->port;  in bnx2x_link_int_ack()
6137 	if (vars->phy_link_up) {  in bnx2x_link_int_ack()
6143 			else if (params->switch_cfg == SWITCH_CFG_10G) {  in bnx2x_link_int_ack()
6148 					((params->lane_config &  in bnx2x_link_int_ack()
6156 		DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",  in bnx2x_link_int_ack()
6178 		return -EINVAL;  in bnx2x_format_ver()
6183 	*len -= ret;  in bnx2x_format_ver()
6194 		return -EINVAL;  in bnx2x_3_seq_format_ver()
6199 	*len -= ret;  in bnx2x_3_seq_format_ver()
6212 		return -EINVAL;  in bnx2x_get_ext_phy_fw_version()
6213 	bp = params->bp;  in bnx2x_get_ext_phy_fw_version()
6215 	/* Extract first external phy*/  in bnx2x_get_ext_phy_fw_version()
6217 	spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6219 	if (params->phy[EXT_PHY1].format_fw_ver) {  in bnx2x_get_ext_phy_fw_version()
6220 		status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,  in bnx2x_get_ext_phy_fw_version()
6223 		ver_p += (len - remain_len);  in bnx2x_get_ext_phy_fw_version()
6225 	if ((params->num_phys == MAX_PHYS) &&  in bnx2x_get_ext_phy_fw_version()
6226 	    (params->phy[EXT_PHY2].ver_addr != 0)) {  in bnx2x_get_ext_phy_fw_version()
6227 		spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);  in bnx2x_get_ext_phy_fw_version()
6228 		if (params->phy[EXT_PHY2].format_fw_ver) {  in bnx2x_get_ext_phy_fw_version()
6231 			remain_len--;  in bnx2x_get_ext_phy_fw_version()
6232 			status |= params->phy[EXT_PHY2].format_fw_ver(  in bnx2x_get_ext_phy_fw_version()
6236 			ver_p = version + (len - remain_len);  in bnx2x_get_ext_phy_fw_version()
6243 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,  in bnx2x_set_xgxs_loopback()  argument
6246 	u8 port = params->port;  in bnx2x_set_xgxs_loopback()
6247 	struct bnx2x *bp = params->bp;  in bnx2x_set_xgxs_loopback()
6249 	if (phy->req_line_speed != SPEED_1000) {  in bnx2x_set_xgxs_loopback()
6252 		DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");  in bnx2x_set_xgxs_loopback()
6263 		bnx2x_cl45_write(bp, phy,  in bnx2x_set_xgxs_loopback()
6269 		bnx2x_cl45_write(bp, phy,  in bnx2x_set_xgxs_loopback()
6276 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_set_xgxs_loopback()
6285 		DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");  in bnx2x_set_xgxs_loopback()
6286 		bnx2x_cl45_read(bp, phy, 5,  in bnx2x_set_xgxs_loopback()
6290 		bnx2x_cl45_write(bp, phy, 5,  in bnx2x_set_xgxs_loopback()
6301 	u8 port = params->port;  in bnx2x_set_led()
6302 	u16 hw_led_mode = params->hw_led_mode;  in bnx2x_set_led()
6307 	struct bnx2x *bp = params->bp;  in bnx2x_set_led()
6308 	DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);  in bnx2x_set_led()
6309 	DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",  in bnx2x_set_led()
6313 		if (params->phy[phy_idx].set_link_led) {  in bnx2x_set_led()
6314 			params->phy[phy_idx].set_link_led(  in bnx2x_set_led()
6315 				&params->phy[phy_idx], params, mode);  in bnx2x_set_led()
6327 		if (params->phy[EXT_PHY1].type ==  in bnx2x_set_led()
6342 		if (!vars->link_up)  in bnx2x_set_led()
6346 		if (((params->phy[EXT_PHY1].type ==  in bnx2x_set_led()
6348 			 (params->phy[EXT_PHY1].type ==  in bnx2x_set_led()
6350 		    CHIP_IS_E2(bp) && params->num_phys == 2) {  in bnx2x_set_led()
6351 			/* This is a work-around for E2+8727 Configurations */  in bnx2x_set_led()
6369 			/* This is a work-around for HW issue found when link  in bnx2x_set_led()
6384 		} else if ((params->phy[EXT_PHY1].type ==  in bnx2x_set_led()
6396 			u32 nig_led_mode = ((params->hw_led_mode <<  in bnx2x_set_led()
6435 		rc = -EINVAL;  in bnx2x_set_led()
6436 		DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",  in bnx2x_set_led()
6450 	struct bnx2x *bp = params->bp;  in bnx2x_test_link()
6454 	struct bnx2x_phy *int_phy = &params->phy[INT_PHY];  in bnx2x_test_link()
6458 		if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]  in bnx2x_test_link()
6477 			return -ESRCH;  in bnx2x_test_link()
6483 		/* Link is up only if both local phy and external phy are up */  in bnx2x_test_link()
6485 			return -ESRCH;  in bnx2x_test_link()
6487 	/* In XGXS loopback mode, do not check external PHY */  in bnx2x_test_link()
6488 	if (params->loopback_mode == LOOPBACK_XGXS)  in bnx2x_test_link()
6491 	switch (params->num_phys) {  in bnx2x_test_link()
6493 		/* No external PHY */  in bnx2x_test_link()
6496 		ext_phy_link_up = params->phy[EXT_PHY1].read_status(  in bnx2x_test_link()
6497 			&params->phy[EXT_PHY1],  in bnx2x_test_link()
6501 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_test_link()
6503 			serdes_phy_type = ((params->phy[phy_index].media_type ==  in bnx2x_test_link()
6505 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6507 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6509 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6514 			if (params->phy[phy_index].read_status) {  in bnx2x_test_link()
6516 					params->phy[phy_index].read_status(  in bnx2x_test_link()
6517 						&params->phy[phy_index],  in bnx2x_test_link()
6525 	return -ESRCH;  in bnx2x_test_link()
6532 	struct bnx2x *bp = params->bp;  in bnx2x_link_initialize()
6533 	/* In case of external phy existence, the line speed would be the  in bnx2x_link_initialize()
6534 	 * line speed linked up by the external phy. In case it is direct  in bnx2x_link_initialize()
6538 	vars->line_speed = params->phy[INT_PHY].req_line_speed;  in bnx2x_link_initialize()
6540 	/* Initialize the internal phy in case this is a direct board  in bnx2x_link_initialize()
6541 	 * (no external phys), or this board has external phy which requires  in bnx2x_link_initialize()
6545 		bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);  in bnx2x_link_initialize()
6546 	/* init ext phy and enable link state int */  in bnx2x_link_initialize()
6548 		       (params->loopback_mode == LOOPBACK_XGXS));  in bnx2x_link_initialize()
6551 	    (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||  in bnx2x_link_initialize()
6552 	    (params->loopback_mode == LOOPBACK_EXT_PHY)) {  in bnx2x_link_initialize()
6553 		struct bnx2x_phy *phy = &params->phy[INT_PHY];  in bnx2x_link_initialize()  local
6554 		if (vars->line_speed == SPEED_AUTO_NEG &&  in bnx2x_link_initialize()
6557 			bnx2x_set_parallel_detection(phy, params);  in bnx2x_link_initialize()
6558 		if (params->phy[INT_PHY].config_init)  in bnx2x_link_initialize()
6559 			params->phy[INT_PHY].config_init(phy, params, vars);  in bnx2x_link_initialize()
6562 	/* Re-read this value in case it was changed inside config_init due to  in bnx2x_link_initialize()
6565 	vars->line_speed = params->phy[INT_PHY].req_line_speed;  in bnx2x_link_initialize()
6567 	/* Init external phy*/  in bnx2x_link_initialize()
6569 		if (params->phy[INT_PHY].supported &  in bnx2x_link_initialize()
6571 			vars->link_status |= LINK_STATUS_SERDES_LINK;  in bnx2x_link_initialize()
6573 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_initialize()
6575 			/* No need to initialize second phy in case of first  in bnx2x_link_initialize()
6576 			 * phy only selection. In case of second phy, we do  in bnx2x_link_initialize()
6577 			 * need to initialize the first phy, since they are  in bnx2x_link_initialize()
6580 			if (params->phy[phy_index].supported &  in bnx2x_link_initialize()
6582 				vars->link_status |= LINK_STATUS_SERDES_LINK;  in bnx2x_link_initialize()
6587 				DP(NETIF_MSG_LINK,  in bnx2x_link_initialize()
6588 				   "Not initializing second phy\n");  in bnx2x_link_initialize()
6591 			params->phy[phy_index].config_init(  in bnx2x_link_initialize()
6592 				&params->phy[phy_index],  in bnx2x_link_initialize()
6596 	/* Reset the interrupt indication after phy was initialized */  in bnx2x_link_initialize()
6598 		       params->port*4,  in bnx2x_link_initialize()
6606 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,  in bnx2x_int_link_reset()  argument
6610 	REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,  in bnx2x_int_link_reset()
6611 	       (0x1ff << (params->port*16)));  in bnx2x_int_link_reset()
6614 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,  in bnx2x_common_ext_link_reset()  argument
6617 	struct bnx2x *bp = params->bp;  in bnx2x_common_ext_link_reset()
6623 		gpio_port = params->port;  in bnx2x_common_ext_link_reset()
6630 	DP(NETIF_MSG_LINK, "reset external PHY\n");  in bnx2x_common_ext_link_reset()
6636 	struct bnx2x *bp = params->bp;  in bnx2x_update_link_down()
6637 	u8 port = params->port;  in bnx2x_update_link_down()
6639 	DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);  in bnx2x_update_link_down()
6641 	vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;  in bnx2x_update_link_down()
6643 	vars->mac_type = MAC_TYPE_NONE;  in bnx2x_update_link_down()
6646 	vars->link_status &= ~LINK_UPDATE_MASK;  in bnx2x_update_link_down()
6647 	vars->line_speed = 0;  in bnx2x_update_link_down()
6648 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_update_link_down()
6661 		bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);  in bnx2x_update_link_down()
6665 		REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),  in bnx2x_update_link_down()
6667 		REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),  in bnx2x_update_link_down()
6669 		vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |  in bnx2x_update_link_down()
6672 		bnx2x_update_mng_eee(params, vars->eee_status);  in bnx2x_update_link_down()
6684 	struct bnx2x *bp = params->bp;  in bnx2x_update_link_up()
6685 	u8 phy_idx, port = params->port;  in bnx2x_update_link_up()
6688 	vars->link_status |= (LINK_STATUS_LINK_UP |  in bnx2x_update_link_up()
6690 	vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;  in bnx2x_update_link_up()
6692 	if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)  in bnx2x_update_link_up()
6693 		vars->link_status |=  in bnx2x_update_link_up()
6696 	if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)  in bnx2x_update_link_up()
6697 		vars->link_status |=  in bnx2x_update_link_up()
6702 			    -ESRCH) {  in bnx2x_update_link_up()
6703 				DP(NETIF_MSG_LINK, "Found errors on XMAC\n");  in bnx2x_update_link_up()
6704 				vars->link_up = 0;  in bnx2x_update_link_up()
6705 				vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;  in bnx2x_update_link_up()
6706 				vars->link_status &= ~LINK_STATUS_LINK_UP;  in bnx2x_update_link_up()
6711 			      LED_MODE_OPER, vars->line_speed);  in bnx2x_update_link_up()
6713 		if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&  in bnx2x_update_link_up()
6714 		    (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {  in bnx2x_update_link_up()
6715 			DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");  in bnx2x_update_link_up()
6717 			       (params->port << 2), 1);  in bnx2x_update_link_up()
6720 			       (params->port << 2), 0xfc20);  in bnx2x_update_link_up()
6727 			    -ESRCH) {  in bnx2x_update_link_up()
6728 				DP(NETIF_MSG_LINK, "Found errors on BMAC\n");  in bnx2x_update_link_up()
6729 				vars->link_up = 0;  in bnx2x_update_link_up()
6730 				vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;  in bnx2x_update_link_up()
6731 				vars->link_status &= ~LINK_STATUS_LINK_UP;  in bnx2x_update_link_up()
6741 			if ((vars->link_status &  in bnx2x_update_link_up()
6743 			    && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&  in bnx2x_update_link_up()
6749 	/* PBF - link up */  in bnx2x_update_link_up()
6751 		rc |= bnx2x_pbf_update(params, vars->flow_ctrl,  in bnx2x_update_link_up()
6752 				       vars->line_speed);  in bnx2x_update_link_up()
6758 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_update_link_up()
6759 	bnx2x_update_mng_eee(params, vars->eee_status);  in bnx2x_update_link_up()
6762 		if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {  in bnx2x_update_link_up()
6773 	struct bnx2x *bp = params->bp;  in bnx2x_chng_link_count()
6780 	addr = params->shmem2_base +  in bnx2x_chng_link_count()
6781 		offsetof(struct shmem2_region, link_change_count[params->port]);  in bnx2x_chng_link_count()
6792  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6794  * - SINGLE_MEDIA - The link between the 577xx and the external
6795  *   phy (XGXS) need to up as well as the external link of the
6796  *   phy (PHY_EXT1)
6797  * - DUAL_MEDIA - The link between the 577xx and the first
6798  *   external phy needs to be up, and at least one of the 2
6799  *   external phy link must be up.
6803 	struct bnx2x *bp = params->bp;  in bnx2x_link_update()
6805 	u8 port = params->port;  in bnx2x_link_update()
6807 	u32 prev_link_status = vars->link_status;  in bnx2x_link_update()
6811 	u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;  in bnx2x_link_update()
6813 	vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;  in bnx2x_link_update()
6814 	vars->link_status &= ~LINK_UPDATE_MASK;  in bnx2x_link_update()
6815 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in bnx2x_link_update()
6825 		phy_vars[phy_index].eee_status = vars->eee_status;  in bnx2x_link_update()
6829 		bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);  in bnx2x_link_update()
6831 	DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",  in bnx2x_link_update()
6832 		 port, (vars->phy_flags & PHY_XGXS_FLAG),  in bnx2x_link_update()
6837 	DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",  in bnx2x_link_update()
6842 	DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",  in bnx2x_link_update()
6854 	 * vars argument is used since each phy may have different link/  in bnx2x_link_update()
6857 	for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_update()
6859 		struct bnx2x_phy *phy = &params->phy[phy_index];  in bnx2x_link_update()  local
6860 		if (!phy->read_status)  in bnx2x_link_update()
6862 		/* Read link status and params of this ext phy */  in bnx2x_link_update()
6863 		cur_link_up = phy->read_status(phy, params,  in bnx2x_link_update()
6866 			DP(NETIF_MSG_LINK, "phy in index %d link is up\n",  in bnx2x_link_update()
6869 			DP(NETIF_MSG_LINK, "phy in index %d link is down\n",  in bnx2x_link_update()
6881 			/* In this option, the first PHY makes sure to pass the  in bnx2x_link_update()
6884 			 * phy.  in bnx2x_link_update()
6889 			/* In this option, the first PHY makes sure to pass the  in bnx2x_link_update()
6890 			 * traffic through the second PHY.  in bnx2x_link_update()
6897 			 * - FIRST_PHY means that second phy wasn't initialized,  in bnx2x_link_update()
6899 			 * - SECOND_PHY means that first phy should not be able  in bnx2x_link_update()
6901 			 * - DEFAULT should be overridden during initialization  in bnx2x_link_update()
6903 				DP(NETIF_MSG_LINK, "Invalid link indication"  in bnx2x_link_update()
6905 					   params->multi_phy_config);  in bnx2x_link_update()
6911 	prev_line_speed = vars->line_speed;  in bnx2x_link_update()
6913 	 * Read the status of the internal phy. In case of  in bnx2x_link_update()
6916 	 * external phy  in bnx2x_link_update()
6918 	if (params->phy[INT_PHY].read_status)  in bnx2x_link_update()
6919 		params->phy[INT_PHY].read_status(  in bnx2x_link_update()
6920 			&params->phy[INT_PHY],  in bnx2x_link_update()
6924 	 * Otherwise, the active external phy flow control result is set  in bnx2x_link_update()
6926 	 * speed is different between the internal phy and external phy.  in bnx2x_link_update()
6930 		vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;  in bnx2x_link_update()
6932 		 * the external phy.  in bnx2x_link_update()
6934 		vars->link_status |= phy_vars[active_external_phy].link_status;  in bnx2x_link_update()
6936 		/* if active_external_phy is first PHY and link is up - disable  in bnx2x_link_update()
6937 		 * disable TX on second external PHY  in bnx2x_link_update()
6940 			if (params->phy[EXT_PHY2].phy_specific_func) {  in bnx2x_link_update()
6941 				DP(NETIF_MSG_LINK,  in bnx2x_link_update()
6943 				params->phy[EXT_PHY2].phy_specific_func(  in bnx2x_link_update()
6944 					&params->phy[EXT_PHY2],  in bnx2x_link_update()
6950 		vars->duplex = phy_vars[active_external_phy].duplex;  in bnx2x_link_update()
6951 		if (params->phy[active_external_phy].supported &  in bnx2x_link_update()
6953 			vars->link_status |= LINK_STATUS_SERDES_LINK;  in bnx2x_link_update()
6955 			vars->link_status &= ~LINK_STATUS_SERDES_LINK;  in bnx2x_link_update()
6957 		vars->eee_status = phy_vars[active_external_phy].eee_status;  in bnx2x_link_update()
6959 		DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",  in bnx2x_link_update()
6963 	for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_update()
6965 		if (params->phy[phy_index].flags &  in bnx2x_link_update()
6973 	DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"  in bnx2x_link_update()
6974 		   " ext_phy_line_speed = %d\n", vars->flow_ctrl,  in bnx2x_link_update()
6975 		   vars->link_status, ext_phy_line_speed);  in bnx2x_link_update()
6981 	if (vars->phy_link_up) {  in bnx2x_link_update()
6983 		    (ext_phy_line_speed != vars->line_speed)) {  in bnx2x_link_update()
6984 			DP(NETIF_MSG_LINK, "Internal link speed %d is"  in bnx2x_link_update()
6986 				   " link speed %d\n", vars->line_speed,  in bnx2x_link_update()
6988 			vars->phy_link_up = 0;  in bnx2x_link_update()
6989 		} else if (prev_line_speed != vars->line_speed) {  in bnx2x_link_update()
6990 			REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,  in bnx2x_link_update()
6997 	link_10g_plus = (vars->line_speed >= SPEED_10000);  in bnx2x_link_update()
7001 	/* In case external phy link is up, and internal link is down  in bnx2x_link_update()
7004 	 * Note that after link down-up as result of cable plug, the xgxs  in bnx2x_link_update()
7009 		DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"  in bnx2x_link_update()
7011 			   vars->phy_link_up,  in bnx2x_link_update()
7012 			   params->phy[EXT_PHY1].flags &  in bnx2x_link_update()
7014 		if (!(params->phy[EXT_PHY1].flags &  in bnx2x_link_update()
7016 		    && ext_phy_link_up && !vars->phy_link_up) {  in bnx2x_link_update()
7017 			vars->line_speed = ext_phy_line_speed;  in bnx2x_link_update()
7018 			if (vars->line_speed < SPEED_1000)  in bnx2x_link_update()
7019 				vars->phy_flags |= PHY_SGMII_FLAG;  in bnx2x_link_update()
7021 				vars->phy_flags &= ~PHY_SGMII_FLAG;  in bnx2x_link_update()
7023 			if (params->phy[INT_PHY].config_init)  in bnx2x_link_update()
7024 				params->phy[INT_PHY].config_init(  in bnx2x_link_update()
7025 					&params->phy[INT_PHY], params,  in bnx2x_link_update()
7029 	/* Link is up only if both local phy and external phy (in case of  in bnx2x_link_update()
7030 	 * non-direct board) are up and no fault detected on active PHY.  in bnx2x_link_update()
7032 	vars->link_up = (vars->phy_link_up &&  in bnx2x_link_update()
7038 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)  in bnx2x_link_update()
7039 		vars->link_status |= LINK_STATUS_PFC_ENABLED;  in bnx2x_link_update()
7041 		vars->link_status &= ~LINK_STATUS_PFC_ENABLED;  in bnx2x_link_update()
7043 	if (vars->link_up)  in bnx2x_link_update()
7048 	if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)  in bnx2x_link_update()
7052 	if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)  in bnx2x_link_update()
7059 /*			    External Phy section			     */
7073 	DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",  in bnx2x_save_spirom_version()
7081 				      struct bnx2x_phy *phy,  in bnx2x_save_bcm_spirom_ver()  argument
7086 	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_save_bcm_spirom_ver()
7088 	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_save_bcm_spirom_ver()
7091 				  phy->ver_addr);  in bnx2x_save_bcm_spirom_ver()
7095 				       struct bnx2x_phy *phy,  in bnx2x_ext_phy_10G_an_resolve()  argument
7099 	bnx2x_cl45_read(bp, phy,  in bnx2x_ext_phy_10G_an_resolve()
7102 	bnx2x_cl45_read(bp, phy,  in bnx2x_ext_phy_10G_an_resolve()
7106 		vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;  in bnx2x_ext_phy_10G_an_resolve()
7108 		vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;  in bnx2x_ext_phy_10G_an_resolve()
7112 /*		common BCM8073/BCM8727 PHY SECTION		  */
7114 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,  in bnx2x_8073_resolve_fc()  argument
7118 	struct bnx2x *bp = params->bp;  in bnx2x_8073_resolve_fc()
7119 	if (phy->req_line_speed == SPEED_10 ||  in bnx2x_8073_resolve_fc()
7120 	    phy->req_line_speed == SPEED_100) {  in bnx2x_8073_resolve_fc()
7121 		vars->flow_ctrl = phy->req_flow_ctrl;  in bnx2x_8073_resolve_fc()
7125 	if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&  in bnx2x_8073_resolve_fc()
7126 	    (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {  in bnx2x_8073_resolve_fc()
7130 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_resolve_fc()
7134 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_resolve_fc()
7142 		bnx2x_pause_resolve(phy, params, vars, pause_result);  in bnx2x_8073_resolve_fc()
7143 		DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",  in bnx2x_8073_resolve_fc()
7148 					     struct bnx2x_phy *phy,  in bnx2x_8073_8727_external_rom_boot()  argument
7157 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7163 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7168 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7173 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7179 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7184 	/* Delay 100ms per the PHY specifications */  in bnx2x_8073_8727_external_rom_boot()
7191 			DP(NETIF_MSG_LINK,  in bnx2x_8073_8727_external_rom_boot()
7195 			rc = -EINVAL;  in bnx2x_8073_8727_external_rom_boot()
7199 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7202 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7208 			((fw_msgout & 0xff) != 0x03 && (phy->type ==  in bnx2x_8073_8727_external_rom_boot()
7212 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_8727_external_rom_boot()
7215 	bnx2x_save_bcm_spirom_ver(bp, phy, port);  in bnx2x_8073_8727_external_rom_boot()
7217 	DP(NETIF_MSG_LINK,  in bnx2x_8073_8727_external_rom_boot()
7226 /*			BCM8073 PHY SECTION			  */
7228 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)  in bnx2x_8073_is_snr_needed()  argument
7234 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_is_snr_needed()
7243 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_is_snr_needed()
7254 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)  in bnx2x_8073_xaui_wa()  argument
7258 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_xaui_wa()
7273 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_xaui_wa()
7278 		   * system initialization (XAUI work-around not required, as  in bnx2x_8073_xaui_wa()
7282 			DP(NETIF_MSG_LINK, "XAUI work-around not required\n");  in bnx2x_8073_xaui_wa()
7285 			DP(NETIF_MSG_LINK, "bit 15 went off\n");  in bnx2x_8073_xaui_wa()
7292 				bnx2x_cl45_read(bp, phy,  in bnx2x_8073_xaui_wa()
7296 					DP(NETIF_MSG_LINK,  in bnx2x_8073_xaui_wa()
7306 	DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");  in bnx2x_8073_xaui_wa()
7307 	return -EINVAL;  in bnx2x_8073_xaui_wa()
7310 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)  in bnx2x_807x_force_10G()  argument
7313 	bnx2x_cl45_write(bp, phy,  in bnx2x_807x_force_10G()
7315 	bnx2x_cl45_write(bp, phy,  in bnx2x_807x_force_10G()
7317 	bnx2x_cl45_write(bp, phy,  in bnx2x_807x_force_10G()
7319 	bnx2x_cl45_write(bp, phy,  in bnx2x_807x_force_10G()
7324 				      struct bnx2x_phy *phy,  in bnx2x_8073_set_pause_cl37()  argument
7328 	struct bnx2x *bp = params->bp;  in bnx2x_8073_set_pause_cl37()
7329 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_set_pause_cl37()
7333 	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */  in bnx2x_8073_set_pause_cl37()
7334 	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in bnx2x_8073_set_pause_cl37()
7335 	if ((vars->ieee_fc &  in bnx2x_8073_set_pause_cl37()
7340 	if ((vars->ieee_fc &  in bnx2x_8073_set_pause_cl37()
7345 	if ((vars->ieee_fc &  in bnx2x_8073_set_pause_cl37()
7350 	DP(NETIF_MSG_LINK,  in bnx2x_8073_set_pause_cl37()
7351 		 "Ext phy AN advertize cl37 0x%x\n", cl37_val);  in bnx2x_8073_set_pause_cl37()
7353 	bnx2x_cl45_write(bp, phy,  in bnx2x_8073_set_pause_cl37()
7358 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,  in bnx2x_8073_specific_func()  argument
7362 	struct bnx2x *bp = params->bp;  in bnx2x_8073_specific_func()
7366 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_specific_func()
7368 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_specific_func()
7374 static void bnx2x_8073_config_init(struct bnx2x_phy *phy,  in bnx2x_8073_config_init()  argument
7378 	struct bnx2x *bp = params->bp;  in bnx2x_8073_config_init()
7381 	DP(NETIF_MSG_LINK, "Init 8073\n");  in bnx2x_8073_config_init()
7386 		gpio_port = params->port;  in bnx2x_8073_config_init()
7394 	bnx2x_8073_specific_func(phy, params, PHY_INIT);  in bnx2x_8073_config_init()
7395 	bnx2x_8073_set_pause_cl37(params, phy, vars);  in bnx2x_8073_config_init()
7397 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_config_init()
7400 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_config_init()
7403 	DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);  in bnx2x_8073_config_init()
7405 	/* Swap polarity if required - Must be done only in non-1G mode */  in bnx2x_8073_config_init()
7406 	if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {  in bnx2x_8073_config_init()
7408 		DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");  in bnx2x_8073_config_init()
7410 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_config_init()
7413 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_config_init()
7421 	if (REG_RD(bp, params->shmem_base +  in bnx2x_8073_config_init()
7423 				  port_hw_config[params->port].default_cfg)) &  in bnx2x_8073_config_init()
7426 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_config_init()
7429 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_config_init()
7432 		DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");  in bnx2x_8073_config_init()
7434 	if (params->loopback_mode == LOOPBACK_EXT) {  in bnx2x_8073_config_init()
7435 		bnx2x_807x_force_10G(bp, phy);  in bnx2x_8073_config_init()
7436 		DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");  in bnx2x_8073_config_init()
7439 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_config_init()
7442 	if (phy->req_line_speed != SPEED_AUTO_NEG) {  in bnx2x_8073_config_init()
7443 		if (phy->req_line_speed == SPEED_10000) {  in bnx2x_8073_config_init()
7445 		} else if (phy->req_line_speed ==  SPEED_2500) {  in bnx2x_8073_config_init()
7454 		if (phy->speed_cap_mask &  in bnx2x_8073_config_init()
7459 		if (phy->speed_cap_mask &  in bnx2x_8073_config_init()
7463 		DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);  in bnx2x_8073_config_init()
7466 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);  in bnx2x_8073_config_init()
7467 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);  in bnx2x_8073_config_init()
7469 	if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&  in bnx2x_8073_config_init()
7470 	     (phy->req_line_speed == SPEED_AUTO_NEG)) ||  in bnx2x_8073_config_init()
7471 	    (phy->req_line_speed == SPEED_2500)) {  in bnx2x_8073_config_init()
7474 		bnx2x_cl45_read(bp, phy,  in bnx2x_8073_config_init()
7477 		DP(NETIF_MSG_LINK, "Add 2.5G\n");  in bnx2x_8073_config_init()
7483 		DP(NETIF_MSG_LINK, "Disable 2.5G\n");  in bnx2x_8073_config_init()
7487 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);  in bnx2x_8073_config_init()
7490 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);  in bnx2x_8073_config_init()
7491 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,  in bnx2x_8073_config_init()
7492 			 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?  in bnx2x_8073_config_init()
7496 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);  in bnx2x_8073_config_init()
7502 	if (bnx2x_8073_is_snr_needed(bp, phy))  in bnx2x_8073_config_init()
7503 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_config_init()
7508 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);  in bnx2x_8073_config_init()
7510 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);  in bnx2x_8073_config_init()
7512 	bnx2x_ext_phy_set_pause(params, phy, vars);  in bnx2x_8073_config_init()
7516 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);  in bnx2x_8073_config_init()
7517 	DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",  in bnx2x_8073_config_init()
7521 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,  in bnx2x_8073_read_status()  argument
7525 	struct bnx2x *bp = params->bp;  in bnx2x_8073_read_status()
7531 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7534 	DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);  in bnx2x_8073_read_status()
7537 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7539 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7541 	DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);  in bnx2x_8073_read_status()
7542 	/* Clear MSG-OUT */  in bnx2x_8073_read_status()
7543 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7547 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7550 	DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);  in bnx2x_8073_read_status()
7553 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7555 	DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);  in bnx2x_8073_read_status()
7557 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7559 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7562 	DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);  in bnx2x_8073_read_status()
7565 	     ((phy->req_line_speed != SPEED_10000))) {  in bnx2x_8073_read_status()
7566 		if (bnx2x_8073_xaui_wa(bp, phy) != 0)  in bnx2x_8073_read_status()
7569 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7571 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7575 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7577 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7579 	DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"  in bnx2x_8073_read_status()
7583 	if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {  in bnx2x_8073_read_status()
7588 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_read_status()
7593 		bnx2x_cl45_write(bp, phy,  in bnx2x_8073_read_status()
7597 	bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7601 	/* Bits 0..2 --> speed detected, bits 13..15--> link is down */  in bnx2x_8073_read_status()
7604 		vars->line_speed = SPEED_10000;  in bnx2x_8073_read_status()
7605 		DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",  in bnx2x_8073_read_status()
7606 			   params->port);  in bnx2x_8073_read_status()
7609 		vars->line_speed = SPEED_2500;  in bnx2x_8073_read_status()
7610 		DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",  in bnx2x_8073_read_status()
7611 			   params->port);  in bnx2x_8073_read_status()
7614 		vars->line_speed = SPEED_1000;  in bnx2x_8073_read_status()
7615 		DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",  in bnx2x_8073_read_status()
7616 			   params->port);  in bnx2x_8073_read_status()
7619 		DP(NETIF_MSG_LINK, "port %x: External link is down\n",  in bnx2x_8073_read_status()
7620 			   params->port);  in bnx2x_8073_read_status()
7625 		if (params->lane_config &  in bnx2x_8073_read_status()
7628 			bnx2x_cl45_read(bp, phy,  in bnx2x_8073_read_status()
7634 			if (vars->line_speed == SPEED_1000) {  in bnx2x_8073_read_status()
7635 				DP(NETIF_MSG_LINK, "Swapping 1G polarity for"  in bnx2x_8073_read_status()
7641 			bnx2x_cl45_write(bp, phy,  in bnx2x_8073_read_status()
7646 		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);  in bnx2x_8073_read_status()
7647 		bnx2x_8073_resolve_fc(phy, params, vars);  in bnx2x_8073_read_status()
7648 		vars->duplex = DUPLEX_FULL;  in bnx2x_8073_read_status()
7651 	if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {  in bnx2x_8073_read_status()
7652 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_8073_read_status()
7656 			vars->link_status |=  in bnx2x_8073_read_status()
7659 			vars->link_status |=  in bnx2x_8073_read_status()
7666 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,  in bnx2x_8073_link_reset()  argument
7669 	struct bnx2x *bp = params->bp;  in bnx2x_8073_link_reset()
7674 		gpio_port = params->port;  in bnx2x_8073_link_reset()
7675 	DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",  in bnx2x_8073_link_reset()
7683 /*			BCM8705 PHY SECTION			  */
7685 static void bnx2x_8705_config_init(struct bnx2x_phy *phy,  in bnx2x_8705_config_init()  argument
7689 	struct bnx2x *bp = params->bp;  in bnx2x_8705_config_init()
7690 	DP(NETIF_MSG_LINK, "init 8705\n");  in bnx2x_8705_config_init()
7693 		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);  in bnx2x_8705_config_init()
7695 	bnx2x_ext_phy_hw_reset(bp, params->port);  in bnx2x_8705_config_init()
7696 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in bnx2x_8705_config_init()
7697 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_8705_config_init()
7699 	bnx2x_cl45_write(bp, phy,  in bnx2x_8705_config_init()
7701 	bnx2x_cl45_write(bp, phy,  in bnx2x_8705_config_init()
7703 	bnx2x_cl45_write(bp, phy,  in bnx2x_8705_config_init()
7705 	bnx2x_cl45_write(bp, phy,  in bnx2x_8705_config_init()
7708 	bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);  in bnx2x_8705_config_init()
7711 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,  in bnx2x_8705_read_status()  argument
7717 	struct bnx2x *bp = params->bp;  in bnx2x_8705_read_status()
7718 	DP(NETIF_MSG_LINK, "read status 8705\n");  in bnx2x_8705_read_status()
7719 	bnx2x_cl45_read(bp, phy,  in bnx2x_8705_read_status()
7721 	DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);  in bnx2x_8705_read_status()
7723 	bnx2x_cl45_read(bp, phy,  in bnx2x_8705_read_status()
7725 	DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);  in bnx2x_8705_read_status()
7727 	bnx2x_cl45_read(bp, phy,  in bnx2x_8705_read_status()
7730 	bnx2x_cl45_read(bp, phy,  in bnx2x_8705_read_status()
7732 	bnx2x_cl45_read(bp, phy,  in bnx2x_8705_read_status()
7735 	DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);  in bnx2x_8705_read_status()
7738 		vars->line_speed = SPEED_10000;  in bnx2x_8705_read_status()
7739 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_8705_read_status()
7748 					   struct bnx2x_phy *phy,  in bnx2x_set_disable_pmd_transmit()  argument
7751 	struct bnx2x *bp = params->bp;  in bnx2x_set_disable_pmd_transmit()
7756 		if (params->feature_config_flags &  in bnx2x_set_disable_pmd_transmit()
7758 			DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");  in bnx2x_set_disable_pmd_transmit()
7760 			DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");  in bnx2x_set_disable_pmd_transmit()
7764 		DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");  in bnx2x_set_disable_pmd_transmit()
7765 	bnx2x_cl45_write(bp, phy,  in bnx2x_set_disable_pmd_transmit()
7774 	struct bnx2x *bp = params->bp;  in bnx2x_get_gpio_port()
7778 		gpio_port = params->port;  in bnx2x_get_gpio_port()
7785 					   struct bnx2x_phy *phy,  in bnx2x_sfp_e1e2_set_transmitter()  argument
7789 	u8 port = params->port;  in bnx2x_sfp_e1e2_set_transmitter()
7790 	struct bnx2x *bp = params->bp;  in bnx2x_sfp_e1e2_set_transmitter()
7794 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_e1e2_set_transmitter()
7798 	DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "  in bnx2x_sfp_e1e2_set_transmitter()
7803 		bnx2x_cl45_read(bp, phy,  in bnx2x_sfp_e1e2_set_transmitter()
7813 		bnx2x_cl45_write(bp, phy,  in bnx2x_sfp_e1e2_set_transmitter()
7830 		gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;  in bnx2x_sfp_e1e2_set_transmitter()
7836 		DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);  in bnx2x_sfp_e1e2_set_transmitter()
7842 				      struct bnx2x_phy *phy,  in bnx2x_sfp_set_transmitter()  argument
7845 	struct bnx2x *bp = params->bp;  in bnx2x_sfp_set_transmitter()
7846 	DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);  in bnx2x_sfp_set_transmitter()
7848 		bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);  in bnx2x_sfp_set_transmitter()
7850 		bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);  in bnx2x_sfp_set_transmitter()
7853 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,  in bnx2x_8726_read_sfp_module_eeprom()  argument
7858 	struct bnx2x *bp = params->bp;  in bnx2x_8726_read_sfp_module_eeprom()
7862 		DP(NETIF_MSG_LINK,  in bnx2x_8726_read_sfp_module_eeprom()
7864 		return -EINVAL;  in bnx2x_8726_read_sfp_module_eeprom()
7867 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7872 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7877 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7883 		bnx2x_cl45_read(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7894 		DP(NETIF_MSG_LINK,  in bnx2x_8726_read_sfp_module_eeprom()
7897 		return -EINVAL;  in bnx2x_8726_read_sfp_module_eeprom()
7902 		bnx2x_cl45_read(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7909 		bnx2x_cl45_read(bp, phy,  in bnx2x_8726_read_sfp_module_eeprom()
7917 	return -EINVAL;  in bnx2x_8726_read_sfp_module_eeprom()
7924 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_power_module()
7926 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_warpcore_power_module()
7928 			dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &  in bnx2x_warpcore_power_module()
7934 	DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",  in bnx2x_warpcore_power_module()
7941 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,  in bnx2x_warpcore_read_sfp_module_eeprom()  argument
7951 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_read_sfp_module_eeprom()
7954 		DP(NETIF_MSG_LINK,  in bnx2x_warpcore_read_sfp_module_eeprom()
7956 		return -EINVAL;  in bnx2x_warpcore_read_sfp_module_eeprom()
7973 		for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {  in bnx2x_warpcore_read_sfp_module_eeprom()
7982 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,  in bnx2x_8727_read_sfp_module_eeprom()  argument
7987 	struct bnx2x *bp = params->bp;  in bnx2x_8727_read_sfp_module_eeprom()
7991 		DP(NETIF_MSG_LINK,  in bnx2x_8727_read_sfp_module_eeprom()
7993 		return -EINVAL;  in bnx2x_8727_read_sfp_module_eeprom()
7996 	/* Set 2-wire transfer rate of SFP+ module EEPROM  in bnx2x_8727_read_sfp_module_eeprom()
8000 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8006 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8012 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8018 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8023 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8029 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8033 	/* Wait appropriate time for two-wire command to finish before  in bnx2x_8727_read_sfp_module_eeprom()
8040 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8051 		DP(NETIF_MSG_LINK,  in bnx2x_8727_read_sfp_module_eeprom()
8054 		return -EFAULT;  in bnx2x_8727_read_sfp_module_eeprom()
8059 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8066 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_sfp_module_eeprom()
8075 	return -EINVAL;  in bnx2x_8727_read_sfp_module_eeprom()
8077 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,  in bnx2x_read_sfp_module_eeprom()  argument
8082 	struct bnx2x *bp = params->bp;  in bnx2x_read_sfp_module_eeprom()
8088 		DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);  in bnx2x_read_sfp_module_eeprom()
8089 		return -EINVAL;  in bnx2x_read_sfp_module_eeprom()
8092 	switch (phy->type) {  in bnx2x_read_sfp_module_eeprom()
8104 		return -EOPNOTSUPP;  in bnx2x_read_sfp_module_eeprom()
8110 		rc = read_func(phy, params, dev_addr, addr, xfer_size,  in bnx2x_read_sfp_module_eeprom()
8112 		byte_cnt -= xfer_size;  in bnx2x_read_sfp_module_eeprom()
8119 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,  in bnx2x_get_edc_mode()  argument
8123 	struct bnx2x *bp = params->bp;  in bnx2x_get_edc_mode()
8127 	phy->media_type = ETH_PHY_UNSPECIFIED;  in bnx2x_get_edc_mode()
8129 	if (bnx2x_read_sfp_module_eeprom(phy,  in bnx2x_get_edc_mode()
8135 		DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");  in bnx2x_get_edc_mode()
8136 		return -EINVAL;  in bnx2x_get_edc_mode()
8138 	params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;  in bnx2x_get_edc_mode()
8139 	params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<  in bnx2x_get_edc_mode()
8141 	bnx2x_update_link_attr(params, params->link_attr_sync);  in bnx2x_get_edc_mode()
8146 		phy->media_type = ETH_PHY_DA_TWINAX;  in bnx2x_get_edc_mode()
8154 			DP(NETIF_MSG_LINK, "Active Copper cable detected\n");  in bnx2x_get_edc_mode()
8155 			if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in bnx2x_get_edc_mode()
8167 				DP(NETIF_MSG_LINK,  in bnx2x_get_edc_mode()
8170 				DP(NETIF_MSG_LINK,  in bnx2x_get_edc_mode()
8171 				   "Unknown copper-cable-type\n");  in bnx2x_get_edc_mode()
8185 			DP(NETIF_MSG_LINK, "1G SFP module detected\n");  in bnx2x_get_edc_mode()
8186 			phy->media_type = ETH_PHY_SFP_1G_FIBER;  in bnx2x_get_edc_mode()
8187 			if (phy->req_line_speed != SPEED_1000) {  in bnx2x_get_edc_mode()
8188 				u8 gport = params->port;  in bnx2x_get_edc_mode()
8189 				phy->req_line_speed = SPEED_1000;  in bnx2x_get_edc_mode()
8192 					(params->port << 1);  in bnx2x_get_edc_mode()
8194 				netdev_err(bp->dev,  in bnx2x_get_edc_mode()
8200 				bnx2x_sfp_set_transmitter(params, phy, 0);  in bnx2x_get_edc_mode()
8202 				bnx2x_sfp_set_transmitter(params, phy, 1);  in bnx2x_get_edc_mode()
8206 			DP(NETIF_MSG_LINK, "10G Optic module detected\n");  in bnx2x_get_edc_mode()
8208 				if (params->phy[idx].type == phy->type) {  in bnx2x_get_edc_mode()
8213 			phy->media_type = ETH_PHY_SFPP_10G_FIBER;  in bnx2x_get_edc_mode()
8214 			phy->req_line_speed = params->req_line_speed[cfg_idx];  in bnx2x_get_edc_mode()
8218 		DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",  in bnx2x_get_edc_mode()
8220 		return -EINVAL;  in bnx2x_get_edc_mode()
8222 	sync_offset = params->shmem_base +  in bnx2x_get_edc_mode()
8224 			 dev_info.port_hw_config[params->port].media_type);  in bnx2x_get_edc_mode()
8226 	/* Update media type for non-PMF sync */  in bnx2x_get_edc_mode()
8228 		if (&(params->phy[phy_idx]) == phy) {  in bnx2x_get_edc_mode()
8231 			media_types |= ((phy->media_type &  in bnx2x_get_edc_mode()
8240 		if (bnx2x_read_sfp_module_eeprom(phy,  in bnx2x_get_edc_mode()
8246 			DP(NETIF_MSG_LINK,  in bnx2x_get_edc_mode()
8248 			return -EINVAL;  in bnx2x_get_edc_mode()
8255 	DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);  in bnx2x_get_edc_mode()
8261 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,  in bnx2x_verify_sfp_module()  argument
8264 	struct bnx2x *bp = params->bp;  in bnx2x_verify_sfp_module()
8269 	phy->flags &= ~FLAGS_SFP_NOT_APPROVED;  in bnx2x_verify_sfp_module()
8270 	val = REG_RD(bp, params->shmem_base +  in bnx2x_verify_sfp_module()
8272 				  port_feature_config[params->port].config));  in bnx2x_verify_sfp_module()
8275 		DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");  in bnx2x_verify_sfp_module()
8279 	if (params->feature_config_flags &  in bnx2x_verify_sfp_module()
8281 		/* Use specific phy request */  in bnx2x_verify_sfp_module()
8283 	} else if (params->feature_config_flags &  in bnx2x_verify_sfp_module()
8285 		/* Use first phy request only in case of non-dual media*/  in bnx2x_verify_sfp_module()
8287 			DP(NETIF_MSG_LINK,  in bnx2x_verify_sfp_module()
8289 			return -EINVAL;  in bnx2x_verify_sfp_module()
8294 		DP(NETIF_MSG_LINK,  in bnx2x_verify_sfp_module()
8296 		return -EINVAL;  in bnx2x_verify_sfp_module()
8299 	fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);  in bnx2x_verify_sfp_module()
8302 		DP(NETIF_MSG_LINK, "Approved module\n");  in bnx2x_verify_sfp_module()
8307 	if (bnx2x_read_sfp_module_eeprom(phy,  in bnx2x_verify_sfp_module()
8316 	if (bnx2x_read_sfp_module_eeprom(phy,  in bnx2x_verify_sfp_module()
8326 	netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"  in bnx2x_verify_sfp_module()
8328 			 params->port, vendor_name, vendor_pn);  in bnx2x_verify_sfp_module()
8331 		phy->flags |= FLAGS_SFP_NOT_APPROVED;  in bnx2x_verify_sfp_module()
8332 	return -EINVAL;  in bnx2x_verify_sfp_module()
8335 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,  in bnx2x_wait_for_sfp_module_initialized()  argument
8341 	struct bnx2x *bp = params->bp;  in bnx2x_wait_for_sfp_module_initialized()
8343 	/* Initialization time after hot-plug may take up to 300ms for  in bnx2x_wait_for_sfp_module_initialized()
8348 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)  in bnx2x_wait_for_sfp_module_initialized()
8350 				phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,  in bnx2x_wait_for_sfp_module_initialized()
8353 			rc = bnx2x_read_sfp_module_eeprom(phy, params,  in bnx2x_wait_for_sfp_module_initialized()
8357 			DP(NETIF_MSG_LINK,  in bnx2x_wait_for_sfp_module_initialized()
8364 	rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,  in bnx2x_wait_for_sfp_module_initialized()
8370 				    struct bnx2x_phy *phy,  in bnx2x_8727_power_module()  argument
8377 	 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0  in bnx2x_8727_power_module()
8378 	 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1  in bnx2x_8727_power_module()
8379 	 * where the 1st bit is the over-current(only input), and 2nd bit is  in bnx2x_8727_power_module()
8383 	 *  as input to enable listening of over-current indication  in bnx2x_8727_power_module()
8385 	if (phy->flags & FLAGS_NOC)  in bnx2x_8727_power_module()
8395 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_power_module()
8402 					struct bnx2x_phy *phy,  in bnx2x_8726_set_limiting_mode()  argument
8407 	bnx2x_cl45_read(bp, phy,  in bnx2x_8726_set_limiting_mode()
8411 	DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",  in bnx2x_8726_set_limiting_mode()
8415 		DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");  in bnx2x_8726_set_limiting_mode()
8416 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_set_limiting_mode()
8422 		DP(NETIF_MSG_LINK, "Setting LRM MODE\n");  in bnx2x_8726_set_limiting_mode()
8430 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_set_limiting_mode()
8434 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_set_limiting_mode()
8438 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_set_limiting_mode()
8442 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_set_limiting_mode()
8451 					struct bnx2x_phy *phy,  in bnx2x_8727_set_limiting_mode()  argument
8456 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_set_limiting_mode()
8461 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_set_limiting_mode()
8466 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_set_limiting_mode()
8470 	/* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */  in bnx2x_8727_set_limiting_mode()
8471 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_set_limiting_mode()
8476 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_set_limiting_mode()
8484 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,  in bnx2x_8727_specific_func()  argument
8488 	struct bnx2x *bp = params->bp;  in bnx2x_8727_specific_func()
8492 		bnx2x_sfp_set_transmitter(params, phy, 0);  in bnx2x_8727_specific_func()
8495 		if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))  in bnx2x_8727_specific_func()
8496 			bnx2x_sfp_set_transmitter(params, phy, 1);  in bnx2x_8727_specific_func()
8499 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_specific_func()
8502 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_specific_func()
8505 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_specific_func()
8508 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_8727_specific_func()
8512 		if (phy->flags & FLAGS_NOC)  in bnx2x_8727_specific_func()
8515 		 * status which reflect SFP+ module over-current  in bnx2x_8727_specific_func()
8517 		if (!(phy->flags & FLAGS_NOC))  in bnx2x_8727_specific_func()
8518 			val &= 0xff8f; /* Reset bits 4-6 */  in bnx2x_8727_specific_func()
8519 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_specific_func()
8524 		DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",  in bnx2x_8727_specific_func()
8533 	struct bnx2x *bp = params->bp;  in bnx2x_set_e1e2_module_fault_led()
8535 	u32 fault_led_gpio = REG_RD(bp, params->shmem_base +  in bnx2x_set_e1e2_module_fault_led()
8537 			dev_info.port_hw_config[params->port].sfp_ctrl)) &  in bnx2x_set_e1e2_module_fault_led()
8548 		u16 gpio_pin = fault_led_gpio -  in bnx2x_set_e1e2_module_fault_led()
8550 		DP(NETIF_MSG_LINK, "Set fault module-detected led "  in bnx2x_set_e1e2_module_fault_led()
8557 		DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",  in bnx2x_set_e1e2_module_fault_led()
8566 	u8 port = params->port;  in bnx2x_set_e3_module_fault_led()
8567 	struct bnx2x *bp = params->bp;  in bnx2x_set_e3_module_fault_led()
8568 	pin_cfg = (REG_RD(bp, params->shmem_base +  in bnx2x_set_e3_module_fault_led()
8573 	DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",  in bnx2x_set_e3_module_fault_led()
8581 	struct bnx2x *bp = params->bp;  in bnx2x_set_sfp_module_fault_led()
8582 	DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);  in bnx2x_set_sfp_module_fault_led()
8592 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,  in bnx2x_warpcore_hw_reset()  argument
8595 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_hw_reset()
8607 				   struct bnx2x_phy *phy,  in bnx2x_power_sfp_module()  argument
8610 	struct bnx2x *bp = params->bp;  in bnx2x_power_sfp_module()
8611 	DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);  in bnx2x_power_sfp_module()
8613 	switch (phy->type) {  in bnx2x_power_sfp_module()
8616 		bnx2x_8727_power_module(params->bp, phy, power);  in bnx2x_power_sfp_module()
8626 					     struct bnx2x_phy *phy,  in bnx2x_warpcore_set_limiting_mode()  argument
8631 	struct bnx2x *bp = params->bp;  in bnx2x_warpcore_set_limiting_mode()
8633 	u8 lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_warpcore_set_limiting_mode()
8635 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_limiting_mode()
8653 	bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_limiting_mode()
8656 	bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_warpcore_set_limiting_mode()
8659 	/* Restart microcode to re-read the new mode */  in bnx2x_warpcore_set_limiting_mode()
8660 	bnx2x_warpcore_reset_lane(bp, phy, 1);  in bnx2x_warpcore_set_limiting_mode()
8661 	bnx2x_warpcore_reset_lane(bp, phy, 0);  in bnx2x_warpcore_set_limiting_mode()
8666 				    struct bnx2x_phy *phy,  in bnx2x_set_limiting_mode()  argument
8669 	switch (phy->type) {  in bnx2x_set_limiting_mode()
8671 		bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);  in bnx2x_set_limiting_mode()
8675 		bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);  in bnx2x_set_limiting_mode()
8678 		bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);  in bnx2x_set_limiting_mode()
8683 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,  in bnx2x_sfp_module_detection()  argument
8686 	struct bnx2x *bp = params->bp;  in bnx2x_sfp_module_detection()
8690 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_sfp_module_detection()
8692 				     port_feature_config[params->port].config));  in bnx2x_sfp_module_detection()
8694 	bnx2x_sfp_set_transmitter(params, phy, 1);  in bnx2x_sfp_module_detection()
8695 	DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",  in bnx2x_sfp_module_detection()
8696 		 params->port);  in bnx2x_sfp_module_detection()
8698 	bnx2x_power_sfp_module(params, phy, 1);  in bnx2x_sfp_module_detection()
8699 	if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {  in bnx2x_sfp_module_detection()
8700 		DP(NETIF_MSG_LINK, "Failed to get valid module type\n");  in bnx2x_sfp_module_detection()
8701 		return -EINVAL;  in bnx2x_sfp_module_detection()
8702 	} else if (bnx2x_verify_sfp_module(phy, params) != 0) {  in bnx2x_sfp_module_detection()
8704 		DP(NETIF_MSG_LINK, "Module verification failed!!\n");  in bnx2x_sfp_module_detection()
8705 		rc = -EINVAL;  in bnx2x_sfp_module_detection()
8706 		/* Turn on fault module-detected led */  in bnx2x_sfp_module_detection()
8713 			DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");  in bnx2x_sfp_module_detection()
8714 			bnx2x_power_sfp_module(params, phy, 0);  in bnx2x_sfp_module_detection()
8718 		/* Turn off fault module-detected led */  in bnx2x_sfp_module_detection()
8725 	bnx2x_set_limiting_mode(params, phy, edc_mode);  in bnx2x_sfp_module_detection()
8733 		bnx2x_sfp_set_transmitter(params, phy, 0);  in bnx2x_sfp_module_detection()
8740 	struct bnx2x *bp = params->bp;  in bnx2x_handle_module_detect_int()
8741 	struct bnx2x_phy *phy;  in bnx2x_handle_module_detect_int()  local
8745 		phy = &params->phy[INT_PHY];  in bnx2x_handle_module_detect_int()
8747 		bnx2x_sfp_set_transmitter(params, phy, 1);  in bnx2x_handle_module_detect_int()
8749 		phy = &params->phy[EXT_PHY1];  in bnx2x_handle_module_detect_int()
8751 	if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,  in bnx2x_handle_module_detect_int()
8752 				      params->port, &gpio_num, &gpio_port) ==  in bnx2x_handle_module_detect_int()
8753 	    -EINVAL) {  in bnx2x_handle_module_detect_int()
8754 		DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");  in bnx2x_handle_module_detect_int()
8767 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_handle_module_detect_int()
8769 		bnx2x_power_sfp_module(params, phy, 1);  in bnx2x_handle_module_detect_int()
8773 		if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {  in bnx2x_handle_module_detect_int()
8774 			bnx2x_sfp_module_detection(phy, params);  in bnx2x_handle_module_detect_int()
8781 				bnx2x_cl45_read(bp, phy,  in bnx2x_handle_module_detect_int()
8786 				    (params->link_flags &  in bnx2x_handle_module_detect_int()
8788 					bnx2x_warpcore_reset_lane(bp, phy, 1);  in bnx2x_handle_module_detect_int()
8789 					bnx2x_warpcore_config_sfi(phy, params);  in bnx2x_handle_module_detect_int()
8790 					bnx2x_warpcore_reset_lane(bp, phy, 0);  in bnx2x_handle_module_detect_int()
8794 			DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");  in bnx2x_handle_module_detect_int()
8803 		phy->media_type = ETH_PHY_NOT_PRESENT;  in bnx2x_handle_module_detect_int()
8811 				 struct bnx2x_phy *phy,  in bnx2x_sfp_mask_fault()  argument
8816 	bnx2x_cl45_read(bp, phy,  in bnx2x_sfp_mask_fault()
8819 	bnx2x_cl45_read(bp, phy,  in bnx2x_sfp_mask_fault()
8823 	bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);  in bnx2x_sfp_mask_fault()
8828 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);  in bnx2x_sfp_mask_fault()
8831 /*		common BCM8706/BCM8726 PHY SECTION		  */
8833 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,  in bnx2x_8706_8726_read_status()  argument
8839 	struct bnx2x *bp = params->bp;  in bnx2x_8706_8726_read_status()
8840 	DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");  in bnx2x_8706_8726_read_status()
8842 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8845 	bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,  in bnx2x_8706_8726_read_status()
8849 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8851 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8853 	DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);  in bnx2x_8706_8726_read_status()
8855 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8857 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8859 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8861 	bnx2x_cl45_read(bp, phy,  in bnx2x_8706_8726_read_status()
8864 	DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"  in bnx2x_8706_8726_read_status()
8872 			vars->line_speed = SPEED_1000;  in bnx2x_8706_8726_read_status()
8874 			vars->line_speed = SPEED_10000;  in bnx2x_8706_8726_read_status()
8875 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_8706_8726_read_status()
8876 		vars->duplex = DUPLEX_FULL;  in bnx2x_8706_8726_read_status()
8880 	if (vars->line_speed == SPEED_10000) {  in bnx2x_8706_8726_read_status()
8881 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_8706_8726_read_status()
8883 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_8706_8726_read_status()
8886 			vars->fault_detected = 1;  in bnx2x_8706_8726_read_status()
8893 /*			BCM8706 PHY SECTION			  */
8895 static void bnx2x_8706_config_init(struct bnx2x_phy *phy,  in bnx2x_8706_config_init()  argument
8901 	struct bnx2x *bp = params->bp;  in bnx2x_8706_config_init()
8904 		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);  in bnx2x_8706_config_init()
8906 	bnx2x_ext_phy_hw_reset(bp, params->port);  in bnx2x_8706_config_init()
8907 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);  in bnx2x_8706_config_init()
8908 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_8706_config_init()
8912 		bnx2x_cl45_read(bp, phy,  in bnx2x_8706_config_init()
8918 	DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);  in bnx2x_8706_config_init()
8919 	if ((params->feature_config_flags &  in bnx2x_8706_config_init()
8925 				i*(MDIO_XS_8706_REG_BANK_RX1 -  in bnx2x_8706_config_init()
8927 			bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);  in bnx2x_8706_config_init()
8931 			val |= (phy->rx_preemphasis[i] & 0x7);  in bnx2x_8706_config_init()
8932 			DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"  in bnx2x_8706_config_init()
8933 				   " reg 0x%x <-- val 0x%x\n", reg, val);  in bnx2x_8706_config_init()
8934 			bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);  in bnx2x_8706_config_init()
8938 	if (phy->req_line_speed == SPEED_10000) {  in bnx2x_8706_config_init()
8939 		DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");  in bnx2x_8706_config_init()
8941 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8944 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8948 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8954 		DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");  in bnx2x_8706_config_init()
8955 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8958 		/* Enable Full-Duplex advertisement on CL37 */  in bnx2x_8706_config_init()
8959 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8962 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8965 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8969 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8971 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8974 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8978 	bnx2x_save_bcm_spirom_ver(bp, phy, params->port);  in bnx2x_8706_config_init()
8980 	/* If TX Laser is controlled by GPIO_0, do not let PHY go into low  in bnx2x_8706_config_init()
8984 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8706_config_init()
8986 				dev_info.port_hw_config[params->port].sfp_ctrl))  in bnx2x_8706_config_init()
8990 		DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");  in bnx2x_8706_config_init()
8991 		bnx2x_cl45_read(bp, phy,  in bnx2x_8706_config_init()
8994 		bnx2x_cl45_write(bp, phy,  in bnx2x_8706_config_init()
8999 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,  in bnx2x_8706_read_status()  argument
9003 	return bnx2x_8706_8726_read_status(phy, params, vars);  in bnx2x_8706_read_status()
9007 /*			BCM8726 PHY SECTION			  */
9009 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,  in bnx2x_8726_config_loopback()  argument
9012 	struct bnx2x *bp = params->bp;  in bnx2x_8726_config_loopback()
9013 	DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");  in bnx2x_8726_config_loopback()
9014 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);  in bnx2x_8726_config_loopback()
9017 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,  in bnx2x_8726_external_rom_boot()  argument
9020 	struct bnx2x *bp = params->bp;  in bnx2x_8726_external_rom_boot()
9024 	/* Micro controller re-boot */  in bnx2x_8726_external_rom_boot()
9025 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_external_rom_boot()
9029 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_external_rom_boot()
9034 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_external_rom_boot()
9038 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_external_rom_boot()
9047 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_external_rom_boot()
9052 	bnx2x_save_bcm_spirom_ver(bp, phy, params->port);  in bnx2x_8726_external_rom_boot()
9055 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,  in bnx2x_8726_read_status()  argument
9059 	struct bnx2x *bp = params->bp;  in bnx2x_8726_read_status()
9061 	u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);  in bnx2x_8726_read_status()
9063 		bnx2x_cl45_read(bp, phy,  in bnx2x_8726_read_status()
9067 			DP(NETIF_MSG_LINK, "Tx is disabled\n");  in bnx2x_8726_read_status()
9069 			vars->line_speed = 0;  in bnx2x_8726_read_status()
9076 static void bnx2x_8726_config_init(struct bnx2x_phy *phy,  in bnx2x_8726_config_init()  argument
9080 	struct bnx2x *bp = params->bp;  in bnx2x_8726_config_init()
9081 	DP(NETIF_MSG_LINK, "Initializing BCM8726\n");  in bnx2x_8726_config_init()
9083 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in bnx2x_8726_config_init()
9084 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_8726_config_init()
9086 	bnx2x_8726_external_rom_boot(phy, params);  in bnx2x_8726_config_init()
9093 	bnx2x_sfp_module_detection(phy, params);  in bnx2x_8726_config_init()
9095 	if (phy->req_line_speed == SPEED_1000) {  in bnx2x_8726_config_init()
9096 		DP(NETIF_MSG_LINK, "Setting 1G force\n");  in bnx2x_8726_config_init()
9097 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9099 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9101 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9103 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9106 	} else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_8726_config_init()
9107 		   (phy->speed_cap_mask &  in bnx2x_8726_config_init()
9109 		   ((phy->speed_cap_mask &  in bnx2x_8726_config_init()
9112 		DP(NETIF_MSG_LINK, "Setting 1G clause37\n");  in bnx2x_8726_config_init()
9114 		bnx2x_ext_phy_set_pause(params, phy, vars);  in bnx2x_8726_config_init()
9115 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9117 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9119 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9121 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9123 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9125 		/* Enable RX-ALARM control to receive interrupt for 1G speed  in bnx2x_8726_config_init()
9128 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9130 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9135 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9140 	if ((params->feature_config_flags &  in bnx2x_8726_config_init()
9142 		DP(NETIF_MSG_LINK,  in bnx2x_8726_config_init()
9144 			 phy->tx_preemphasis[0],  in bnx2x_8726_config_init()
9145 			 phy->tx_preemphasis[1]);  in bnx2x_8726_config_init()
9146 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9149 				 phy->tx_preemphasis[0]);  in bnx2x_8726_config_init()
9151 		bnx2x_cl45_write(bp, phy,  in bnx2x_8726_config_init()
9154 				 phy->tx_preemphasis[1]);  in bnx2x_8726_config_init()
9158 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,  in bnx2x_8726_link_reset()  argument
9161 	struct bnx2x *bp = params->bp;  in bnx2x_8726_link_reset()
9162 	DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);  in bnx2x_8726_link_reset()
9164 	bnx2x_cl45_write(bp, phy,  in bnx2x_8726_link_reset()
9170 /*			BCM8727 PHY SECTION			  */
9173 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,  in bnx2x_8727_set_link_led()  argument
9176 	struct bnx2x *bp = params->bp;  in bnx2x_8727_set_link_led()
9181 	if (!(phy->flags & FLAGS_NOC))  in bnx2x_8727_set_link_led()
9198 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_set_link_led()
9204 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_set_link_led()
9208 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_set_link_led()
9214 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_set_link_led()
9219 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,  in bnx2x_8727_hw_reset()  argument
9223 	/* The PHY reset is controlled by GPIO 1. Fake the port number  in bnx2x_8727_hw_reset()
9226 	struct bnx2x *bp = params->bp;  in bnx2x_8727_hw_reset()
9234 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,  in bnx2x_8727_config_speed()  argument
9237 	struct bnx2x *bp = params->bp;  in bnx2x_8727_config_speed()
9240 	if ((phy->req_line_speed == SPEED_1000) ||  in bnx2x_8727_config_speed()
9241 	    (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {  in bnx2x_8727_config_speed()
9242 		DP(NETIF_MSG_LINK, "Setting 1G force\n");  in bnx2x_8727_config_speed()
9243 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9245 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9247 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_speed()
9249 		DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);  in bnx2x_8727_config_speed()
9250 		/* Power down the XAUI until link is up in case of dual-media  in bnx2x_8727_config_speed()
9254 			bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_speed()
9258 			bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9262 	} else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_8727_config_speed()
9263 		   ((phy->speed_cap_mask &  in bnx2x_8727_config_speed()
9265 		   ((phy->speed_cap_mask &  in bnx2x_8727_config_speed()
9269 		DP(NETIF_MSG_LINK, "Setting 1G clause37\n");  in bnx2x_8727_config_speed()
9270 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9272 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9278 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9281 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9283 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9285 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_speed()
9291 static void bnx2x_8727_config_init(struct bnx2x_phy *phy,  in bnx2x_8727_config_init()  argument
9297 	struct bnx2x *bp = params->bp;  in bnx2x_8727_config_init()
9300 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_8727_config_init()
9302 	DP(NETIF_MSG_LINK, "Initializing BCM8727\n");  in bnx2x_8727_config_init()
9304 	bnx2x_8727_specific_func(phy, params, PHY_INIT);  in bnx2x_8727_config_init()
9308 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_init()
9315 	if (!(phy->flags & FLAGS_NOC))  in bnx2x_8727_config_init()
9317 	bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_init()
9320 	/* Enable/Disable PHY transmitter output */  in bnx2x_8727_config_init()
9321 	bnx2x_set_disable_pmd_transmit(params, phy, 0);  in bnx2x_8727_config_init()
9323 	bnx2x_8727_power_module(bp, phy, 1);  in bnx2x_8727_config_init()
9325 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_init()
9328 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_init()
9331 	bnx2x_8727_config_speed(phy, params);  in bnx2x_8727_config_init()
9335 	if ((params->feature_config_flags &  in bnx2x_8727_config_init()
9337 		DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",  in bnx2x_8727_config_init()
9338 			   phy->tx_preemphasis[0],  in bnx2x_8727_config_init()
9339 			   phy->tx_preemphasis[1]);  in bnx2x_8727_config_init()
9340 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_init()
9342 				 phy->tx_preemphasis[0]);  in bnx2x_8727_config_init()
9344 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_init()
9346 				 phy->tx_preemphasis[1]);  in bnx2x_8727_config_init()
9349 	/* If TX Laser is controlled by GPIO_0, do not let PHY go into low  in bnx2x_8727_config_init()
9352 	tx_en_mode = REG_RD(bp, params->shmem_base +  in bnx2x_8727_config_init()
9354 				dev_info.port_hw_config[params->port].sfp_ctrl))  in bnx2x_8727_config_init()
9359 		DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");  in bnx2x_8727_config_init()
9360 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_init()
9364 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_init()
9366 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_config_init()
9369 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_config_init()
9375 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,  in bnx2x_8727_handle_mod_abs()  argument
9378 	struct bnx2x *bp = params->bp;  in bnx2x_8727_handle_mod_abs()
9380 	u32 val = REG_RD(bp, params->shmem_base +  in bnx2x_8727_handle_mod_abs()
9382 				      port_feature_config[params->port].  in bnx2x_8727_handle_mod_abs()
9384 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_handle_mod_abs()
9390 		DP(NETIF_MSG_LINK,  in bnx2x_8727_handle_mod_abs()
9392 		phy->media_type = ETH_PHY_NOT_PRESENT;  in bnx2x_8727_handle_mod_abs()
9401 		if (!(phy->flags & FLAGS_NOC))  in bnx2x_8727_handle_mod_abs()
9403 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_handle_mod_abs()
9410 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_handle_mod_abs()
9416 		DP(NETIF_MSG_LINK,  in bnx2x_8727_handle_mod_abs()
9426 		if (!(phy->flags & FLAGS_NOC))  in bnx2x_8727_handle_mod_abs()
9428 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_handle_mod_abs()
9437 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_handle_mod_abs()
9444 			bnx2x_sfp_set_transmitter(params, phy, 0);  in bnx2x_8727_handle_mod_abs()
9446 		if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)  in bnx2x_8727_handle_mod_abs()
9447 			bnx2x_sfp_module_detection(phy, params);  in bnx2x_8727_handle_mod_abs()
9449 			DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");  in bnx2x_8727_handle_mod_abs()
9452 		bnx2x_8727_config_speed(phy, params);  in bnx2x_8727_handle_mod_abs()
9455 	DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",  in bnx2x_8727_handle_mod_abs()
9460 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,  in bnx2x_8727_read_status()  argument
9465 	struct bnx2x *bp = params->bp;  in bnx2x_8727_read_status()
9466 	u8 link_up = 0, oc_port = params->port;  in bnx2x_8727_read_status()
9470 	/* If PHY is not initialized, do not check link status */  in bnx2x_8727_read_status()
9471 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9478 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9481 	vars->line_speed = 0;  in bnx2x_8727_read_status()
9482 	DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);  in bnx2x_8727_read_status()
9484 	bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,  in bnx2x_8727_read_status()
9487 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9490 	DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);  in bnx2x_8727_read_status()
9492 	/* Clear MSG-OUT */  in bnx2x_8727_read_status()
9493 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9499 	if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {  in bnx2x_8727_read_status()
9500 		/* Check over-current using 8727 GPIO0 input*/  in bnx2x_8727_read_status()
9501 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9507 				oc_port = BP_PATH(bp) + (params->port << 1);  in bnx2x_8727_read_status()
9508 			DP(NETIF_MSG_LINK,  in bnx2x_8727_read_status()
9511 			netdev_err(bp->dev, "Error: Power fault on Port %d has "  in bnx2x_8727_read_status()
9520 			bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_status()
9524 			bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9529 			bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_status()
9533 			bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9536 			bnx2x_8727_power_module(params->bp, phy, 0);  in bnx2x_8727_read_status()
9543 		bnx2x_8727_handle_mod_abs(phy, params);  in bnx2x_8727_read_status()
9545 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_status()
9550 	if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {  in bnx2x_8727_read_status()
9551 		DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");  in bnx2x_8727_read_status()
9552 		bnx2x_sfp_set_transmitter(params, phy, 1);  in bnx2x_8727_read_status()
9554 		DP(NETIF_MSG_LINK, "Tx is disabled\n");  in bnx2x_8727_read_status()
9558 	bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9562 	/* Bits 0..2 --> speed detected,  in bnx2x_8727_read_status()
9563 	 * Bits 13..15--> link is down  in bnx2x_8727_read_status()
9567 		vars->line_speed = SPEED_10000;  in bnx2x_8727_read_status()
9568 		DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",  in bnx2x_8727_read_status()
9569 			   params->port);  in bnx2x_8727_read_status()
9572 		vars->line_speed = SPEED_1000;  in bnx2x_8727_read_status()
9573 		DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",  in bnx2x_8727_read_status()
9574 			   params->port);  in bnx2x_8727_read_status()
9577 		DP(NETIF_MSG_LINK, "port %x: External link is down\n",  in bnx2x_8727_read_status()
9578 			   params->port);  in bnx2x_8727_read_status()
9582 	if (vars->line_speed == SPEED_10000) {  in bnx2x_8727_read_status()
9583 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_8727_read_status()
9586 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,  in bnx2x_8727_read_status()
9590 			vars->fault_detected = 1;  in bnx2x_8727_read_status()
9595 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_8727_read_status()
9596 		vars->duplex = DUPLEX_FULL;  in bnx2x_8727_read_status()
9597 		DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);  in bnx2x_8727_read_status()
9601 	    (phy->req_line_speed == SPEED_1000)) {  in bnx2x_8727_read_status()
9602 		bnx2x_cl45_read(bp, phy,  in bnx2x_8727_read_status()
9605 		/* In case of dual-media board and 1G, power up the XAUI side,  in bnx2x_8727_read_status()
9612 		bnx2x_cl45_write(bp, phy,  in bnx2x_8727_read_status()
9619 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,  in bnx2x_8727_link_reset()  argument
9622 	struct bnx2x *bp = params->bp;  in bnx2x_8727_link_reset()
9624 	/* Enable/Disable PHY transmitter output */  in bnx2x_8727_link_reset()
9625 	bnx2x_set_disable_pmd_transmit(params, phy, 1);  in bnx2x_8727_link_reset()
9628 	bnx2x_sfp_set_transmitter(params, phy, 0);  in bnx2x_8727_link_reset()
9630 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);  in bnx2x_8727_link_reset()
9635 /*		BCM8481/BCM84823/BCM84833 PHY SECTION	          */
9637 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)  in bnx2x_is_8483x_8485x()  argument
9639 	return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||  in bnx2x_is_8483x_8485x()
9640 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||  in bnx2x_is_8483x_8485x()
9641 		(phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));  in bnx2x_is_8483x_8485x()
9644 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,  in bnx2x_save_848xx_spirom_version()  argument
9658 	if (bnx2x_is_8483x_8485x(phy)) {  in bnx2x_save_848xx_spirom_version()
9659 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);  in bnx2x_save_848xx_spirom_version()
9660 		if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)  in bnx2x_save_848xx_spirom_version()
9662 		bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr);  in bnx2x_save_848xx_spirom_version()
9664 		/* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */  in bnx2x_save_848xx_spirom_version()
9667 			bnx2x_cl45_write(bp, phy, reg_set[i].devad,  in bnx2x_save_848xx_spirom_version()
9671 			bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in bnx2x_save_848xx_spirom_version()
9677 			DP(NETIF_MSG_LINK, "Unable to read 848xx "  in bnx2x_save_848xx_spirom_version()
9678 					"phy fw version(1)\n");  in bnx2x_save_848xx_spirom_version()
9680 						  phy->ver_addr);  in bnx2x_save_848xx_spirom_version()
9686 		bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);  in bnx2x_save_848xx_spirom_version()
9687 		bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);  in bnx2x_save_848xx_spirom_version()
9688 		bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);  in bnx2x_save_848xx_spirom_version()
9690 			bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);  in bnx2x_save_848xx_spirom_version()
9696 			DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "  in bnx2x_save_848xx_spirom_version()
9699 						  phy->ver_addr);  in bnx2x_save_848xx_spirom_version()
9704 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);  in bnx2x_save_848xx_spirom_version()
9706 		bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);  in bnx2x_save_848xx_spirom_version()
9709 					  phy->ver_addr);  in bnx2x_save_848xx_spirom_version()
9714 				struct bnx2x_phy *phy)  in bnx2x_848xx_set_led()  argument
9726 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {  in bnx2x_848xx_set_led()
9728 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_led()
9737 	bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_led()
9743 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_set_led()
9749 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)  in bnx2x_848xx_set_led()
9752 	bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_led()
9757 		bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,  in bnx2x_848xx_set_led()
9760 	if (bnx2x_is_8483x_8485x(phy))  in bnx2x_848xx_set_led()
9765 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)  in bnx2x_848xx_set_led()
9772 	bnx2x_cl45_read_or_write(bp, phy,  in bnx2x_848xx_set_led()
9778 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,  in bnx2x_848xx_specific_func()  argument
9782 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_specific_func()
9785 		if (bnx2x_is_8483x_8485x(phy)) {  in bnx2x_848xx_specific_func()
9787 			bnx2x_save_848xx_spirom_version(phy, bp, params->port);  in bnx2x_848xx_specific_func()
9789 		/* This phy uses the NIG latch mechanism since link indication  in bnx2x_848xx_specific_func()
9793 		bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,  in bnx2x_848xx_specific_func()
9796 		bnx2x_848xx_set_led(bp, phy);  in bnx2x_848xx_specific_func()
9801 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,  in bnx2x_848xx_cmn_config_init()  argument
9805 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_cmn_config_init()
9808 	bnx2x_848xx_specific_func(phy, params, PHY_INIT);  in bnx2x_848xx_cmn_config_init()
9809 	bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9813 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_cmn_config_init()
9817 	bnx2x_ext_phy_set_pause(params, phy, vars);  in bnx2x_848xx_cmn_config_init()
9818 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_cmn_config_init()
9822 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_cmn_config_init()
9829 	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_848xx_cmn_config_init()
9830 	     (phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9832 	    (phy->req_line_speed == SPEED_1000)) {  in bnx2x_848xx_cmn_config_init()
9835 		if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_848xx_cmn_config_init()
9837 		DP(NETIF_MSG_LINK, "Advertising 1G\n");  in bnx2x_848xx_cmn_config_init()
9841 	bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9846 	if (phy->req_line_speed == SPEED_AUTO_NEG) {  in bnx2x_848xx_cmn_config_init()
9847 		if (phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9853 			DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");  in bnx2x_848xx_cmn_config_init()
9856 		if (phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9862 			DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");  in bnx2x_848xx_cmn_config_init()
9865 		if ((phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9867 		    (phy->supported & SUPPORTED_10baseT_Full)) {  in bnx2x_848xx_cmn_config_init()
9870 			DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");  in bnx2x_848xx_cmn_config_init()
9873 		if ((phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9875 		    (phy->supported & SUPPORTED_10baseT_Half)) {  in bnx2x_848xx_cmn_config_init()
9878 			DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");  in bnx2x_848xx_cmn_config_init()
9883 	if ((phy->req_line_speed == SPEED_100) &&  in bnx2x_848xx_cmn_config_init()
9884 	    (phy->supported &  in bnx2x_848xx_cmn_config_init()
9888 		/* Enabled AUTO-MDIX when autoneg is disabled */  in bnx2x_848xx_cmn_config_init()
9889 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9892 		/* The PHY needs this set even for forced link. */  in bnx2x_848xx_cmn_config_init()
9894 		DP(NETIF_MSG_LINK, "Setting 100M force\n");  in bnx2x_848xx_cmn_config_init()
9896 	if ((phy->req_line_speed == SPEED_10) &&  in bnx2x_848xx_cmn_config_init()
9897 	    (phy->supported &  in bnx2x_848xx_cmn_config_init()
9900 		/* Enabled AUTO-MDIX when autoneg is disabled */  in bnx2x_848xx_cmn_config_init()
9901 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9904 		DP(NETIF_MSG_LINK, "Setting 10M force\n");  in bnx2x_848xx_cmn_config_init()
9907 	bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9911 	if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_848xx_cmn_config_init()
9917 	if (!bnx2x_is_8483x_8485x(phy) ||  in bnx2x_848xx_cmn_config_init()
9919 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9923 	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_848xx_cmn_config_init()
9924 	    (phy->speed_cap_mask &  in bnx2x_848xx_cmn_config_init()
9926 		(phy->req_line_speed == SPEED_10000)) {  in bnx2x_848xx_cmn_config_init()
9927 			DP(NETIF_MSG_LINK, "Advertising 10G\n");  in bnx2x_848xx_cmn_config_init()
9931 				bp, phy,  in bnx2x_848xx_cmn_config_init()
9935 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9939 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_cmn_config_init()
9947 static void bnx2x_8481_config_init(struct bnx2x_phy *phy,  in bnx2x_8481_config_init()  argument
9951 	struct bnx2x *bp = params->bp;  in bnx2x_8481_config_init()
9954 		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);  in bnx2x_8481_config_init()
9957 	bnx2x_ext_phy_hw_reset(bp, params->port);  in bnx2x_8481_config_init()
9958 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_8481_config_init()
9960 	bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);  in bnx2x_8481_config_init()
9961 	bnx2x_848xx_cmn_config_init(phy, params, vars);  in bnx2x_8481_config_init()
9967 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,  in bnx2x_84858_cmd_hdlr()  argument
9974 	struct bnx2x *bp = params->bp;  in bnx2x_84858_cmd_hdlr()
9984 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84858_cmd_hdlr()
9992 		DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");  in bnx2x_84858_cmd_hdlr()
9993 		return -EINVAL;  in bnx2x_84858_cmd_hdlr()
10001 		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84858_cmd_hdlr()
10009 	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84858_cmd_hdlr()
10018 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84858_cmd_hdlr()
10027 		DP(NETIF_MSG_LINK, "FW cmd failed.\n");  in bnx2x_84858_cmd_hdlr()
10028 		return -EINVAL;  in bnx2x_84858_cmd_hdlr()
10036 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84858_cmd_hdlr()
10044 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,  in bnx2x_84833_cmd_hdlr()  argument
10050 	struct bnx2x *bp = params->bp;  in bnx2x_84833_cmd_hdlr()
10055 		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10061 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10068 		DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");  in bnx2x_84833_cmd_hdlr()
10074 			bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10078 		return -EINVAL;  in bnx2x_84833_cmd_hdlr()
10084 			bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10090 	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10093 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10102 		DP(NETIF_MSG_LINK, "FW cmd failed.\n");  in bnx2x_84833_cmd_hdlr()
10103 		rc = -EINVAL;  in bnx2x_84833_cmd_hdlr()
10108 			bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10115 		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_84833_cmd_hdlr()
10122 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,  in bnx2x_848xx_cmd_hdlr()  argument
10128 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_cmd_hdlr()
10130 	if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||  in bnx2x_848xx_cmd_hdlr()
10131 	    (REG_RD(bp, params->shmem2_base +  in bnx2x_848xx_cmd_hdlr()
10133 			     link_attr_sync[params->port])) &  in bnx2x_848xx_cmd_hdlr()
10135 		return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in bnx2x_848xx_cmd_hdlr()
10138 		return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,  in bnx2x_848xx_cmd_hdlr()
10143 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,  in bnx2x_848xx_pair_swap_cfg()  argument
10150 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_pair_swap_cfg()
10153 	pair_swap = REG_RD(bp, params->shmem_base +  in bnx2x_848xx_pair_swap_cfg()
10155 			dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &  in bnx2x_848xx_pair_swap_cfg()
10164 	status = bnx2x_848xx_cmd_hdlr(phy, params,  in bnx2x_848xx_pair_swap_cfg()
10168 		DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);  in bnx2x_848xx_pair_swap_cfg()
10190 			reset_pin[idx] -= PIN_CFG_GPIO0_P0;  in bnx2x_84833_get_reset_gpios()
10201 			reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;  in bnx2x_84833_get_reset_gpios()
10211 static void bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,  in bnx2x_84833_hw_reset_phy()  argument
10214 	struct bnx2x *bp = params->bp;  in bnx2x_84833_hw_reset_phy()
10216 	u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +  in bnx2x_84833_hw_reset_phy()
10223 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_84833_hw_reset_phy()
10226 	bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_84833_hw_reset_phy()
10230 	shmem_base_path[0] = params->shmem_base;  in bnx2x_84833_hw_reset_phy()
10234 						  params->chip_id);  in bnx2x_84833_hw_reset_phy()
10238 	DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",  in bnx2x_84833_hw_reset_phy()
10242 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,  in bnx2x_8483x_disable_eee()  argument
10247 	struct bnx2x *bp = params->bp;  in bnx2x_8483x_disable_eee()
10250 	DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");  in bnx2x_8483x_disable_eee()
10252 	/* Prevent Phy from working in EEE and advertising it */  in bnx2x_8483x_disable_eee()
10253 	rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in bnx2x_8483x_disable_eee()
10256 		DP(NETIF_MSG_LINK, "EEE disable failed.\n");  in bnx2x_8483x_disable_eee()
10260 	return bnx2x_eee_disable(phy, params, vars);  in bnx2x_8483x_disable_eee()
10263 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,  in bnx2x_8483x_enable_eee()  argument
10268 	struct bnx2x *bp = params->bp;  in bnx2x_8483x_enable_eee()
10271 	rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,  in bnx2x_8483x_enable_eee()
10274 		DP(NETIF_MSG_LINK, "EEE enable failed.\n");  in bnx2x_8483x_enable_eee()
10278 	return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);  in bnx2x_8483x_enable_eee()
10282 static void bnx2x_848x3_config_init(struct bnx2x_phy *phy,  in bnx2x_848x3_config_init()  argument
10286 	struct bnx2x *bp = params->bp;  in bnx2x_848x3_config_init()
10298 		port = params->port;  in bnx2x_848x3_config_init()
10300 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in bnx2x_848x3_config_init()
10306 		bnx2x_cl45_write(bp, phy,  in bnx2x_848x3_config_init()
10311 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_848x3_config_init()
10315 	if (!bnx2x_is_8483x_8485x(phy)) {  in bnx2x_848x3_config_init()
10320 		temp = vars->line_speed;  in bnx2x_848x3_config_init()
10321 		vars->line_speed = SPEED_10000;  in bnx2x_848x3_config_init()
10322 		bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);  in bnx2x_848x3_config_init()
10323 		bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);  in bnx2x_848x3_config_init()
10324 		vars->line_speed = temp;  in bnx2x_848x3_config_init()
10327 	if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {  in bnx2x_848x3_config_init()
10330 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10333 			params->link_attr_sync |= LINK_ATTR_84858;  in bnx2x_848x3_config_init()
10334 			bnx2x_update_link_attr(params, params->link_attr_sync);  in bnx2x_848x3_config_init()
10338 	/* Set dual-media configuration according to configuration */  in bnx2x_848x3_config_init()
10339 	bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_848x3_config_init()
10368 		/* Do nothing here. The first PHY won't be initialized at all */  in bnx2x_848x3_config_init()
10375 	if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)  in bnx2x_848x3_config_init()
10378 	bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_848x3_config_init()
10380 	DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",  in bnx2x_848x3_config_init()
10381 		   params->multi_phy_config, val);  in bnx2x_848x3_config_init()
10383 	if (bnx2x_is_8483x_8485x(phy)) {  in bnx2x_848x3_config_init()
10384 		bnx2x_848xx_pair_swap_cfg(phy, params, vars);  in bnx2x_848x3_config_init()
10391 		rc = bnx2x_848xx_cmd_hdlr(phy, params,  in bnx2x_848x3_config_init()
10395 			DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");  in bnx2x_848x3_config_init()
10398 		rc = bnx2x_848xx_cmn_config_init(phy, params, vars);  in bnx2x_848x3_config_init()
10400 		bnx2x_save_848xx_spirom_version(phy, bp, params->port);  in bnx2x_848x3_config_init()
10401 	/* 84833 PHY has a better feature and doesn't need to support this. */  in bnx2x_848x3_config_init()
10402 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in bnx2x_848x3_config_init()
10403 		u32 cms_enable = REG_RD(bp, params->shmem_base +  in bnx2x_848x3_config_init()
10405 			dev_info.port_hw_config[params->port].default_cfg)) &  in bnx2x_848x3_config_init()
10408 		bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_848x3_config_init()
10414 		bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_848x3_config_init()
10418 	bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,  in bnx2x_848x3_config_init()
10427 			DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");  in bnx2x_848x3_config_init()
10428 			bnx2x_8483x_disable_eee(phy, params, vars);  in bnx2x_848x3_config_init()
10432 		if ((phy->req_duplex == DUPLEX_FULL) &&  in bnx2x_848x3_config_init()
10433 		    (params->eee_mode & EEE_MODE_ADV_LPI) &&  in bnx2x_848x3_config_init()
10435 		     !(params->eee_mode & EEE_MODE_ENABLE_LPI)))  in bnx2x_848x3_config_init()
10436 			rc = bnx2x_8483x_enable_eee(phy, params, vars);  in bnx2x_848x3_config_init()
10438 			rc = bnx2x_8483x_disable_eee(phy, params, vars);  in bnx2x_848x3_config_init()
10440 			DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");  in bnx2x_848x3_config_init()
10444 		vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;  in bnx2x_848x3_config_init()
10447 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {  in bnx2x_848x3_config_init()
10448 		/* Additional settings for jumbo packets in 1000BASE-T mode */  in bnx2x_848x3_config_init()
10450 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10453 		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10456 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10459 		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10463 		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10466 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10469 		bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848x3_config_init()
10473 	if (bnx2x_is_8483x_8485x(phy)) {  in bnx2x_848x3_config_init()
10474 		/* Bring PHY out of super isolate mode as the final step. */  in bnx2x_848x3_config_init()
10475 		bnx2x_cl45_read_and_write(bp, phy,  in bnx2x_848x3_config_init()
10482 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,  in bnx2x_848xx_read_status()  argument
10486 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_read_status()
10491 	/* Check 10G-BaseT link status */  in bnx2x_848xx_read_status()
10493 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_read_status()
10495 	bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_read_status()
10498 	DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);  in bnx2x_848xx_read_status()
10502 		vars->line_speed = SPEED_10000;  in bnx2x_848xx_read_status()
10503 		vars->duplex = DUPLEX_FULL;  in bnx2x_848xx_read_status()
10505 		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);  in bnx2x_848xx_read_status()
10510 		bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_read_status()
10515 		bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_read_status()
10520 		DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",  in bnx2x_848xx_read_status()
10525 			vars->line_speed = SPEED_10;  in bnx2x_848xx_read_status()
10527 			vars->line_speed = SPEED_100;  in bnx2x_848xx_read_status()
10529 			vars->line_speed = SPEED_1000;  in bnx2x_848xx_read_status()
10531 			vars->line_speed = 0;  in bnx2x_848xx_read_status()
10537 				vars->duplex = DUPLEX_FULL;  in bnx2x_848xx_read_status()
10539 				vars->duplex = DUPLEX_HALF;  in bnx2x_848xx_read_status()
10541 			DP(NETIF_MSG_LINK,  in bnx2x_848xx_read_status()
10543 			   vars->line_speed,  in bnx2x_848xx_read_status()
10544 			   (vars->duplex == DUPLEX_FULL));  in bnx2x_848xx_read_status()
10546 			bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_read_status()
10551 				vars->link_status |=  in bnx2x_848xx_read_status()
10553 			bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_read_status()
10558 				vars->link_status |=  in bnx2x_848xx_read_status()
10563 		DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",  in bnx2x_848xx_read_status()
10564 			   vars->line_speed);  in bnx2x_848xx_read_status()
10565 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_848xx_read_status()
10568 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848xx_read_status()
10571 			vars->link_status |=  in bnx2x_848xx_read_status()
10574 			vars->link_status |=  in bnx2x_848xx_read_status()
10577 			vars->link_status |=  in bnx2x_848xx_read_status()
10580 			vars->link_status |=  in bnx2x_848xx_read_status()
10583 			vars->link_status |=  in bnx2x_848xx_read_status()
10586 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848xx_read_status()
10590 			vars->link_status |=  in bnx2x_848xx_read_status()
10593 			vars->link_status |=  in bnx2x_848xx_read_status()
10596 		bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_848xx_read_status()
10600 			vars->link_status |=  in bnx2x_848xx_read_status()
10604 		if (bnx2x_is_8483x_8485x(phy))  in bnx2x_848xx_read_status()
10605 			bnx2x_eee_an_resolve(phy, params, vars);  in bnx2x_848xx_read_status()
10628 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,  in bnx2x_8481_hw_reset()  argument
10631 	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,  in bnx2x_8481_hw_reset()
10633 	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,  in bnx2x_8481_hw_reset()
10637 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,  in bnx2x_8481_link_reset()  argument
10640 	bnx2x_cl45_write(params->bp, phy,  in bnx2x_8481_link_reset()
10642 	bnx2x_cl45_write(params->bp, phy,  in bnx2x_8481_link_reset()
10646 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,  in bnx2x_848x3_link_reset()  argument
10649 	struct bnx2x *bp = params->bp;  in bnx2x_848x3_link_reset()
10656 		port = params->port;  in bnx2x_848x3_link_reset()
10658 	if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {  in bnx2x_848x3_link_reset()
10663 		bnx2x_cl45_read(bp, phy,  in bnx2x_848x3_link_reset()
10667 		bnx2x_cl45_write(bp, phy,  in bnx2x_848x3_link_reset()
10673 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,  in bnx2x_848xx_set_link_led()  argument
10676 	struct bnx2x *bp = params->bp;  in bnx2x_848xx_set_link_led()
10683 		port = params->port;  in bnx2x_848xx_set_link_led()
10688 		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);  in bnx2x_848xx_set_link_led()
10690 		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==  in bnx2x_848xx_set_link_led()
10694 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10699 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10704 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10709 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10716 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10721 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10724 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10729 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10738 		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",  in bnx2x_848xx_set_link_led()
10741 		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==  in bnx2x_848xx_set_link_led()
10745 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10750 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10755 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10760 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10766 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10770 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10776 					   params->port*4) &  in bnx2x_848xx_set_link_led()
10778 					params->link_flags |=  in bnx2x_848xx_set_link_led()
10784 						params->port*4,  in bnx2x_848xx_set_link_led()
10787 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10792 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10795 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10800 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10809 		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);  in bnx2x_848xx_set_link_led()
10811 		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==  in bnx2x_848xx_set_link_led()
10814 			bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_set_link_led()
10821 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10827 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10832 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10837 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10842 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10847 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10851 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10857 					   params->port*4) &  in bnx2x_848xx_set_link_led()
10859 					params->link_flags |=  in bnx2x_848xx_set_link_led()
10865 						params->port*4,  in bnx2x_848xx_set_link_led()
10869 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10872 				bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_set_link_led()
10878 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10882 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10887 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10897 		DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);  in bnx2x_848xx_set_link_led()
10899 		if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==  in bnx2x_848xx_set_link_led()
10903 			bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_set_link_led()
10911 				DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");  in bnx2x_848xx_set_link_led()
10912 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10919 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10924 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10929 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10934 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10944 			val = ((params->hw_led_mode <<  in bnx2x_848xx_set_link_led()
10948 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10954 			bnx2x_cl45_read(bp, phy,  in bnx2x_848xx_set_link_led()
10960 			bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10964 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10966 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10970 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10975 			if (phy->type ==  in bnx2x_848xx_set_link_led()
10978 				 * and re-enable interrupts.  in bnx2x_848xx_set_link_led()
10980 				bnx2x_cl45_write(bp, phy,  in bnx2x_848xx_set_link_led()
10984 				if (params->link_flags &  in bnx2x_848xx_set_link_led()
10987 					params->link_flags &=  in bnx2x_848xx_set_link_led()
10999 		bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,  in bnx2x_848xx_set_link_led()
11005 /*			54618SE PHY SECTION			  */
11007 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,  in bnx2x_54618se_specific_func()  argument
11011 	struct bnx2x *bp = params->bp;  in bnx2x_54618se_specific_func()
11017 		bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_specific_func()
11020 		bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_specific_func()
11025 		bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_specific_func()
11029 		bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_specific_func()
11036 static void bnx2x_54618se_config_init(struct bnx2x_phy *phy,  in bnx2x_54618se_config_init()  argument
11040 	struct bnx2x *bp = params->bp;  in bnx2x_54618se_config_init()
11045 	DP(NETIF_MSG_LINK, "54618SE cfg init\n");  in bnx2x_54618se_config_init()
11051 	port = params->port;  in bnx2x_54618se_config_init()
11053 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_config_init()
11065 	/* reset phy */  in bnx2x_54618se_config_init()
11066 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11068 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_54618se_config_init()
11074 	bnx2x_54618se_specific_func(phy, params, PHY_INIT);  in bnx2x_54618se_config_init()
11076 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11079 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_config_init()
11083 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11088 	/* Please refer to Table 28B-3 of 802.3ab-1999 spec. */  in bnx2x_54618se_config_init()
11089 	bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);  in bnx2x_54618se_config_init()
11091 	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==  in bnx2x_54618se_config_init()
11095 	if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==  in bnx2x_54618se_config_init()
11100 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_config_init()
11104 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_config_init()
11108 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_config_init()
11117 	if (((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_54618se_config_init()
11118 	     (phy->speed_cap_mask &  in bnx2x_54618se_config_init()
11120 	    (phy->req_line_speed == SPEED_1000)) {  in bnx2x_54618se_config_init()
11123 		if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_54618se_config_init()
11125 		DP(NETIF_MSG_LINK, "Advertising 1G\n");  in bnx2x_54618se_config_init()
11129 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11132 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_config_init()
11137 	if (phy->req_line_speed == SPEED_AUTO_NEG) {  in bnx2x_54618se_config_init()
11138 		if (phy->speed_cap_mask &  in bnx2x_54618se_config_init()
11142 			DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");  in bnx2x_54618se_config_init()
11144 		if (phy->speed_cap_mask &  in bnx2x_54618se_config_init()
11148 			DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");  in bnx2x_54618se_config_init()
11150 		if (phy->speed_cap_mask &  in bnx2x_54618se_config_init()
11154 			DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");  in bnx2x_54618se_config_init()
11156 		if (phy->speed_cap_mask &  in bnx2x_54618se_config_init()
11160 			DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");  in bnx2x_54618se_config_init()
11165 	if (phy->req_line_speed == SPEED_100) {  in bnx2x_54618se_config_init()
11167 		/* Enabled AUTO-MDIX when autoneg is disabled */  in bnx2x_54618se_config_init()
11168 		bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11171 		DP(NETIF_MSG_LINK, "Setting 100M force\n");  in bnx2x_54618se_config_init()
11173 	if (phy->req_line_speed == SPEED_10) {  in bnx2x_54618se_config_init()
11174 		/* Enabled AUTO-MDIX when autoneg is disabled */  in bnx2x_54618se_config_init()
11175 		bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11178 		DP(NETIF_MSG_LINK, "Setting 10M force\n");  in bnx2x_54618se_config_init()
11181 	if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {  in bnx2x_54618se_config_init()
11184 		bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,  in bnx2x_54618se_config_init()
11187 		bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);  in bnx2x_54618se_config_init()
11189 		bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);  in bnx2x_54618se_config_init()
11193 			DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");  in bnx2x_54618se_config_init()
11194 			bnx2x_eee_disable(phy, params, vars);  in bnx2x_54618se_config_init()
11195 		} else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&  in bnx2x_54618se_config_init()
11196 			   (phy->req_duplex == DUPLEX_FULL) &&  in bnx2x_54618se_config_init()
11198 			    !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {  in bnx2x_54618se_config_init()
11204 			bnx2x_eee_advertise(phy, params, vars,  in bnx2x_54618se_config_init()
11207 			DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");  in bnx2x_54618se_config_init()
11208 			bnx2x_eee_disable(phy, params, vars);  in bnx2x_54618se_config_init()
11211 		vars->eee_status &= ~SHMEM_EEE_1G_ADV <<  in bnx2x_54618se_config_init()
11214 		if (phy->flags & FLAGS_EEE) {  in bnx2x_54618se_config_init()
11215 			/* Handle legacy auto-grEEEn */  in bnx2x_54618se_config_init()
11216 			if (params->feature_config_flags &  in bnx2x_54618se_config_init()
11219 				DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");  in bnx2x_54618se_config_init()
11222 				DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");  in bnx2x_54618se_config_init()
11224 			bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,  in bnx2x_54618se_config_init()
11229 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11233 	if (phy->req_duplex == DUPLEX_FULL)  in bnx2x_54618se_config_init()
11236 	bnx2x_cl22_write(bp, phy,  in bnx2x_54618se_config_init()
11241 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,  in bnx2x_5461x_set_link_led()  argument
11244 	struct bnx2x *bp = params->bp;  in bnx2x_5461x_set_link_led()
11247 	bnx2x_cl22_write(bp, phy,  in bnx2x_5461x_set_link_led()
11250 	bnx2x_cl22_read(bp, phy,  in bnx2x_5461x_set_link_led()
11255 	DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);  in bnx2x_5461x_set_link_led()
11270 	bnx2x_cl22_write(bp, phy,  in bnx2x_5461x_set_link_led()
11277 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,  in bnx2x_54618se_link_reset()  argument
11280 	struct bnx2x *bp = params->bp;  in bnx2x_54618se_link_reset()
11287 	bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);  in bnx2x_54618se_link_reset()
11291 	port = params->port;  in bnx2x_54618se_link_reset()
11292 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_54618se_link_reset()
11302 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,  in bnx2x_54618se_read_status()  argument
11306 	struct bnx2x *bp = params->bp;  in bnx2x_54618se_read_status()
11312 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_read_status()
11315 	DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);  in bnx2x_54618se_read_status()
11317 	/* Read status to clear the PHY interrupt. */  in bnx2x_54618se_read_status()
11318 	bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_read_status()
11327 			vars->line_speed = SPEED_1000;  in bnx2x_54618se_read_status()
11328 			vars->duplex = DUPLEX_FULL;  in bnx2x_54618se_read_status()
11330 			vars->line_speed = SPEED_1000;  in bnx2x_54618se_read_status()
11331 			vars->duplex = DUPLEX_HALF;  in bnx2x_54618se_read_status()
11333 			vars->line_speed = SPEED_100;  in bnx2x_54618se_read_status()
11334 			vars->duplex = DUPLEX_FULL;  in bnx2x_54618se_read_status()
11336 		/* Omitting 100Base-T4 for now */  in bnx2x_54618se_read_status()
11338 			vars->line_speed = SPEED_100;  in bnx2x_54618se_read_status()
11339 			vars->duplex = DUPLEX_HALF;  in bnx2x_54618se_read_status()
11341 			vars->line_speed = SPEED_10;  in bnx2x_54618se_read_status()
11342 			vars->duplex = DUPLEX_FULL;  in bnx2x_54618se_read_status()
11344 			vars->line_speed = SPEED_10;  in bnx2x_54618se_read_status()
11345 			vars->duplex = DUPLEX_HALF;  in bnx2x_54618se_read_status()
11347 			vars->line_speed = 0;  in bnx2x_54618se_read_status()
11349 		DP(NETIF_MSG_LINK,  in bnx2x_54618se_read_status()
11351 		   vars->line_speed,  in bnx2x_54618se_read_status()
11352 		   (vars->duplex == DUPLEX_FULL));  in bnx2x_54618se_read_status()
11355 		bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_read_status()
11359 			vars->link_status |=  in bnx2x_54618se_read_status()
11361 		bnx2x_cl22_read(bp, phy,  in bnx2x_54618se_read_status()
11365 			vars->link_status |=  in bnx2x_54618se_read_status()
11368 		DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",  in bnx2x_54618se_read_status()
11369 			   vars->line_speed);  in bnx2x_54618se_read_status()
11371 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_54618se_read_status()
11373 		if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {  in bnx2x_54618se_read_status()
11375 			bnx2x_cl22_read(bp, phy, 0x5, &val);  in bnx2x_54618se_read_status()
11378 				vars->link_status |=  in bnx2x_54618se_read_status()
11381 				vars->link_status |=  in bnx2x_54618se_read_status()
11384 				vars->link_status |=  in bnx2x_54618se_read_status()
11387 				vars->link_status |=  in bnx2x_54618se_read_status()
11390 				vars->link_status |=  in bnx2x_54618se_read_status()
11393 			bnx2x_cl22_read(bp, phy, 0xa, &val);  in bnx2x_54618se_read_status()
11395 				vars->link_status |=  in bnx2x_54618se_read_status()
11398 				vars->link_status |=  in bnx2x_54618se_read_status()
11401 			if ((phy->flags & FLAGS_EEE) &&  in bnx2x_54618se_read_status()
11403 				bnx2x_eee_an_resolve(phy, params, vars);  in bnx2x_54618se_read_status()
11409 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,  in bnx2x_54618se_config_loopback()  argument
11412 	struct bnx2x *bp = params->bp;  in bnx2x_54618se_config_loopback()
11414 	u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;  in bnx2x_54618se_config_loopback()
11416 	DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");  in bnx2x_54618se_config_loopback()
11420 	bnx2x_cl22_write(bp, phy, 0x09, 3<<11);  in bnx2x_54618se_config_loopback()
11427 	bnx2x_cl22_read(bp, phy, 0x00, &val);  in bnx2x_54618se_config_loopback()
11430 	bnx2x_cl22_write(bp, phy, 0x00, val);  in bnx2x_54618se_config_loopback()
11436 	bnx2x_cl22_write(bp, phy, 0x18, 7);  in bnx2x_54618se_config_loopback()
11437 	bnx2x_cl22_read(bp, phy, 0x18, &val);  in bnx2x_54618se_config_loopback()
11438 	bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));  in bnx2x_54618se_config_loopback()
11441 	REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);  in bnx2x_54618se_config_loopback()
11443 	/* Maximum Frame Length (RW). Defines a 14-Bit maximum frame  in bnx2x_54618se_config_loopback()
11450 /*			SFX7101 PHY SECTION			  */
11452 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,  in bnx2x_7101_config_loopback()  argument
11455 	struct bnx2x *bp = params->bp;  in bnx2x_7101_config_loopback()
11457 	bnx2x_cl45_write(bp, phy,  in bnx2x_7101_config_loopback()
11461 static void bnx2x_7101_config_init(struct bnx2x_phy *phy,  in bnx2x_7101_config_init()  argument
11466 	struct bnx2x *bp = params->bp;  in bnx2x_7101_config_init()
11467 	DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");  in bnx2x_7101_config_init()
11471 		       MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);  in bnx2x_7101_config_init()
11473 	bnx2x_ext_phy_hw_reset(bp, params->port);  in bnx2x_7101_config_init()
11474 	bnx2x_wait_reset_complete(bp, phy, params);  in bnx2x_7101_config_init()
11476 	bnx2x_cl45_write(bp, phy,  in bnx2x_7101_config_init()
11478 	DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");  in bnx2x_7101_config_init()
11479 	bnx2x_cl45_write(bp, phy,  in bnx2x_7101_config_init()
11482 	bnx2x_ext_phy_set_pause(params, phy, vars);  in bnx2x_7101_config_init()
11484 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_config_init()
11487 	bnx2x_cl45_write(bp, phy,  in bnx2x_7101_config_init()
11491 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_config_init()
11494 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_config_init()
11496 	bnx2x_save_spirom_version(bp, params->port,  in bnx2x_7101_config_init()
11497 				  (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);  in bnx2x_7101_config_init()
11500 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,  in bnx2x_7101_read_status()  argument
11504 	struct bnx2x *bp = params->bp;  in bnx2x_7101_read_status()
11507 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_read_status()
11509 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_read_status()
11511 	DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",  in bnx2x_7101_read_status()
11513 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_read_status()
11515 	bnx2x_cl45_read(bp, phy,  in bnx2x_7101_read_status()
11517 	DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",  in bnx2x_7101_read_status()
11520 	/* If link is up print the AN outcome of the SFX7101 PHY */  in bnx2x_7101_read_status()
11522 		bnx2x_cl45_read(bp, phy,  in bnx2x_7101_read_status()
11525 		vars->line_speed = SPEED_10000;  in bnx2x_7101_read_status()
11526 		vars->duplex = DUPLEX_FULL;  in bnx2x_7101_read_status()
11527 		DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",  in bnx2x_7101_read_status()
11529 		bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);  in bnx2x_7101_read_status()
11530 		bnx2x_ext_phy_resolve_fc(phy, params, vars);  in bnx2x_7101_read_status()
11534 			vars->link_status |=  in bnx2x_7101_read_status()
11543 		return -EINVAL;  in bnx2x_7101_format_ver()
11549 	*len -= 4;  in bnx2x_7101_format_ver()
11553 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)  in bnx2x_sfx7101_sp_sw_reset()  argument
11557 	bnx2x_cl45_read(bp, phy,  in bnx2x_sfx7101_sp_sw_reset()
11563 		/* Writes a self-clearing reset */  in bnx2x_sfx7101_sp_sw_reset()
11564 		bnx2x_cl45_write(bp, phy,  in bnx2x_sfx7101_sp_sw_reset()
11569 		bnx2x_cl45_read(bp, phy,  in bnx2x_sfx7101_sp_sw_reset()
11578 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,  in bnx2x_7101_hw_reset()  argument
11581 	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,  in bnx2x_7101_hw_reset()
11582 		       MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);  in bnx2x_7101_hw_reset()
11583 	/* The PHY reset is controlled by GPIO 1 */  in bnx2x_7101_hw_reset()
11584 	bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,  in bnx2x_7101_hw_reset()
11585 		       MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);  in bnx2x_7101_hw_reset()
11588 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,  in bnx2x_7101_set_link_led()  argument
11592 	struct bnx2x *bp = params->bp;  in bnx2x_7101_set_link_led()
11605 	bnx2x_cl45_write(bp, phy,  in bnx2x_7101_set_link_led()
11612 /*			STATIC PHY DECLARATION			  */
12142 /* Populate the phy according. Main function: bnx2x_populate_phy   */
12147 				     struct bnx2x_phy *phy, u8 port,  in bnx2x_populate_preemphasis()  argument
12175 		phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);  in bnx2x_populate_preemphasis()
12176 		phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);  in bnx2x_populate_preemphasis()
12178 		phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);  in bnx2x_populate_preemphasis()
12179 		phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);  in bnx2x_populate_preemphasis()
12199 		DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);  in bnx2x_get_ext_phy_config()
12200 		return -EINVAL;  in bnx2x_get_ext_phy_config()
12206 				  struct bnx2x_phy *phy)  in bnx2x_populate_int_phy()  argument
12217 	DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);  in bnx2x_populate_int_phy()
12222 		*phy = phy_warpcore;  in bnx2x_populate_int_phy()
12224 			phy->flags |= FLAGS_4_PORT_MODE;  in bnx2x_populate_int_phy()
12226 			phy->flags &= ~FLAGS_4_PORT_MODE;  in bnx2x_populate_int_phy()
12237 			phy->supported &= (SUPPORTED_10baseT_Half |  in bnx2x_populate_int_phy()
12246 			phy->media_type = ETH_PHY_BASE_T;  in bnx2x_populate_int_phy()
12249 			phy->supported &= (SUPPORTED_1000baseT_Full |  in bnx2x_populate_int_phy()
12254 			phy->media_type = ETH_PHY_XFP_FIBER;  in bnx2x_populate_int_phy()
12257 			phy->supported &= (SUPPORTED_1000baseT_Full |  in bnx2x_populate_int_phy()
12262 			phy->media_type = ETH_PHY_SFPP_10G_FIBER;  in bnx2x_populate_int_phy()
12265 			phy->media_type = ETH_PHY_KR;  in bnx2x_populate_int_phy()
12266 			phy->supported &= (SUPPORTED_1000baseKX_Full |  in bnx2x_populate_int_phy()
12274 			phy->media_type = ETH_PHY_KR;  in bnx2x_populate_int_phy()
12275 			phy->flags |= FLAGS_WC_DUAL_MODE;  in bnx2x_populate_int_phy()
12276 			phy->supported &= (SUPPORTED_20000baseMLD2_Full |  in bnx2x_populate_int_phy()
12282 			phy->media_type = ETH_PHY_KR;  in bnx2x_populate_int_phy()
12283 			phy->flags |= FLAGS_WC_DUAL_MODE;  in bnx2x_populate_int_phy()
12284 			phy->supported &= (SUPPORTED_20000baseKR2_Full |  in bnx2x_populate_int_phy()
12291 			phy->flags &= ~FLAGS_TX_ERROR_CHECK;  in bnx2x_populate_int_phy()
12294 			DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",  in bnx2x_populate_int_phy()
12299 		/* Enable MDC/MDIO work-around for E3 A0 since free running MDC  in bnx2x_populate_int_phy()
12304 			phy->flags |= FLAGS_MDC_MDIO_WA;  in bnx2x_populate_int_phy()
12306 			phy->flags |= FLAGS_MDC_MDIO_WA_B0;  in bnx2x_populate_int_phy()
12313 			*phy = phy_serdes;  in bnx2x_populate_int_phy()
12319 			*phy = phy_xgxs;  in bnx2x_populate_int_phy()
12322 			DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");  in bnx2x_populate_int_phy()
12323 			return -EINVAL;  in bnx2x_populate_int_phy()
12326 	phy->addr = (u8)phy_addr;  in bnx2x_populate_int_phy()
12327 	phy->mdio_ctrl = bnx2x_get_emac_base(bp,  in bnx2x_populate_int_phy()
12331 		phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;  in bnx2x_populate_int_phy()
12333 		phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;  in bnx2x_populate_int_phy()
12335 	DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",  in bnx2x_populate_int_phy()
12336 		   port, phy->addr, phy->mdio_ctrl);  in bnx2x_populate_int_phy()
12338 	bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);  in bnx2x_populate_int_phy()
12347 				  struct bnx2x_phy *phy)  in bnx2x_populate_ext_phy()  argument
12354 	/* Select the phy type */  in bnx2x_populate_ext_phy()
12358 		*phy = phy_8073;  in bnx2x_populate_ext_phy()
12361 		*phy = phy_8705;  in bnx2x_populate_ext_phy()
12364 		*phy = phy_8706;  in bnx2x_populate_ext_phy()
12368 		*phy = phy_8726;  in bnx2x_populate_ext_phy()
12373 		*phy = phy_8727;  in bnx2x_populate_ext_phy()
12374 		phy->flags |= FLAGS_NOC;  in bnx2x_populate_ext_phy()
12379 		*phy = phy_8727;  in bnx2x_populate_ext_phy()
12382 		*phy = phy_8481;  in bnx2x_populate_ext_phy()
12385 		*phy = phy_84823;  in bnx2x_populate_ext_phy()
12388 		*phy = phy_84833;  in bnx2x_populate_ext_phy()
12391 		*phy = phy_84834;  in bnx2x_populate_ext_phy()
12394 		*phy = phy_84858;  in bnx2x_populate_ext_phy()
12398 		*phy = phy_54618se;  in bnx2x_populate_ext_phy()
12400 			phy->flags |= FLAGS_EEE;  in bnx2x_populate_ext_phy()
12403 		*phy = phy_7101;  in bnx2x_populate_ext_phy()
12406 		*phy = phy_null;  in bnx2x_populate_ext_phy()
12407 		return -EINVAL;  in bnx2x_populate_ext_phy()
12409 		*phy = phy_null;  in bnx2x_populate_ext_phy()
12410 		/* In case external PHY wasn't found */  in bnx2x_populate_ext_phy()
12413 			return -EINVAL;  in bnx2x_populate_ext_phy()
12417 	phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);  in bnx2x_populate_ext_phy()
12418 	bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);  in bnx2x_populate_ext_phy()
12420 	/* The shmem address of the phy version is located on different  in bnx2x_populate_ext_phy()
12427 		phy->ver_addr = shmem_base + offsetof(struct shmem_region,  in bnx2x_populate_ext_phy()
12439 			phy->ver_addr = shmem2_base +  in bnx2x_populate_ext_phy()
12447 			(SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -  in bnx2x_populate_ext_phy()
12450 	phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);  in bnx2x_populate_ext_phy()
12452 	if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {  in bnx2x_populate_ext_phy()
12453 		/* Remove 100Mb link supported for BCM84833/4 when phy fw  in bnx2x_populate_ext_phy()
12456 		u32 raw_ver = REG_RD(bp, phy->ver_addr);  in bnx2x_populate_ext_phy()
12459 			phy->supported &= ~(SUPPORTED_100baseT_Half |  in bnx2x_populate_ext_phy()
12463 	DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",  in bnx2x_populate_ext_phy()
12465 	DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",  in bnx2x_populate_ext_phy()
12466 		   phy->addr, phy->mdio_ctrl);  in bnx2x_populate_ext_phy()
12471 			      u32 shmem2_base, u8 port, struct bnx2x_phy *phy)  in bnx2x_populate_phy()  argument
12473 	phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;  in bnx2x_populate_phy()
12475 		return bnx2x_populate_int_phy(bp, shmem_base, port, phy);  in bnx2x_populate_phy()
12478 					port, phy);  in bnx2x_populate_phy()
12482 			      struct bnx2x_phy *phy,  in bnx2x_phy_def_cfg()  argument
12485 	struct bnx2x *bp = params->bp;  in bnx2x_phy_def_cfg()
12487 	/* Populate the default phy configuration for MF mode */  in bnx2x_phy_def_cfg()
12489 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12491 			port_feature_config[params->port].link_config2));  in bnx2x_phy_def_cfg()
12492 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12495 			port_hw_config[params->port].speed_capability_mask2));  in bnx2x_phy_def_cfg()
12497 		link_config = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12499 				port_feature_config[params->port].link_config));  in bnx2x_phy_def_cfg()
12500 		phy->speed_cap_mask = REG_RD(bp, params->shmem_base +  in bnx2x_phy_def_cfg()
12503 			port_hw_config[params->port].speed_capability_mask));  in bnx2x_phy_def_cfg()
12505 	DP(NETIF_MSG_LINK,  in bnx2x_phy_def_cfg()
12506 	   "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",  in bnx2x_phy_def_cfg()
12507 	   phy_index, link_config, phy->speed_cap_mask);  in bnx2x_phy_def_cfg()
12509 	phy->req_duplex = DUPLEX_FULL;  in bnx2x_phy_def_cfg()
12512 		phy->req_duplex = DUPLEX_HALF;  in bnx2x_phy_def_cfg()
12515 		phy->req_line_speed = SPEED_10;  in bnx2x_phy_def_cfg()
12518 		phy->req_duplex = DUPLEX_HALF;  in bnx2x_phy_def_cfg()
12521 		phy->req_line_speed = SPEED_100;  in bnx2x_phy_def_cfg()
12524 		phy->req_line_speed = SPEED_1000;  in bnx2x_phy_def_cfg()
12527 		phy->req_line_speed = SPEED_2500;  in bnx2x_phy_def_cfg()
12530 		phy->req_line_speed = SPEED_10000;  in bnx2x_phy_def_cfg()
12533 		phy->req_line_speed = SPEED_AUTO_NEG;  in bnx2x_phy_def_cfg()
12539 		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;  in bnx2x_phy_def_cfg()
12542 		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;  in bnx2x_phy_def_cfg()
12545 		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;  in bnx2x_phy_def_cfg()
12548 		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;  in bnx2x_phy_def_cfg()
12551 		phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_phy_def_cfg()
12561 	phy_config_swapped = params->multi_phy_config &  in bnx2x_phy_selection()
12564 	prio_cfg = params->multi_phy_config &  in bnx2x_phy_selection()
12592 	struct bnx2x *bp = params->bp;  in bnx2x_phy_probe()
12593 	struct bnx2x_phy *phy;  in bnx2x_phy_probe()  local
12594 	params->num_phys = 0;  in bnx2x_phy_probe()
12595 	DP(NETIF_MSG_LINK, "Begin phy probe\n");  in bnx2x_phy_probe()
12596 	phy_config_swapped = params->multi_phy_config &  in bnx2x_phy_probe()
12608 		DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"  in bnx2x_phy_probe()
12611 		phy = &params->phy[actual_phy_idx];  in bnx2x_phy_probe()
12612 		if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,  in bnx2x_phy_probe()
12613 				       params->shmem2_base, params->port,  in bnx2x_phy_probe()
12614 				       phy) != 0) {  in bnx2x_phy_probe()
12615 			params->num_phys = 0;  in bnx2x_phy_probe()
12616 			DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",  in bnx2x_phy_probe()
12621 				*phy = phy_null;  in bnx2x_phy_probe()
12622 			return -EINVAL;  in bnx2x_phy_probe()
12624 		if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)  in bnx2x_phy_probe()
12627 		if (params->feature_config_flags &  in bnx2x_phy_probe()
12629 			phy->flags &= ~FLAGS_TX_ERROR_CHECK;  in bnx2x_phy_probe()
12631 		if (!(params->feature_config_flags &  in bnx2x_phy_probe()
12633 			phy->flags |= FLAGS_MDC_MDIO_WA_G;  in bnx2x_phy_probe()
12635 		sync_offset = params->shmem_base +  in bnx2x_phy_probe()
12637 			dev_info.port_hw_config[params->port].media_type);  in bnx2x_phy_probe()
12640 		/* Update media type for non-PMF sync only for the first time  in bnx2x_phy_probe()
12647 			media_types |= ((phy->media_type &  in bnx2x_phy_probe()
12654 		bnx2x_phy_def_cfg(params, phy, phy_index);  in bnx2x_phy_probe()
12655 		params->num_phys++;  in bnx2x_phy_probe()
12658 	DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);  in bnx2x_phy_probe()
12665 	struct bnx2x *bp = params->bp;  in bnx2x_init_bmac_loopback()
12666 	vars->link_up = 1;  in bnx2x_init_bmac_loopback()
12667 	vars->line_speed = SPEED_10000;  in bnx2x_init_bmac_loopback()
12668 	vars->duplex = DUPLEX_FULL;  in bnx2x_init_bmac_loopback()
12669 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_init_bmac_loopback()
12670 	vars->mac_type = MAC_TYPE_BMAC;  in bnx2x_init_bmac_loopback()
12672 	vars->phy_flags = PHY_XGXS_FLAG;  in bnx2x_init_bmac_loopback()
12679 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);  in bnx2x_init_bmac_loopback()
12685 	struct bnx2x *bp = params->bp;  in bnx2x_init_emac_loopback()
12686 	vars->link_up = 1;  in bnx2x_init_emac_loopback()
12687 	vars->line_speed = SPEED_1000;  in bnx2x_init_emac_loopback()
12688 	vars->duplex = DUPLEX_FULL;  in bnx2x_init_emac_loopback()
12689 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_init_emac_loopback()
12690 	vars->mac_type = MAC_TYPE_EMAC;  in bnx2x_init_emac_loopback()
12692 	vars->phy_flags = PHY_XGXS_FLAG;  in bnx2x_init_emac_loopback()
12698 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0);  in bnx2x_init_emac_loopback()
12704 	struct bnx2x *bp = params->bp;  in bnx2x_init_xmac_loopback()
12705 	vars->link_up = 1;  in bnx2x_init_xmac_loopback()
12706 	if (!params->req_line_speed[0])  in bnx2x_init_xmac_loopback()
12707 		vars->line_speed = SPEED_10000;  in bnx2x_init_xmac_loopback()
12709 		vars->line_speed = params->req_line_speed[0];  in bnx2x_init_xmac_loopback()
12710 	vars->duplex = DUPLEX_FULL;  in bnx2x_init_xmac_loopback()
12711 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_init_xmac_loopback()
12712 	vars->mac_type = MAC_TYPE_XMAC;  in bnx2x_init_xmac_loopback()
12713 	vars->phy_flags = PHY_XGXS_FLAG;  in bnx2x_init_xmac_loopback()
12717 	bnx2x_set_aer_mmd(params, &params->phy[0]);  in bnx2x_init_xmac_loopback()
12718 	bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);  in bnx2x_init_xmac_loopback()
12719 	params->phy[INT_PHY].config_loopback(  in bnx2x_init_xmac_loopback()
12720 			&params->phy[INT_PHY],  in bnx2x_init_xmac_loopback()
12724 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_init_xmac_loopback()
12730 	struct bnx2x *bp = params->bp;  in bnx2x_init_umac_loopback()
12731 	vars->link_up = 1;  in bnx2x_init_umac_loopback()
12732 	vars->line_speed = SPEED_1000;  in bnx2x_init_umac_loopback()
12733 	vars->duplex = DUPLEX_FULL;  in bnx2x_init_umac_loopback()
12734 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_init_umac_loopback()
12735 	vars->mac_type = MAC_TYPE_UMAC;  in bnx2x_init_umac_loopback()
12736 	vars->phy_flags = PHY_XGXS_FLAG;  in bnx2x_init_umac_loopback()
12739 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_init_umac_loopback()
12745 	struct bnx2x *bp = params->bp;  in bnx2x_init_xgxs_loopback()
12746 	struct bnx2x_phy *int_phy = &params->phy[INT_PHY];  in bnx2x_init_xgxs_loopback()
12747 	vars->link_up = 1;  in bnx2x_init_xgxs_loopback()
12748 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_init_xgxs_loopback()
12749 	vars->duplex = DUPLEX_FULL;  in bnx2x_init_xgxs_loopback()
12750 	if (params->req_line_speed[0] == SPEED_1000)  in bnx2x_init_xgxs_loopback()
12751 		vars->line_speed = SPEED_1000;  in bnx2x_init_xgxs_loopback()
12752 	else if ((params->req_line_speed[0] == SPEED_20000) ||  in bnx2x_init_xgxs_loopback()
12753 		 (int_phy->flags & FLAGS_WC_DUAL_MODE))  in bnx2x_init_xgxs_loopback()
12754 		vars->line_speed = SPEED_20000;  in bnx2x_init_xgxs_loopback()
12756 		vars->line_speed = SPEED_10000;  in bnx2x_init_xgxs_loopback()
12762 	if (params->req_line_speed[0] == SPEED_1000) {  in bnx2x_init_xgxs_loopback()
12776 	if (params->loopback_mode == LOOPBACK_XGXS) {  in bnx2x_init_xgxs_loopback()
12778 		int_phy->config_loopback(int_phy, params);  in bnx2x_init_xgxs_loopback()
12780 		/* Set external phy loopback */  in bnx2x_init_xgxs_loopback()
12783 		      phy_index < params->num_phys; phy_index++)  in bnx2x_init_xgxs_loopback()
12784 			if (params->phy[phy_index].config_loopback)  in bnx2x_init_xgxs_loopback()
12785 				params->phy[phy_index].config_loopback(  in bnx2x_init_xgxs_loopback()
12786 					&params->phy[phy_index],  in bnx2x_init_xgxs_loopback()
12789 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_init_xgxs_loopback()
12791 	bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);  in bnx2x_init_xgxs_loopback()
12796 	struct bnx2x *bp = params->bp;  in bnx2x_set_rx_filter()
12802 	REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);  in bnx2x_set_rx_filter()
12805 		REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,  in bnx2x_set_rx_filter()
12809 	REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :  in bnx2x_set_rx_filter()
12817 	struct bnx2x *bp = params->bp;  in bnx2x_avoid_link_flap()
12828 	for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {  in bnx2x_avoid_link_flap()
12829 		struct bnx2x_phy *phy = &params->phy[phy_idx];  in bnx2x_avoid_link_flap()  local
12830 		if (phy->phy_specific_func) {  in bnx2x_avoid_link_flap()
12831 			DP(NETIF_MSG_LINK, "Calling PHY specific func\n");  in bnx2x_avoid_link_flap()
12832 			phy->phy_specific_func(phy, params, PHY_INIT);  in bnx2x_avoid_link_flap()
12834 		if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||  in bnx2x_avoid_link_flap()
12835 		    (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||  in bnx2x_avoid_link_flap()
12836 		    (phy->media_type == ETH_PHY_DA_TWINAX))  in bnx2x_avoid_link_flap()
12837 			bnx2x_verify_sfp_module(phy, params);  in bnx2x_avoid_link_flap()
12839 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_avoid_link_flap()
12845 	/* Re-enable the NIG/MAC */  in bnx2x_avoid_link_flap()
12851 				params->port));  in bnx2x_avoid_link_flap()
12855 				params->port));  in bnx2x_avoid_link_flap()
12857 		if (vars->line_speed < SPEED_10000)  in bnx2x_avoid_link_flap()
12862 		if (vars->line_speed < SPEED_10000)  in bnx2x_avoid_link_flap()
12876 	REG_WR(bp, params->lfa_base +  in bnx2x_avoid_link_flap()
12880 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_avoid_link_flap()
12892 	struct bnx2x *bp = params->bp;  in bnx2x_cannot_avoid_link_flap()
12896 	if (!params->lfa_base)  in bnx2x_cannot_avoid_link_flap()
12899 	REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12901 	       params->req_duplex[0] | (params->req_duplex[1] << 16));  in bnx2x_cannot_avoid_link_flap()
12903 	REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12905 	       params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));  in bnx2x_cannot_avoid_link_flap()
12907 	REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12909 	       params->req_line_speed[0] | (params->req_line_speed[1] << 16));  in bnx2x_cannot_avoid_link_flap()
12912 		REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12915 		       params->speed_cap_mask[cfg_idx]);  in bnx2x_cannot_avoid_link_flap()
12918 	tmp_val = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12921 	tmp_val |= params->req_fc_auto_adv;  in bnx2x_cannot_avoid_link_flap()
12923 	REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12926 	lfa_sts = REG_RD(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12942 	REG_WR(bp, params->lfa_base +  in bnx2x_cannot_avoid_link_flap()
12950 	struct bnx2x *bp = params->bp;  in bnx2x_phy_init()
12951 	DP(NETIF_MSG_LINK, "Phy Initialization started\n");  in bnx2x_phy_init()
12952 	DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",  in bnx2x_phy_init()
12953 		   params->req_line_speed[0], params->req_flow_ctrl[0]);  in bnx2x_phy_init()
12954 	DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",  in bnx2x_phy_init()
12955 		   params->req_line_speed[1], params->req_flow_ctrl[1]);  in bnx2x_phy_init()
12956 	DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);  in bnx2x_phy_init()
12957 	vars->link_status = 0;  in bnx2x_phy_init()
12958 	vars->phy_link_up = 0;  in bnx2x_phy_init()
12959 	vars->link_up = 0;  in bnx2x_phy_init()
12960 	vars->line_speed = 0;  in bnx2x_phy_init()
12961 	vars->duplex = DUPLEX_FULL;  in bnx2x_phy_init()
12962 	vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;  in bnx2x_phy_init()
12963 	vars->mac_type = MAC_TYPE_NONE;  in bnx2x_phy_init()
12964 	vars->phy_flags = 0;  in bnx2x_phy_init()
12965 	vars->check_kr2_recovery_cnt = 0;  in bnx2x_phy_init()
12966 	params->link_flags = PHY_INITIALIZED;  in bnx2x_phy_init()
12967 	/* Driver opens NIG-BRB filters */  in bnx2x_phy_init()
12974 		DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");  in bnx2x_phy_init()
12978 	DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",  in bnx2x_phy_init()
12983 	bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,  in bnx2x_phy_init()
12991 	if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)  in bnx2x_phy_init()
12992 		vars->link_status |= LINK_STATUS_PFC_ENABLED;  in bnx2x_phy_init()
12994 	if (params->num_phys == 0) {  in bnx2x_phy_init()
12995 		DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");  in bnx2x_phy_init()
12996 		return -EINVAL;  in bnx2x_phy_init()
13000 	DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);  in bnx2x_phy_init()
13001 	switch (params->loopback_mode) {  in bnx2x_phy_init()
13020 			if (params->switch_cfg == SWITCH_CFG_10G)  in bnx2x_phy_init()
13023 				bnx2x_serdes_deassert(bp, params->port);  in bnx2x_phy_init()
13030 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_phy_init()
13032 	bnx2x_update_mng_eee(params, vars->eee_status);  in bnx2x_phy_init()
13039 	struct bnx2x *bp = params->bp;  in bnx2x_link_reset()
13040 	u8 phy_index, port = params->port, clear_latch_ind = 0;  in bnx2x_link_reset()
13041 	DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);  in bnx2x_link_reset()
13043 	vars->link_status = 0;  in bnx2x_link_reset()
13045 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_link_reset()
13046 	vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |  in bnx2x_link_reset()
13048 	bnx2x_update_mng_eee(params, vars->eee_status);  in bnx2x_link_reset()
13065 		bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);  in bnx2x_link_reset()
13075 	/* The PHY reset is controlled by GPIO 1  in bnx2x_link_reset()
13083 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_reset()
13085 			if (params->phy[phy_index].link_reset) {  in bnx2x_link_reset()
13087 						  &params->phy[phy_index]);  in bnx2x_link_reset()
13088 				params->phy[phy_index].link_reset(  in bnx2x_link_reset()
13089 					&params->phy[phy_index],  in bnx2x_link_reset()
13092 			if (params->phy[phy_index].flags &  in bnx2x_link_reset()
13104 	if (params->phy[INT_PHY].link_reset)  in bnx2x_link_reset()
13105 		params->phy[INT_PHY].link_reset(  in bnx2x_link_reset()
13106 			&params->phy[INT_PHY], params);  in bnx2x_link_reset()
13116 		u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_link_reset()
13123 	vars->link_up = 0;  in bnx2x_link_reset()
13124 	vars->phy_flags = 0;  in bnx2x_link_reset()
13130 	struct bnx2x *bp = params->bp;  in bnx2x_lfa_reset()
13131 	vars->link_up = 0;  in bnx2x_lfa_reset()
13132 	vars->phy_flags = 0;  in bnx2x_lfa_reset()
13133 	params->link_flags &= ~PHY_INITIALIZED;  in bnx2x_lfa_reset()
13134 	if (!params->lfa_base)  in bnx2x_lfa_reset()
13140 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);  in bnx2x_lfa_reset()
13147 		bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);  in bnx2x_lfa_reset()
13156 	/* Clean the NIG-BRB using the network filters in a way that will  in bnx2x_lfa_reset()
13162 	 * Re-open the gate between the BMAC and the NIG, after verifying the  in bnx2x_lfa_reset()
13168 		bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);  in bnx2x_lfa_reset()
13175 	REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_lfa_reset()
13187 	struct bnx2x_phy phy[PORT_MAX];  in bnx2x_8073_common_init_phy()  local
13197 	/* PART1 - Reset both phys */  in bnx2x_8073_common_init_phy()
13198 	for (port = PORT_MAX - 1; port >= PORT_0; port--) {  in bnx2x_8073_common_init_phy()
13200 		/* In E2, same phy is using for port0 of the two paths */  in bnx2x_8073_common_init_phy()
13211 		/* Extract the ext phy address for the port */  in bnx2x_8073_common_init_phy()
13213 				       port_of_path, &phy[port]) !=  in bnx2x_8073_common_init_phy()
13215 			DP(NETIF_MSG_LINK, "populate_phy failed\n");  in bnx2x_8073_common_init_phy()
13216 			return -EINVAL;  in bnx2x_8073_common_init_phy()
13226 		/* Need to take the phy out of low power mode in order  in bnx2x_8073_common_init_phy()
13233 		/* Reset the phy */  in bnx2x_8073_common_init_phy()
13234 		bnx2x_cl45_write(bp, &phy[port],  in bnx2x_8073_common_init_phy()
13243 	if (phy[PORT_0].addr & 0x1) {  in bnx2x_8073_common_init_phy()
13244 		phy_blk[PORT_0] = &(phy[PORT_1]);  in bnx2x_8073_common_init_phy()
13245 		phy_blk[PORT_1] = &(phy[PORT_0]);  in bnx2x_8073_common_init_phy()
13247 		phy_blk[PORT_0] = &(phy[PORT_0]);  in bnx2x_8073_common_init_phy()
13248 		phy_blk[PORT_1] = &(phy[PORT_1]);  in bnx2x_8073_common_init_phy()
13251 	/* PART2 - Download firmware to both phys */  in bnx2x_8073_common_init_phy()
13252 	for (port = PORT_MAX - 1; port >= PORT_0; port--) {  in bnx2x_8073_common_init_phy()
13258 		DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",  in bnx2x_8073_common_init_phy()
13259 			   phy_blk[port]->addr);  in bnx2x_8073_common_init_phy()
13262 			return -EINVAL;  in bnx2x_8073_common_init_phy()
13281 	/* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */  in bnx2x_8073_common_init_phy()
13282 	for (port = PORT_MAX - 1; port >= PORT_0; port--) {  in bnx2x_8073_common_init_phy()
13294 		/* Read modify write the SPI-ROM version select register */  in bnx2x_8073_common_init_phy()
13315 	struct bnx2x_phy phy;  in bnx2x_8726_common_init_phy()  local
13316 	/* Use port1 because of the static port-swap */  in bnx2x_8726_common_init_phy()
13328 		/* In E2, same phy is using for port0 of the two paths */  in bnx2x_8726_common_init_phy()
13336 		/* Extract the ext phy address for the port */  in bnx2x_8726_common_init_phy()
13338 				       port, &phy) !=  in bnx2x_8726_common_init_phy()
13340 			DP(NETIF_MSG_LINK, "populate phy failed\n");  in bnx2x_8726_common_init_phy()
13341 			return -EINVAL;  in bnx2x_8726_common_init_phy()
13344 		/* Reset phy*/  in bnx2x_8726_common_init_phy()
13345 		bnx2x_cl45_write(bp, &phy,  in bnx2x_8726_common_init_phy()
13410 	struct bnx2x_phy phy[PORT_MAX];  in bnx2x_8727_common_init_phy()  local
13428 	/* Initiate PHY reset*/  in bnx2x_8727_common_init_phy()
13437 	/* PART1 - Reset both phys */  in bnx2x_8727_common_init_phy()
13438 	for (port = PORT_MAX - 1; port >= PORT_0; port--) {  in bnx2x_8727_common_init_phy()
13441 		/* In E2, same phy is using for port0 of the two paths */  in bnx2x_8727_common_init_phy()
13452 		/* Extract the ext phy address for the port */  in bnx2x_8727_common_init_phy()
13454 				       port_of_path, &phy[port]) !=  in bnx2x_8727_common_init_phy()
13456 			DP(NETIF_MSG_LINK, "populate phy failed\n");  in bnx2x_8727_common_init_phy()
13457 			return -EINVAL;  in bnx2x_8727_common_init_phy()
13468 		/* Reset the phy */  in bnx2x_8727_common_init_phy()
13469 		bnx2x_cl45_write(bp, &phy[port],  in bnx2x_8727_common_init_phy()
13475 	if (phy[PORT_0].addr & 0x1) {  in bnx2x_8727_common_init_phy()
13476 		phy_blk[PORT_0] = &(phy[PORT_1]);  in bnx2x_8727_common_init_phy()
13477 		phy_blk[PORT_1] = &(phy[PORT_0]);  in bnx2x_8727_common_init_phy()
13479 		phy_blk[PORT_0] = &(phy[PORT_0]);  in bnx2x_8727_common_init_phy()
13480 		phy_blk[PORT_1] = &(phy[PORT_1]);  in bnx2x_8727_common_init_phy()
13482 	/* PART2 - Download firmware to both phys */  in bnx2x_8727_common_init_phy()
13483 	for (port = PORT_MAX - 1; port >= PORT_0; port--) {  in bnx2x_8727_common_init_phy()
13488 		DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",  in bnx2x_8727_common_init_phy()
13489 			   phy_blk[port]->addr);  in bnx2x_8727_common_init_phy()
13492 			return -EINVAL;  in bnx2x_8727_common_init_phy()
13493 		/* Disable PHY transmitter output */  in bnx2x_8727_common_init_phy()
13513 	DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",  in bnx2x_84833_common_init_phy()
13557 		rc = -EINVAL;  in bnx2x_ext_phy_common_init()
13560 		DP(NETIF_MSG_LINK,  in bnx2x_ext_phy_common_init()
13567 		netdev_err(bp->dev,  "Warning: PHY was not initialized,"  in bnx2x_ext_phy_common_init()
13583 	DP(NETIF_MSG_LINK, "Begin common phy init\n");  in bnx2x_common_init_phy()
13594 		DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",  in bnx2x_common_init_phy()
13617 	struct bnx2x *bp = params->bp;  in bnx2x_check_over_curr()
13619 	u8 port = params->port;  in bnx2x_check_over_curr()
13622 	cfg_pin = (REG_RD(bp, params->shmem_base +  in bnx2x_check_over_curr()
13633 		if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {  in bnx2x_check_over_curr()
13634 			netdev_err(bp->dev, "Error:  Power fault on Port %d has"  in bnx2x_check_over_curr()
13641 			 params->port);  in bnx2x_check_over_curr()
13642 			vars->phy_flags |= PHY_OVER_CURRENT_FLAG;  in bnx2x_check_over_curr()
13646 		vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;  in bnx2x_check_over_curr()
13654 	struct bnx2x *bp = params->bp;  in bnx2x_analyze_link_error()
13657 	u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;  in bnx2x_analyze_link_error()
13665 		DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");  in bnx2x_analyze_link_error()
13668 		DP(NETIF_MSG_LINK, "Analyze TX Fault\n");  in bnx2x_analyze_link_error()
13671 		DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");  in bnx2x_analyze_link_error()
13673 	DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,  in bnx2x_analyze_link_error()
13677 	if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)  in bnx2x_analyze_link_error()
13680 	/* a. Update shmem->link_status accordingly  in bnx2x_analyze_link_error()
13681 	 * b. Update link_vars->link_up  in bnx2x_analyze_link_error()
13684 		vars->link_status &= ~LINK_STATUS_LINK_UP;  in bnx2x_analyze_link_error()
13685 		vars->link_status |= link_flag;  in bnx2x_analyze_link_error()
13686 		vars->link_up = 0;  in bnx2x_analyze_link_error()
13687 		vars->phy_flags |= phy_flag;  in bnx2x_analyze_link_error()
13690 		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);  in bnx2x_analyze_link_error()
13691 		/* Set LED mode to off since the PHY doesn't know about these  in bnx2x_analyze_link_error()
13696 		vars->link_status |= LINK_STATUS_LINK_UP;  in bnx2x_analyze_link_error()
13697 		vars->link_status &= ~link_flag;  in bnx2x_analyze_link_error()
13698 		vars->link_up = 1;  in bnx2x_analyze_link_error()
13699 		vars->phy_flags &= ~phy_flag;  in bnx2x_analyze_link_error()
13703 		REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);  in bnx2x_analyze_link_error()
13710 	bnx2x_update_mng(params, vars->link_status);  in bnx2x_analyze_link_error()
13713 	vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;  in bnx2x_analyze_link_error()
13733 	struct bnx2x *bp = params->bp;  in bnx2x_check_half_open_conn()
13737 	if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||  in bnx2x_check_half_open_conn()
13738 	    (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))  in bnx2x_check_half_open_conn()
13749 		mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;  in bnx2x_check_half_open_conn()
13763 		   (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {  in bnx2x_check_half_open_conn()
13767 		mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :  in bnx2x_check_half_open_conn()
13784 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,  in bnx2x_sfp_tx_fault_detection()  argument
13788 	struct bnx2x *bp = params->bp;  in bnx2x_sfp_tx_fault_detection()
13790 	u8 led_change, port = params->port;  in bnx2x_sfp_tx_fault_detection()
13793 	cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,  in bnx2x_sfp_tx_fault_detection()
13799 		DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);  in bnx2x_sfp_tx_fault_detection()
13811 		if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {  in bnx2x_sfp_tx_fault_detection()
13813 			vars->link_status |= LINK_STATUS_SFP_TX_FAULT;  in bnx2x_sfp_tx_fault_detection()
13816 			vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;  in bnx2x_sfp_tx_fault_detection()
13820 		if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {  in bnx2x_sfp_tx_fault_detection()
13821 			DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",  in bnx2x_sfp_tx_fault_detection()
13829 			       struct bnx2x_phy *phy)  in bnx2x_kr2_recovery()  argument
13831 	struct bnx2x *bp = params->bp;  in bnx2x_kr2_recovery()
13832 	DP(NETIF_MSG_LINK, "KR2 recovery\n");  in bnx2x_kr2_recovery()
13833 	bnx2x_warpcore_enable_AN_KR2(phy, params, vars);  in bnx2x_kr2_recovery()
13834 	bnx2x_warpcore_restart_AN_KR(phy, params);  in bnx2x_kr2_recovery()
13839 			       struct bnx2x_phy *phy)  in bnx2x_check_kr2_wa()  argument
13841 	struct bnx2x *bp = params->bp;  in bnx2x_check_kr2_wa()
13850 	if (vars->check_kr2_recovery_cnt > 0) {  in bnx2x_check_kr2_wa()
13851 		vars->check_kr2_recovery_cnt--;  in bnx2x_check_kr2_wa()
13855 	sigdet = bnx2x_warpcore_get_sigdet(phy, params);  in bnx2x_check_kr2_wa()
13857 		if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {  in bnx2x_check_kr2_wa()
13858 			bnx2x_kr2_recovery(params, vars, phy);  in bnx2x_check_kr2_wa()
13859 			DP(NETIF_MSG_LINK, "No sigdet\n");  in bnx2x_check_kr2_wa()
13864 	lane = bnx2x_get_warpcore_lane(phy, params);  in bnx2x_check_kr2_wa()
13865 	CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,  in bnx2x_check_kr2_wa()
13867 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_check_kr2_wa()
13869 	bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,  in bnx2x_check_kr2_wa()
13871 	bnx2x_set_aer_mmd(params, phy);  in bnx2x_check_kr2_wa()
13875 		if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {  in bnx2x_check_kr2_wa()
13876 			bnx2x_kr2_recovery(params, vars, phy);  in bnx2x_check_kr2_wa()
13877 			DP(NETIF_MSG_LINK, "No BP\n");  in bnx2x_check_kr2_wa()
13883 	 * but only KX is advertised, declare this link partner as non-KR2  in bnx2x_check_kr2_wa()
13890 	/* In case KR2 is already disabled, check if we need to re-enable it */  in bnx2x_check_kr2_wa()
13891 	if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {  in bnx2x_check_kr2_wa()
13893 			DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,  in bnx2x_check_kr2_wa()
13895 			bnx2x_kr2_recovery(params, vars, phy);  in bnx2x_check_kr2_wa()
13902 		DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);  in bnx2x_check_kr2_wa()
13903 		bnx2x_disable_kr2(params, vars, phy);  in bnx2x_check_kr2_wa()
13905 		bnx2x_warpcore_restart_AN_KR(phy, params);  in bnx2x_check_kr2_wa()
13913 	struct bnx2x *bp = params->bp;  in bnx2x_period_func()
13915 		if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {  in bnx2x_period_func()
13916 			bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);  in bnx2x_period_func()
13919 				DP(NETIF_MSG_LINK, "Fault detection failed\n");  in bnx2x_period_func()
13925 		struct bnx2x_phy *phy = &params->phy[INT_PHY];  in bnx2x_period_func()  local
13926 		bnx2x_set_aer_mmd(params, phy);  in bnx2x_period_func()
13927 		if (((phy->req_line_speed == SPEED_AUTO_NEG) &&  in bnx2x_period_func()
13928 		     (phy->speed_cap_mask &  in bnx2x_period_func()
13930 		    (phy->req_line_speed == SPEED_20000))  in bnx2x_period_func()
13931 			bnx2x_check_kr2_wa(params, vars, phy);  in bnx2x_period_func()
13933 		if (vars->rx_tx_asic_rst)  in bnx2x_period_func()
13934 			bnx2x_warpcore_config_runtime(phy, params, vars);  in bnx2x_period_func()
13936 		if ((REG_RD(bp, params->shmem_base +  in bnx2x_period_func()
13938 				port_hw_config[params->port].default_cfg))  in bnx2x_period_func()
13941 			if (bnx2x_is_sfp_module_plugged(phy, params)) {  in bnx2x_period_func()
13942 				bnx2x_sfp_tx_fault_detection(phy, params, vars);  in bnx2x_period_func()
13943 			} else if (vars->link_status &  in bnx2x_period_func()
13946 				vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;  in bnx2x_period_func()
13947 				vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;  in bnx2x_period_func()
13949 				bnx2x_update_mng(params, vars->link_status);  in bnx2x_period_func()
13961 	struct bnx2x_phy phy;  in bnx2x_fan_failure_det_req()  local
13965 				       port, &phy)  in bnx2x_fan_failure_det_req()
13967 			DP(NETIF_MSG_LINK, "populate phy failed\n");  in bnx2x_fan_failure_det_req()
13970 		fan_failure_det_req |= (phy.flags &  in bnx2x_fan_failure_det_req()
13979 	struct bnx2x *bp = params->bp;  in bnx2x_hw_reset_phy()
13981 	bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,  in bnx2x_hw_reset_phy()
13989 		if (params->phy[phy_index].hw_reset) {  in bnx2x_hw_reset_phy()
13990 			params->phy[phy_index].hw_reset(  in bnx2x_hw_reset_phy()
13991 				&params->phy[phy_index],  in bnx2x_hw_reset_phy()
13993 			params->phy[phy_index] = phy_null;  in bnx2x_hw_reset_phy()
14013 		struct bnx2x_phy phy;  in bnx2x_init_mod_abs_int()  local
14017 					       shmem2_base, port, &phy)  in bnx2x_init_mod_abs_int()
14019 				DP(NETIF_MSG_LINK, "populate phy failed\n");  in bnx2x_init_mod_abs_int()
14022 			if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {  in bnx2x_init_mod_abs_int()
14040 	vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<  in bnx2x_init_mod_abs_int()
14046 	REG_WR(bp, sync_offset, vars->aeu_int_mask);  in bnx2x_init_mod_abs_int()
14048 	DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",  in bnx2x_init_mod_abs_int()
14049 		       gpio_num, gpio_port, vars->aeu_int_mask);  in bnx2x_init_mod_abs_int()
14058 	aeu_mask |= vars->aeu_int_mask;  in bnx2x_init_mod_abs_int()