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Searched +full:dp +full:- +full:lane +full:- +full:mux (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
129 /* vo-grf */
162 struct typec_mux_dev *mux; member
179 bool hs; /* flag for high-speed */
181 /* utilized for DP */
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/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
12 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON */
18 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
32 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
38 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
61 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
65 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW
118 // for example, 1080p -> 8K is 4.0, or 4000 raw value
126 // for example, 8K -> 1080p is 0.25, or 250 raw value
138 * DOC: color-management-caps
143 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
150 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
166 * struct dpp_color_caps - color pipeline capabilities for display pipe and
171 * just plain 256-entry lookup
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/linux/drivers/gpu/drm/bridge/
H A Dti-sn65dsi86.c1 // SPDX-License-Identifier: GPL-2.0
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
159 * serves double-duty of keeping track of the direction and
165 * each other's read-modify-write.
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); in ti_sn65dsi86_read_u16()
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-usb-legacy.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-misc-v3.h"
25 #include "phy-qcom-qmp-pcs-usb-v4.h"
26 #include "phy-qcom-qmp-pcs-usb-v5.h"
28 #include "phy-qcom-qmp-dp-com-v3.h"
31 /* DP PHY soft reset */
33 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
37 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-evb2-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/clock/rockchip,rk3588-cru.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
17 compatible = "rockchip,rk3588-evb2-v10", "rockchip,rk3588";
25 stdout-path = "serial2:1500000n8";
28 hdmi-con {
29 compatible = "hdmi-connector";
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H A Drk3588-firefly-itx-3588j.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/pwm/pwm.h>
10 #include <dt-bindings/soc/rockchip,vop2.h>
11 #include "dt-bindings/usb/pd.h"
13 #include "rk3588-firefly-core-3588j.dtsi"
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H A Drk3588-turing-rk1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Based on RK3588-EVB1 devicetree
11 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
27 fan-supply = <&vcc5v0_sys>;
28 pinctrl-names = "default";
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H A Drk3588s-indiedroid-nova.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/soc/rockchip,vop2.h>
9 #include <dt-bindings/usb/pd.h>
16 adc-keys-0 {
17 compatible = "adc-keys";
18 io-channel-names = "buttons";
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H A Drk3588-evb1-v10.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,vop2.h>
13 #include <dt-bindings/usb/pd.h>
18 compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
26 stdout-path = "serial2:1500000n8";
29 adc-keys {
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
704 // =0: DP encoder
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
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