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/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst82 * `Downstream Ports` typically connected to `Host Bridge Ports`.
104 only has downstream port connections.
110 contains one or more decoders used to route memory requests downstream ports,
133 * The root has a downstream port connection to a host bridge
137 * The host bridge has one or more downstream port connections to switch
145 upstream and downstream ports.
242 Decoders may have one or more `Downstream Targets` if configured to interleave
275 the *immediate downstream targets*, not the entire interleave set.
300 of `Switch Decoder` due to having downstream targets. ::
323 decoder and downstream target ports. Interleaving done within a switch decoder
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/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dintra-hb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
234 applies the interleave across the downstream ports :code:`port1` and
H A Dhb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
250 applies the interleave across the downstream ports :code:`port1` and
H A Dsingle-device.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
H A Dmulti-interleave.rst47 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
51 The `ports:root0` section lays out how each of these downstream ports are
80 This chunk shows the available downstream ports associated with the CXL Host
81 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
326 applies the interleave across the downstream ports :code:`port1` and
/linux/include/linux/
H A Di2c-atr.h55 * struct i2c_atr_adap_desc - An ATR downstream bus descriptor
106 * i2c_atr_add_adapter - Create a child ("downstream") I2C bus.
111 * devices on the downstream bus will result in calls to the
126 * i2c_atr_del_adapter - Remove a child ("downstream") I2C bus added by
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi141 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
149 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
157 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
165 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
/linux/include/uapi/linux/usb/
H A Dcharger.h11 * SDP (Standard Downstream Port)
13 * CDP (Charging Downstream Port)
/linux/arch/arm/mach-omap2/
H A Dclockdomain.c938 * into active or idle states, as needed by downstream clocks. If the
939 * clockdomain has any downstream clocks enabled in the clock
980 * active or idle states, as needed by downstream clocks. If the
981 * clockdomain has any downstream clocks enabled in the clock
998 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1036 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1111 * clkdm_clk_enable - add an enabled downstream clock to this clkdm
1113 * @unused: struct clk * of the enabled downstream clock
1152 * clkdm_clk_disable - remove an enabled downstream clock from this clkdm
1154 * @clk: struct clk * of the disabled downstream clock
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-atr.yaml14 ("upstream") port and N I2C master child ("downstream") ports, and
15 forwards transactions from upstream to the appropriate downstream port
H A Di2c-mux-ltc4306.txt24 - ltc,downstream-accelerators-enable: Enables the rise time accelerators
25 on the downstream port.
/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h213 #define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream
215 #define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)
433 #define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream
451 #define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream
461 #define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2
462 #define MO_VIPD_LNGTH 0x340054 // VIP downstream line length
519 #define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream
522 #define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2
523 #define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length
/linux/Documentation/ABI/testing/
H A Dusb-charger-uevent14 USB_CHARGER_SDP_TYPE Standard Downstream Port
15 USB_CHARGER_CDP_TYPE Charging Downstream Port
H A Dsysfs-bus-usb-lvstest16 Set "U1 timeout" for the downstream port where Link Layer
24 Set "U2 timeout" for the downstream port where Link Layer
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-clkgen.c424 * from top to bottom, from upstream to downstream. Read TRM for details.
605 /* downstream of div_50m_a53 */
647 /* downstream of div_top_axi0 */
682 /* upon are gate clocks directly downstream of muxes */
684 /* downstream of clk_div_top_rp_cmn_div2 */
692 * downstream of clk_gate_rp_cpu_normal
708 /* downstream of div_50m_a53 */
728 /* gate clocks downstream from div clocks one-to-one */
747 /* downstream of clk_div_top_axi0 */
774 /* downstream of DIV clocks which are sourced from clk_div_top_axi0 */
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/linux/Documentation/devicetree/bindings/misc/
H A Dti,fpc202.yaml41 description: Downstream device ports 0 and 1
47 Downstream port ID
/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst9 all Endpoints downstream these Root Ports.
66 PMU could only monitor the performance of traffic downstream target Root
67 Ports or downstream target Endpoint. PCIe PMU driver support "port" and
/linux/include/cxl/
H A Devent.h216 RCH_DP, /* Restricted CXL Host Downstream Port */
221 DSP, /* CXL Downstream Switch Port */
234 * Except for RCH Downstream Port, all the remaining CXL Agent
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pxl2dpi.yaml37 A phandle which points to companion PXL2DPI which is used by downstream
50 description: The PXL2DPI output port node to downstream bridge.
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994-sony-xperia-kitakami.dtsi72 /* This is for getting crash logs using Android downstream kernels */
160 * specific downstream MDSS/backlight nodes in the active DTB.
162 * LK with the downstream DTB appended and then, only from there, load
459 * Downstream pushes 2.95V to the sdhci device,
/linux/drivers/gpu/drm/msm/
H A DNOTES77 the downstream android fbdev driver), bitfield sizes, etc. My current
85 parse logged register reads/writes (both from downstream android fbdev
/linux/Documentation/i2c/
H A Di2c-address-translators.rst14 ("upstream") port and N I2C master child ("downstream") ports, and
15 forwards transactions from upstream to the appropriate downstream port
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml300 - description: bus clock required for downstream bus access and for
342 - description: bus clock required for downstream bus access and for
369 - description: bus clock required for downstream bus access
389 - description: bus clock required for downstream bus access and for
446 - description: bus clock required for downstream bus access and for
/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi91 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
108 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
125 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
/linux/drivers/gpu/drm/amd/display/include/
H A Dddc_service_types.h81 /* Dongle's downstream count. */
83 /* Is dongle's downstream count info field (downstrm_sink_count)

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