| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
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| /freebsd/sys/dev/sound/macio/ |
| H A D | aoa.c | 71 aoa_dma_set_program(struct aoa_dma *dma) in aoa_dma_set_program() argument
76 addr = (u_int32_t) sndbuf_getbufaddr(dma->buf); in aoa_dma_set_program()
77 KASSERT(dma->bufsz == sndbuf_getsize(dma->buf), ("bad size")); in aoa_dma_set_program()
79 dma->slots = dma->bufsz / dma->blksz; in aoa_dma_set_program()
81 for (i = 0; i < dma->slots; ++i) { in aoa_dma_set_program()
82 dbdma_insert_command(dma->channel, in aoa_dma_set_program()
87 dma->blksz, /* count */ in aoa_dma_set_program()
91 dma->slots + 1 /* branch_slot */ in aoa_dma_set_program()
94 addr += dma->blksz; in aoa_dma_set_program()
98 dbdma_insert_branch(dma->channel, dma->slots, 0); in aoa_dma_set_program()
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| /freebsd/sys/dev/ata/ |
| H A D | ata-dma.c | 53 static MALLOC_DEFINE(M_ATADMA, "ata_dma", "ATA driver DMA");
70 if (ch->dma.alloc == NULL) in ata_dmainit()
71 ch->dma.alloc = ata_dmaalloc; in ata_dmainit()
72 if (ch->dma.free == NULL) in ata_dmainit()
73 ch->dma.free = ata_dmafree; in ata_dmainit()
74 if (ch->dma.setprd == NULL) in ata_dmainit()
75 ch->dma.setprd = ata_dmasetprd; in ata_dmainit()
76 if (ch->dma.load == NULL) in ata_dmainit()
77 ch->dma.load = ata_dmaload; in ata_dmainit()
78 if (ch->dma.unload == NULL) in ata_dmainit()
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | qcom,gpi.yaml | 4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
23 - qcom,sdm845-gpi-dma
24 - qcom,sm6350-gpi-dma
27 - qcom,qcm2290-gpi-dma
28 - qcom,qdu1000-gpi-dma
29 - qcom,sc7280-gpi-dma
30 - qcom,sdx75-gpi-dma
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| H A D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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| H A D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - dma-channels : Number of DMA channels supported. Should be 16.
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| H A D | intel,ldma.yaml | 4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
7 title: Lightning Mountain centralized DMA controllers.
14 - $ref: dma-controller.yaml#
31 "#dma-cells":
34 The first cell is the peripheral's DMA request line.
38 dma-channels:
42 dma-channel-mask:
58 intel,dma-poll-cnt:
61 DMA descriptor polling counter is used to control the poling mechanism
64 intel,dma-byte-en:
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| H A D | sprd,sc9860-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
22 const: sprd,sc9860-dma
33 - description: DMA enable clock
34 - description: optional ashb_eb clock, only for the AGCP DMA controller
42 '#dma-cells':
45 dma-channels:
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| H A D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
22 - reset-names: must contain at least "dma", and optional is "dma-ocp".
30 #dma-cells = <1>;
31 #dma-channels = <8>;
32 #dma-requests = <32>;
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| H A D | owl-dma.txt | 1 * Actions Semi Owl SoCs DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "actions,s900-dma".
7 - reg: Should contain DMA registers location and length.
9 - #dma-cells: Must be <1>. Used to represent the number of integer
11 - dma-channels: Physical channels supported.
12 - dma-requests: Number of DMA request signals supported by the controller.
13 Refer to Documentation/devicetree/bindings/dma/dma.txt
14 - clocks: Phandle and Specifier of the clock feeding the DMA controller.
19 dma: dma-controller@e0260000 {
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| H A D | fsl,mxs-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
13 - $ref: dma-controller.yaml#
18 const: fsl,imx8qxp-dma-apbh
31 - fsl,imx6q-dma-apbh
32 - fsl,imx6sx-dma-apbh
33 - fsl,imx7d-dma-apbh
34 - fsl,imx8qxp-dma-apbh
35 - const: fsl,imx28-dma-apbh
37 - fsl,imx23-dma-apbh
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| H A D | owl-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
18 - $ref: dma-controller.yaml#
23 - actions,s500-dma
24 - actions,s700-dma
25 - actions,s900-dma
33 DMA channels.
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| H A D | allwinner,sun50i-a64-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
7 title: Allwinner A64 DMA Controller
14 - $ref: dma-controller.yaml#
17 "#dma-cells":
24 - allwinner,sun20i-d1-dma
25 - allwinner,sun50i-a64-dma
26 - allwinner,sun50i-a100-dma
27 - allwinner,sun50i-h6-dma
29 - const: allwinner,sun8i-r40-dma
30 - const: allwinner,sun50i-a64-dma
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| H A D | ingenic,dma.yaml | 4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
7 title: Ingenic SoCs DMA Controller
13 - $ref: dma-controller.yaml#
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
21 - ingenic,jz4755-dma
22 - ingenic,jz4760-dma
25 - ingenic,jz4760b-dma
28 - ingenic,jz4770-dma
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| H A D | dma-router.yaml | 4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
7 title: DMA Router Common Properties
13 - $ref: dma-common.yaml#
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
23 pattern: "^dma
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| H A D | snps,dma-spear1340.yaml | 4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
7 title: Synopsys Designware DMA Controller
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
22 - renesas,r9a06g032-dma
23 - const: renesas,rzn1-dma
26 "#dma-cells":
30 First cell is a phandle pointing to the DMA controller. Second one is
31 the DMA request line number. Third cell is the memory master identifier
34 cell is an optional mask of the DMA channels permitted to be allocated
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| H A D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
21 - brcm,dma-channel-mask: Bit mask representing the channels
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| H A D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "sprd,sc9860-dma".
7 - reg: Should contain DMA registers location and length.
9 - #dma-cells: must be <1>. Used to represent the number of integer
11 - dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
16 - #dma-channels : Number of DMA channels supported. Should be 32.
21 apdma: dma-controller@20100000 {
22 compatible = "sprd,sc9860-dma";
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| H A D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
8 the dma/dma.txt file for a more detailed description of binding.
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
22 dma0: dma@14000 {
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| H A D | st,stm32-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
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| H A D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
28 * while DMA controller may not able to distinguish the irq channel
33 pdma: dma-controller@d4000000 {
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| /freebsd/sys/dev/oce/ |
| H A D | oce_util.c | 50 * @brief Allocate DMA memory
53 * @param dma dma memory area
58 oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags) in oce_dma_alloc() argument
62 memset(dma, 0, sizeof(OCE_DMA_MEM)); in oce_dma_alloc()
69 size, 1, size, 0, NULL, NULL, &dma->tag); in oce_dma_alloc()
72 rc = bus_dmamem_alloc(dma->tag, in oce_dma_alloc()
73 &dma->ptr, in oce_dma_alloc()
76 &dma->map); in oce_dma_alloc()
79 dma->paddr = 0; in oce_dma_alloc()
81 rc = bus_dmamap_load(dma->tag, in oce_dma_alloc()
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| /freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
| H A D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
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| /freebsd/sys/dev/drm2/ |
| H A D | drm_dma.c | 3 * DMA IOCTL and function support
40 * Initialize the DMA data.
51 dev->dma = malloc(sizeof(*dev->dma), DRM_MEM_DRIVER, M_NOWAIT | M_ZERO); in drm_dma_setup()
52 if (!dev->dma) in drm_dma_setup()
56 memset(&dev->dma->bufs[i], 0, sizeof(dev->dma->bufs[0])); in drm_dma_setup()
62 * Cleanup the DMA resources.
66 * Free all pages associated with DMA buffers, the buffers and pages lists, and
67 * finally the drm_device::dma structure itself.
71 struct drm_device_dma *dma = dev->dma; in drm_dma_takedown() local
74 if (!dma) in drm_dma_takedown()
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| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
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