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/linux/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A DKbuild1 # SPDX-License-Identifier: MIT
2 nvkm-y += nvkm/engine/dma/base.o
3 nvkm-y += nvkm/engine/dma/nv04.o
4 nvkm-y += nvkm/engine/dma/nv50.o
5 nvkm-y += nvkm/engine/dma/gf100.o
6 nvkm-y += nvkm/engine/dma/gf119.o
7 nvkm-y += nvkm/engine/dma/gv100.o
9 nvkm-y += nvkm/engine/dma/user.o
10 nvkm-y += nvkm/engine/dma/usernv04.o
11 nvkm-y += nvkm/engine/dma/usernv50.o
[all …]
H A Dbase.c27 #include <engine/fifo.h>
36 struct nvkm_dma *dma = nvkm_dma(oclass->engine); in nvkm_dma_oclass_new() local
40 ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); in nvkm_dma_oclass_new()
42 *pobject = &dmaobj->object; in nvkm_dma_oclass_new()
55 return nvkm_dma_oclass_new(oclass->engine->subdev.device, in nvkm_dma_oclass_fifo_new()
73 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
74 sclass->engn = oclass; in nvkm_dma_oclass_base_get()
86 oclass->base = nvkm_dma_sclass[index]; in nvkm_dma_oclass_fifo_get()
93 nvkm_dma_dtor(struct nvkm_engine *engine) in nvkm_dma_dtor() argument
95 return nvkm_dma(engine); in nvkm_dma_dtor()
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/linux/Documentation/driver-api/dmaengine/
H A Dclient.rst2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
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/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ddma-engine.txt1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
8 - compatible: "cavium,octeon-5750-bootbus-dma"
12 - reg: The base address of the DMA Engine's register bank.
14 - interrupts: A single interrupt specifier.
17 dma0: dma-engine@1180000000100 {
18 compatible = "cavium,octeon-5750-bootbus-dma";
/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c31 * DMA
33 * DMA engine. The programming model is very similar
34 * to the 3D engine (ring buffer, IBs, etc.), but the
35 * DMA controller has it's own packet format that is
36 * different form the PM4 format used by the 3D engine.
43 * r600_dma_get_rptr - get the current read pointer
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
78 * r600_dma_set_wptr - commit the write pointer
[all …]
H A Devergreen_dma.c31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
37 * the fence seq number and DMA trap packet to generate
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit()
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
59 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
64 * Schedule an IB in the DMA ring (evergreen).
69 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_dma_ring_ib_execute()
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H A Dni_dma.c32 * DMA
34 * DMA engine. The programming model is very similar
35 * to the 3D engine (ring buffer, IBs, etc.), but the
36 * DMA controller has it's own packet format that is
37 * different form the PM4 format used by the 3D engine.
41 * Cayman and newer support two asynchronous DMA engines.
45 * cayman_dma_get_rptr - get the current read pointer
57 if (rdev->wb.enabled) { in cayman_dma_get_rptr()
58 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_dma_get_rptr()
60 if (ring->idx == R600_RING_TYPE_DMA_INDEX) in cayman_dma_get_rptr()
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/linux/arch/powerpc/platforms/powernv/
H A Dopal-hmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 "Hypervisor Resource error - core check stop" }, in print_core_checkstop_reason()
74 if (!hmi_evt->u.xstop_error.xstop_reason) { in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
82 if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) & in print_core_checkstop_reason()
84 printk("%s [Unit: %-3s] %s\n", level, in print_core_checkstop_reason()
94 { NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
96 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine", in print_nx_checkstop_reason()
97 "DMA invalid state error bit 15" }, in print_nx_checkstop_reason()
98 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine", in print_nx_checkstop_reason()
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/linux/drivers/dma/sh/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
40 Renesas R-Car Gen{2,3} and RZ/G{1,2} SoCs.
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H A Dusb-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB DMA Controller Driver
7 * based on rcar-dmac.c
13 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
30 * struct usb_dmac_sg - Descriptor for a hardware transfer
40 * struct usb_dmac_desc - USB DMA Transfer Descriptor
41 * @vd: base virtual channel DMA transaction descriptor
42 * @direction: direction of the DMA transfer
66 * struct usb_dmac_chan - USB DMA Controller Channel
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H A Drcar-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2/Gen3 DMA Controller Driver
5 * Copyright (C) 2014-2019 Renesas Electronics Inc.
11 #include <linux/dma-mapping.h>
28 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
43 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
56 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
57 * @async_tx: base DMA asynchronous transaction descriptor
58 * @direction: direction of the DMA transfer
67 * @hwdescs.dma: device address of the hardware descriptors memory
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/linux/drivers/ata/
H A Dpata_sl82c105.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
45 * sl82c105_pre_reset - probe begin
58 struct ata_port *ap = link->ap; in sl82c105_pre_reset()
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_pre_reset()
61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) in sl82c105_pre_reset()
62 return -ENOENT; in sl82c105_pre_reset()
68 * sl82c105_configure_piomode - set chip PIO timing
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_configure_piomode()
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/linux/Documentation/misc-devices/
H A Dmrvl_cn10k_dpi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
42 ioctl that sets DMA engine's fifo sizes & max outstanding load request
[all …]
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,hps-copy-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel HPS Copy Engine
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
14 The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
17 well as a keep-a-live indication to the host.
21 const: intel,hps-copy-engine
23 '#dma-cells':
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/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxlnx,axi-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP
10 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
11 - Abin Joseph <abin.joseph@amd.com>
14 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
19 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
24 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
[all …]
H A Dxlnx,zynqmp-dma-1.0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
12 control and rate control support for slave/peripheral dma access.
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
[all …]
H A Dxlnx,zynqmp-dpdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
16 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
19 - $ref: ../dma-controller.yaml#
22 "#dma-cells":
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/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
25 struct intel_engine_cs *engine; in __igt_reset_stolen() local
34 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
43 return -ENOMEM; in __igt_reset_stolen()
47 err = -ENOMEM; in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
58 for_each_engine(engine, gt, id) { in __igt_reset_stolen()
62 if (!(mask & engine->mask)) in __igt_reset_stolen()
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/linux/Documentation/hid/
H A Dintel-thc-hid.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - A natively half-duplex Quad I/O capable SPI master
11 - Low latency I2C interface to support HIDI2C compliant devices
12 - A HW sequencer with RW DMA capability to system memory
16 bandwidth DMA services to the touch driver and transfers the HID report to host system main memory.
18 Hardware sequencer within the THC is responsible for transferring (via DMA) data from touch devices
20 consumption (by host) in relation to data production (by touch device via DMA).
29 -------------------------------
31 Below diagram illustrates the high-level architecture of THC software/hardware stack, which is fully
36 ----------------------------------------------
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/linux/drivers/dma/amd/ptdma/
H A Dptdma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Passthru DMA device driver
4 * -- Based on the CCP driver
25 #include "../../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
125 * without performing DMA mapping
133 * - bit_mod, byte_swap, src, dst, src_len
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/linux/drivers/crypto/ti/
H A Ddthev2-common.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) Texas Instruments 2025 - https://www.ti.com
6 * Author: T Pratham <t-pratham@ti.com>
11 #include <crypto/engine.h>
15 #include "dthev2-common.h"
20 #include <linux/dma-mapping.h>
38 if (ctx->dev_data) in dthe_get_dev()
39 return ctx->dev_data; in dthe_get_dev()
44 list_move_tail(&dev_data->list, &dthe_dev_list.dev_list); in dthe_get_dev()
57 for (to_sg = dst, from_sg = src; buflen && from_sg; buflen -= sglen) { in dthe_copy_sg()
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/linux/drivers/crypto/intel/keembay/
H A Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
42 * @dma_err_mask: Error reported by OCS DMA interrupts.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
58 * @dma_addr: DMA address of the linked list head.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
[all …]
/linux/drivers/dma/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "MediaTek High-Speed DMA controller support"
9 Enable support for High-Speed DMA controller on MediaTek
13 memory-to-memory transfer to offload from CPU through ring-
17 tristate "MediaTek Command-Queue DMA controller support"
23 Enable support for Command-Queue DMA controller on MediaTek
27 memory-to-memory transfer to offload from CPU.
35 Support for the UART DMA engine found on MediaTek MTK SoCs.
36 When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
37 you can enable the config. The DMA engine can only be used
/linux/Documentation/gpu/nova/core/
H A Dfalcon.rst1 .. SPDX-License-Identifier: GPL-2.0
10 interactions of nova-core driver with the Falcon.
12 NVIDIA GPUs embed small RISC-like microcontrollers called Falcon cores, which
15 processor) and SEC2 (the security engine)) and also may integrate a RISC-V core.
16 This core is capable of running both RISC-V and Falcon code.
22 small DMA engine (via the FBIF - "Frame Buffer Interface") to load code from
23 system memory. The nova-core driver must reset and configure the Falcon, load
24 its firmware via DMA, and start its CPU.
28 Falcons can run in Non-secure (NS), Light Secure (LS), or Heavy Secure (HS)
32 --------------------------------------------------------
[all …]
/linux/include/linux/
H A Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
110 #define VDE_I_DMA0DDONE 0x00000010 /* DMA 0 descr done */
111 #define VDE_I_DMA0TDONE 0x00000020 /* DMA 0 transfer done */
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
115 #define VDE_I_HQV0 0x00000200 /* First HQV engine */
116 #define VDE_I_HQV1 0x00000400 /* Second HQV engine */
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