Home
last modified time | relevance | path

Searched +full:dma +full:- +full:engine (Results 1 – 25 of 702) sorted by relevance

12345678910>>...29

/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A DKbuild1 # SPDX-License-Identifier: MIT
2 nvkm-y += nvkm/engine/dma/base.o
3 nvkm-y += nvkm/engine/dma/nv04.o
4 nvkm-y += nvkm/engine/dma/nv50.o
5 nvkm-y += nvkm/engine/dma/gf100.o
6 nvkm-y += nvkm/engine/dma/gf119.o
7 nvkm-y += nvkm/engine/dma/gv100.o
9 nvkm-y += nvkm/engine/dma/user.o
10 nvkm-y += nvkm/engine/dma/usernv04.o
11 nvkm-y += nvkm/engine/dma/usernv50.o
[all …]
H A Dbase.c27 #include <engine/fifo.h>
36 struct nvkm_dma *dma = nvkm_dma(oclass->engine); in nvkm_dma_oclass_new() local
40 ret = dma->func->class_new(dma, oclass, data, size, &dmaobj); in nvkm_dma_oclass_new()
42 *pobject = &dmaobj->object; in nvkm_dma_oclass_new()
55 return nvkm_dma_oclass_new(oclass->engine->subdev.device, in nvkm_dma_oclass_fifo_new()
73 sclass->base = oclass[0]; in nvkm_dma_oclass_base_get()
74 sclass->engn = oclass; in nvkm_dma_oclass_base_get()
86 oclass->base = nvkm_dma_sclass[index]; in nvkm_dma_oclass_fifo_get()
93 nvkm_dma_dtor(struct nvkm_engine *engine) in nvkm_dma_dtor() argument
95 return nvkm_dma(engine); in nvkm_dma_dtor()
[all …]
/linux/drivers/crypto/marvell/cesa/
H A Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
58 spin_lock_bh(&engine->lock); in mv_cesa_rearm_engine()
[all …]
/linux/Documentation/driver-api/dmaengine/
H A Dclient.rst2 DMA Engine API Guide
7 .. note:: For DMA Engine usage in async_tx please see:
8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
12 DMA Engine. This is applicable only for slave DMA usage only.
14 DMA usage
17 The slave DMA usage consists of following steps:
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
[all …]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Ddma-engine.txt1 * DMA Engine.
3 The Octeon DMA Engine transfers between the Boot Bus and main memory.
4 The DMA Engine will be referred to by phandle by any device that is
8 - compatible: "cavium,octeon-5750-bootbus-dma"
12 - reg: The base address of the DMA Engine's register bank.
14 - interrupts: A single interrupt specifier.
17 dma0: dma-engine@1180000000100 {
18 compatible = "cavium,octeon-5750-bootbus-dma";
/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c31 * DMA
33 * DMA engine. The programming model is very similar
34 * to the 3D engine (ring buffer, IBs, etc.), but the
35 * DMA controller has it's own packet format that is
36 * different form the PM4 format used by the 3D engine.
43 * r600_dma_get_rptr - get the current read pointer
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
78 * r600_dma_set_wptr - commit the write pointer
[all …]
H A Devergreen_dma.c31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
37 * the fence seq number and DMA trap packet to generate
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit()
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
59 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
64 * Schedule an IB in the DMA ring (evergreen).
69 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_dma_ring_ib_execute()
[all …]
/linux/drivers/soc/sunxi/
H A Dsunxi_mbus.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/dma-map-ops.h>
13 * The display engine virtual devices are not strictly speaking
15 * memory allocations and DMA operations through that device, we
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
[all …]
/linux/drivers/dma/ti/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Texas Instruments DMA drivers
7 tristate "Texas Instruments CPPI 4.1 DMA support"
11 The Communications Port Programming Interface (CPPI) 4.1 DMA engine
22 Enable support for the TI EDMA (Enhanced DMA) controller. This DMA
23 engine is found on TI DaVinci, AM33xx, AM43xx, DRA7xx and Keystone 2
27 tristate "Texas Instruments sDMA (omap-dma) support"
34 Enable support for the TI sDMA (System DMA or DMA4) controller. This
35 DMA engine is found on OMAP and DRA7xx parts.
47 Enable support for the TI UDMA (Unified DMA) controller. This
[all …]
/linux/arch/powerpc/platforms/powernv/
H A Dopal-hmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 "Hypervisor Resource error - core check stop" }, in print_core_checkstop_reason()
74 if (!hmi_evt->u.xstop_error.xstop_reason) { in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
82 if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) & in print_core_checkstop_reason()
84 printk("%s [Unit: %-3s] %s\n", level, in print_core_checkstop_reason()
94 { NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
96 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine", in print_nx_checkstop_reason()
97 "DMA invalid state error bit 15" }, in print_nx_checkstop_reason()
98 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine", in print_nx_checkstop_reason()
[all …]
/linux/drivers/dma/sh/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # DMA engine configuration for sh
11 # DMA Engine Helpers
15 bool "Renesas SuperH DMA Engine support"
22 Enable support for the Renesas SuperH DMA controllers.
25 # DMA Controllers
32 Enable support for the Renesas SuperH DMA controllers.
35 tristate "Renesas R-Car Gen{2,3} and RZ/G{1,2} DMA Controller"
39 This driver supports the general purpose DMA controller found in the
40 Renesas R-Car Gen{2,3} and RZ/G{1,2} SoCs.
[all …]
H A Dusb-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas USB DMA Controller Driver
7 * based on rcar-dmac.c
13 #include <linux/dma-mapping.h>
27 #include "../virt-dma.h"
30 * struct usb_dmac_sg - Descriptor for a hardware transfer
40 * struct usb_dmac_desc - USB DMA Transfer Descriptor
41 * @vd: base virtual channel DMA transaction descriptor
42 * @direction: direction of the DMA transfer
66 * struct usb_dmac_chan - USB DMA Controller Channel
[all …]
H A Drcar-dmac.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car Gen2/Gen3 DMA Controller Driver
5 * Copyright (C) 2014-2019 Renesas Electronics Inc.
11 #include <linux/dma-mapping.h>
28 * struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
43 * struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
56 * struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
57 * @async_tx: base DMA asynchronous transaction descriptor
58 * @direction: direction of the DMA transfer
67 * @hwdescs.dma: device address of the hardware descriptors memory
[all …]
/linux/Documentation/devicetree/bindings/dma/xilinx/
H A Dxilinx_dma.txt1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
[all …]
/linux/drivers/ata/
H A Dpata_sl82c105.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
14 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
45 * sl82c105_pre_reset - probe begin
58 struct ata_port *ap = link->ap; in sl82c105_pre_reset()
59 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_pre_reset()
61 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no])) in sl82c105_pre_reset()
62 return -ENOENT; in sl82c105_pre_reset()
68 * sl82c105_configure_piomode - set chip PIO timing
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in sl82c105_configure_piomode()
[all …]
/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
[all …]
H A Dnvidia,tegra210-nvdec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvdec@[0-9a-f]*$"
24 - nvidia,tegra210-nvdec
25 - nvidia,tegra186-nvdec
26 - nvidia,tegra194-nvdec
[all …]
/linux/Documentation/misc-devices/
H A Dmrvl_cn10k_dpi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Marvell CN10K DMA packet interface (DPI) driver
10 DPI is a DMA packet interface hardware block in Marvell's CN10K silicon.
12 mailbox logic, and a set of DMA engines & DMA command queues.
15 requests from its VF functions and provisions DMA engine resources to
20 the DMA engines and VF device's DMA command queues. Also, driver creates
21 /dev/mrvl-cn10k-dpi node to set DMA engine and PEM (PCIe interface) port
26 DMA operations. Only VF devices are provisioned with DMA capabilities.
38 a pem port to which DMA engines are wired.
42 ioctl that sets DMA engine's fifo sizes & max outstanding load request
[all …]
/linux/Documentation/devicetree/bindings/soc/intel/
H A Dintel,hps-copy-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Intel HPS Copy Engine
11 - Matthew Gerlach <matthew.gerlach@linux.intel.com>
14 The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
17 well as a keep-a-live indication to the host.
21 const: intel,hps-copy-engine
23 '#dma-cells':
[all …]
/linux/drivers/crypto/ti/
H A Ddthev2-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) Texas Instruments 2025 - https://www.ti.com
6 * Author: T Pratham <t-pratham@ti.com>
15 #include <crypto/engine.h>
24 #include <linux/dma-mapping.h>
32 * This is currently the keysize of XTS-AES-256 which is 512 bits (64 bytes)
45 * struct dthe_data - DTHE_V2 driver instance data
49 * @engine: Crypto engine instance
50 * @dma_aes_rx: AES Rx DMA Channel
51 * @dma_aes_tx: AES Tx DMA Channel
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_reset.c1 // SPDX-License-Identifier: MIT
22 struct i915_ggtt *ggtt = gt->ggtt; in __igt_reset_stolen()
23 const struct resource *dsm = &gt->i915->dsm.stolen; in __igt_reset_stolen()
25 struct intel_engine_cs *engine; in __igt_reset_stolen() local
34 if (!drm_mm_node_allocated(&ggtt->error_capture)) in __igt_reset_stolen()
43 return -ENOMEM; in __igt_reset_stolen()
47 err = -ENOMEM; in __igt_reset_stolen()
52 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in __igt_reset_stolen()
58 for_each_engine(engine, gt, id) { in __igt_reset_stolen()
62 if (!(mask & engine->mask)) in __igt_reset_stolen()
[all …]
/linux/drivers/dma/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "MediaTek High-Speed DMA controller support"
9 Enable support for High-Speed DMA controller on MediaTek
13 memory-to-memory transfer to offload from CPU through ring-
17 tristate "MediaTek Command-Queue DMA controller support"
23 Enable support for Command-Queue DMA controller on MediaTek
27 memory-to-memory transfer to offload from CPU.
35 Support for the UART DMA engine found on MediaTek MTK SoCs.
36 When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
37 you can enable the config. The DMA engine can only be used
/linux/drivers/crypto/intel/keembay/
H A Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
42 * @dma_err_mask: Error reported by OCS DMA interrupts.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
58 * @dma_addr: DMA address of the linked list head.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
[all …]
/linux/drivers/dma/amd/ptdma/
H A Dptdma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Passthru DMA device driver
4 * -- Based on the CCP driver
25 #include "../../virt-dma.h"
94 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \
96 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
109 #define LSB_COUNT (LSB_END - LSB_START + 1)
124 * struct pt_passthru_engine - pass-through operation
125 * without performing DMA mapping
133 * - bit_mod, byte_swap, src, dst, src_len
[all …]

12345678910>>...29