Lines Matching +full:dma +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
19 if (!sgiter->sg)
22 sgiter->op_offset += len;
23 sgiter->offset += len;
24 if (sgiter->offset == sg_dma_len(sgiter->sg)) {
25 if (sg_is_last(sgiter->sg))
27 sgiter->offset = 0;
28 sgiter->sg = sg_next(sgiter->sg);
31 if (sgiter->op_offset == iter->op_len)
39 struct mv_cesa_engine *engine = dreq->engine;
41 spin_lock_bh(&engine->lock);
42 if (engine->chain_sw.first == dreq->chain.first) {
43 engine->chain_sw.first = NULL;
44 engine->chain_sw.last = NULL;
46 engine->chain_hw.first = dreq->chain.first;
47 engine->chain_hw.last = dreq->chain.last;
48 spin_unlock_bh(&engine->lock);
50 writel_relaxed(0, engine->regs + CESA_SA_CFG);
52 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
55 engine->regs + CESA_TDMA_CONTROL);
59 engine->regs + CESA_SA_CFG);
60 writel_relaxed(dreq->chain.first->cur_dma,
61 engine->regs + CESA_TDMA_NEXT_ADDR);
62 WARN_ON(readl(engine->regs + CESA_SA_CMD) &
64 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
71 for (tdma = dreq->chain.first; tdma;) {
73 u32 type = tdma->flags & CESA_TDMA_TYPE_MSK;
76 dma_pool_free(cesa_dev->dma->op_pool, tdma->op,
77 le32_to_cpu(tdma->src));
79 tdma = tdma->next;
80 dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma,
81 old_tdma->cur_dma);
84 dreq->chain.first = NULL;
85 dreq->chain.last = NULL;
89 struct mv_cesa_engine *engine)
93 for (tdma = dreq->chain.first; tdma; tdma = tdma->next) {
94 if (tdma->flags & CESA_TDMA_DST_IN_SRAM)
95 tdma->dst = cpu_to_le32(tdma->dst_dma + engine->sram_dma);
97 if (tdma->flags & CESA_TDMA_SRC_IN_SRAM)
98 tdma->src = cpu_to_le32(tdma->src_dma + engine->sram_dma);
100 if ((tdma->flags & CESA_TDMA_TYPE_MSK) == CESA_TDMA_OP)
101 mv_cesa_adjust_op(engine, tdma->op);
105 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
108 struct mv_cesa_tdma_desc *last = engine->chain_sw.last;
111 * Break the DMA chain if the request being queued needs the IV
114 if (!last || dreq->chain.first->flags & CESA_TDMA_SET_STATE)
115 engine->chain_sw.first = dreq->chain.first;
117 last->next = dreq->chain.first;
118 last->next_dma = cpu_to_le32(dreq->chain.first->cur_dma);
120 last = dreq->chain.last;
121 engine->chain_sw.last = last;
123 * Break the DMA chain if the CESA_TDMA_BREAK_CHAIN is set on
126 if (last->flags & CESA_TDMA_BREAK_CHAIN) {
127 engine->chain_sw.first = NULL;
128 engine->chain_sw.last = NULL;
132 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
139 tdma_cur = readl(engine->regs + CESA_TDMA_CUR);
141 for (tdma = engine->chain_hw.first; tdma; tdma = next) {
142 spin_lock_bh(&engine->lock);
143 next = tdma->next;
144 spin_unlock_bh(&engine->lock);
146 if (tdma->flags & CESA_TDMA_END_OF_REQ) {
151 spin_lock_bh(&engine->lock);
154 * request in engine->req.
157 req = engine->req;
159 req = mv_cesa_dequeue_req_locked(engine,
162 /* Re-chaining to the next request */
163 engine->chain_hw.first = tdma->next;
164 tdma->next = NULL;
167 if (engine->chain_hw.first == NULL)
168 engine->chain_hw.last = NULL;
169 spin_unlock_bh(&engine->lock);
171 ctx = crypto_tfm_ctx(req->tfm);
172 current_status = (tdma->cur_dma == tdma_cur) ?
174 res = ctx->ops->process(req, current_status);
175 ctx->ops->complete(req);
178 mv_cesa_engine_enqueue_complete_request(engine,
182 crypto_request_complete(backlog, -EINPROGRESS);
185 if (res || tdma->cur_dma == tdma_cur)
190 * Save the last request in error to engine->req, so that the core
194 spin_lock_bh(&engine->lock);
195 engine->req = req;
196 spin_unlock_bh(&engine->lock);
208 new_tdma = dma_pool_zalloc(cesa_dev->dma->tdma_desc_pool, flags,
211 return ERR_PTR(-ENOMEM);
213 new_tdma->cur_dma = dma_handle;
214 if (chain->last) {
215 chain->last->next_dma = cpu_to_le32(dma_handle);
216 chain->last->next = new_tdma;
218 chain->first = new_tdma;
221 chain->last = new_tdma;
235 /* We re-use an existing op_desc object to retrieve the context
240 for (op_desc = chain->first; op_desc; op_desc = op_desc->next) {
241 u32 type = op_desc->flags & CESA_TDMA_TYPE_MSK;
248 return -EIO;
250 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
251 tdma->src_dma = src;
252 tdma->dst_dma = op_desc->src_dma;
253 tdma->op = op_desc->op;
256 tdma->flags = flags | CESA_TDMA_RESULT;
274 op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle);
276 return ERR_PTR(-ENOMEM);
280 size = skip_ctx ? sizeof(op->desc) : sizeof(*op);
282 tdma = chain->last;
283 tdma->op = op;
284 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
285 tdma->src = cpu_to_le32(dma_handle);
286 tdma->dst_dma = CESA_SA_CFG_SRAM_OFFSET;
287 tdma->flags = CESA_TDMA_DST_IN_SRAM | CESA_TDMA_OP;
302 tdma->byte_cnt = cpu_to_le32(size | BIT(31));
303 tdma->src_dma = src;
304 tdma->dst_dma = dst;
307 tdma->flags = flags | CESA_TDMA_DATA;
328 tdma->byte_cnt = cpu_to_le32(BIT(31));
338 u32 flags = sgiter->dir == DMA_TO_DEVICE ?
347 if (sgiter->dir == DMA_TO_DEVICE) {
348 dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
349 src = sg_dma_address(sgiter->sg) + sgiter->offset;
351 dst = sg_dma_address(sgiter->sg) + sgiter->offset;
352 src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset;
365 size_t mv_cesa_sg_copy(struct mv_cesa_engine *engine,
387 len = min(miter.length, buflen - offset);
390 if (engine->pool)
391 memcpy(engine->sram_pool + sram_off + offset,
394 memcpy_toio(engine->sram + sram_off + offset,
397 if (engine->pool)
399 engine->sram_pool + sram_off + offset,
403 engine->sram + sram_off + offset,