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/linux/Documentation/devicetree/bindings/dma/
H A Dsprd,sc9860-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
16 - Orson Zhai <orsonzhai@gmail.com>
17 - Baolin Wang <baolin.wang7@gmail.com>
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H A Dmpc512x-dma.txt1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
8 the dma/dma.txt file for a more detailed description of binding.
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
14 is described in interrupt-controller/interrupts.txt file.
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
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H A Dowl-dma.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
15 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 - $ref: dma-controller.yaml#
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H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
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H A Dapple,admac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/apple,admac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Audio DMA Controller (ADMAC)
10 Apple's Audio DMA Controller (ADMAC) is used to fetch and store audio samples
13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
18 - Martin Povišer <povik+lin@cutebit.org>
21 - $ref: dma-controller.yaml#
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H A Dti-dma-crossbar.txt1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
5 "ti,am335x-edma-crossbar" for AM335x and AM437x
6 - reg: Memory map for accessing module
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
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H A Dmediatek,uart-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek UART APDMA controller
10 - Long Cheng <long.cheng@mediatek.com>
13 The MediaTek UART APDMA controller provides DMA capabilities
17 - $ref: dma-controller.yaml#
22 - items:
23 - enum:
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H A Datmel-xdma.txt
H A Dingenic,dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dma-controller.yaml#
18 - enum:
19 - ingenic,jz4740-dma
20 - ingenic,jz4725b-dma
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H A Dcirrus,ep9301-dma-m2m.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2m
20 - items:
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H A Dfsl,mxs-dma.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
10 - Marek Vasut <marex@denx.de>
13 - $ref: dma-controller.yaml#
14 - if:
18 const: fsl,imx8qxp-dma-apbh
21 - power-domains
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddma.txt1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
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/linux/drivers/dma/
H A Dof-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree helpers for DMA request / controller
7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
24 * of_dma_find_controller - Get a DMA controller in DT DMA helpers list
25 * @dma_spec: pointer to DMA specifier as found in the device tree
27 * Finds a DMA controller with matching device node and number for dma cells
28 * in a list of registered DMA controllers. If a match is found a valid pointer
29 * to the DMA data stored is returned. A NULL pointer is returned if no match is
37 if (ofdma->of_node == dma_spec->np) in of_dma_find_controller()
40 pr_debug("%s: can't find DMA controller %pOF\n", __func__, in of_dma_find_controller()
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/linux/Documentation/core-api/
H A Ddma-isa-lpc.rst2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
8 controller. Even though ISA is more or less dead today the LPC bus
9 uses the same DMA system so it will be around for quite some time.
12 ------------------------
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
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/linux/Documentation/devicetree/bindings/dma/stm32/
H A Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA Controller
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
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H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 MDMA Controller
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
12 DMA clients connected to the STM32 MDMA controller must use the format
13 described in the dma.txt file, using a five-cell specifier for each channel:
14 a phandle to the MDMA controller plus the following five integer cells:
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/linux/drivers/dma/qcom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 Enable support for the Qualcomm Application Data Mover (ADM) DMA
9 controller, as present on MSM8x60, APQ8064, and IPQ8064 devices.
10 This controller provides DMA capabilities for both general purpose
11 and on-chip peripheral devices.
14 tristate "QCOM BAM DMA support"
19 Enable support for the QCOM BAM DMA controller. This controller
20 provides DMA capabilities for a variety of on-chip devices.
23 tristate "Qualcomm Technologies GPI DMA support"
28 Enable support for the QCOM GPI DMA controller. This controller
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/linux/drivers/usb/musb/
H A Dmusb_dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MUSB OTG driver DMA controller abstraction
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
16 * DMA Controller Abstraction
18 * DMA Controllers are abstracted to allow use of a variety of different
19 * implementations of DMA, as allowed by the Inventra USB cores. On the
20 * host side, usbcore sets up the DMA mappings and flushes caches; on the
21 * peripheral side, the gadget controller driver does. Responsibilities
22 * of a DMA controller driver include:
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H A Dtusb6010_omap.c1 // SPDX-License-Identifier: GPL-2.0
3 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
13 #include <linux/dma-mapping.h>
20 #define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
51 struct dma_controller controller; member
63 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); in tusb_omap_use_shared_dmareq()
66 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", in tusb_omap_use_shared_dmareq()
67 chdat->epnum, reg & 0xf); in tusb_omap_use_shared_dmareq()
68 return -EAGAIN; in tusb_omap_use_shared_dmareq()
71 if (chdat->tx) in tusb_omap_use_shared_dmareq()
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/linux/include/linux/dma/
H A Dsprd-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
29 * support the 2-stage transfer.
35 * Now the DMA controller can supports 2 groups 2-stage transfer.
46 * enum sprd_dma_trg_mode: define the DMA channel trigger mode for 2-stage
56 * automatically once the source channel's link-list request is done.
67 * enum sprd_dma_req_mode: define the DMA request mode
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/linux/drivers/dma/stm32/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # STM32 DMA controllers drivers
8 bool "STMicroelectronics STM32 DMA support"
12 Enable support for the on-chip DMA controller on STMicroelectronics
14 If you have a board based on STM32 SoC with such DMA controller
15 and want to use DMA say Y here.
18 bool "STMicroelectronics STM32 DMA multiplexer support"
21 Enable support for the on-chip DMA multiplexer on STMicroelectronics
23 If you have a board based on STM32 SoC with such DMA multiplexer
27 bool "STMicroelectronics STM32 master DMA support"
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/linux/sound/soc/fsl/
H A Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
3 // Freescale DMA ALSA SoC PCM driver
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // This driver implements ASoC support for the Elo DMA controller, which is
10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
11 // the PCM driver is what handles the DMA buffer.
16 #include <linux/dma-mapping.h>
39 * The formats that the DMA controller supports, which is anything
67 * The number of DMA links to use. Two is the bare minimum, but if you
72 /** fsl_dma_private: p-substream DMA data
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/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
[all …]
/linux/drivers/dma/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "MediaTek High-Speed DMA controller support"
9 Enable support for High-Speed DMA controller on MediaTek
12 This controller provides the channels which is dedicated to
13 memory-to-memory transfer to offload from CPU through ring-
17 tristate "MediaTek Command-Queue DMA controller support"
23 Enable support for Command-Queue DMA controller on MediaTek
26 This controller provides the channels which is dedicated to
27 memory-to-memory transfer to offload from CPU.
35 Support for the UART DMA engine found on MediaTek MTK SoCs.
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/linux/Documentation/driver-api/dmaengine/
H A Dprovider.rst2 DMAengine controller documentation
8 Most of the Slave DMA controllers have the same general principles of
11 They have a given number of channels to use for the DMA transfers, and
20 DMA-eligible devices to the controller itself. Whenever the device
21 will want to start a transfer, it will assert a DMA request (DRQ) by
24 A very simple DMA controller would only take into account a single
35 is why most if not all of the DMA controllers can adjust this, using a
38 Moreover, some DMA controllers, whenever the RAM is used as a source
43 reads/writes it's allowed to do without the controller splitting the
44 transfer into smaller sub-transfers.
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