xref: /linux/Documentation/devicetree/bindings/dma/nvidia,tegra20-apbdma.yaml (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1*d2c9d354SCharan Pedumuru# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*d2c9d354SCharan Pedumuru%YAML 1.2
3*d2c9d354SCharan Pedumuru---
4*d2c9d354SCharan Pedumuru$id: http://devicetree.org/schemas/dma/nvidia,tegra20-apbdma.yaml#
5*d2c9d354SCharan Pedumuru$schema: http://devicetree.org/meta-schemas/core.yaml#
6*d2c9d354SCharan Pedumuru
7*d2c9d354SCharan Pedumurutitle: NVIDIA Tegra APB DMA Controller
8*d2c9d354SCharan Pedumuru
9*d2c9d354SCharan Pedumurudescription:
10*d2c9d354SCharan Pedumuru  The NVIDIA Tegra APB DMA controller is a hardware component that
11*d2c9d354SCharan Pedumuru  enables direct memory access (DMA) on Tegra systems. It facilitates
12*d2c9d354SCharan Pedumuru  data transfer between I/O devices and main memory without constant
13*d2c9d354SCharan Pedumuru  CPU intervention.
14*d2c9d354SCharan Pedumuru
15*d2c9d354SCharan Pedumurumaintainers:
16*d2c9d354SCharan Pedumuru  - Jonathan Hunter <jonathanh@nvidia.com>
17*d2c9d354SCharan Pedumuru
18*d2c9d354SCharan Pedumuruproperties:
19*d2c9d354SCharan Pedumuru  compatible:
20*d2c9d354SCharan Pedumuru    oneOf:
21*d2c9d354SCharan Pedumuru      - const: nvidia,tegra20-apbdma
22*d2c9d354SCharan Pedumuru      - items:
23*d2c9d354SCharan Pedumuru          - const: nvidia,tegra30-apbdma
24*d2c9d354SCharan Pedumuru          - const: nvidia,tegra20-apbdma
25*d2c9d354SCharan Pedumuru
26*d2c9d354SCharan Pedumuru  reg:
27*d2c9d354SCharan Pedumuru    maxItems: 1
28*d2c9d354SCharan Pedumuru
29*d2c9d354SCharan Pedumuru  "#dma-cells":
30*d2c9d354SCharan Pedumuru    const: 1
31*d2c9d354SCharan Pedumuru
32*d2c9d354SCharan Pedumuru  clocks:
33*d2c9d354SCharan Pedumuru    maxItems: 1
34*d2c9d354SCharan Pedumuru
35*d2c9d354SCharan Pedumuru  interrupts:
36*d2c9d354SCharan Pedumuru    description:
37*d2c9d354SCharan Pedumuru      Should contain all of the per-channel DMA interrupts in
38*d2c9d354SCharan Pedumuru      ascending order with respect to the DMA channel index.
39*d2c9d354SCharan Pedumuru    minItems: 1
40*d2c9d354SCharan Pedumuru    maxItems: 32
41*d2c9d354SCharan Pedumuru
42*d2c9d354SCharan Pedumuru  resets:
43*d2c9d354SCharan Pedumuru    maxItems: 1
44*d2c9d354SCharan Pedumuru
45*d2c9d354SCharan Pedumuru  reset-names:
46*d2c9d354SCharan Pedumuru    const: dma
47*d2c9d354SCharan Pedumuru
48*d2c9d354SCharan Pedumururequired:
49*d2c9d354SCharan Pedumuru  - compatible
50*d2c9d354SCharan Pedumuru  - reg
51*d2c9d354SCharan Pedumuru  - "#dma-cells"
52*d2c9d354SCharan Pedumuru  - clocks
53*d2c9d354SCharan Pedumuru  - interrupts
54*d2c9d354SCharan Pedumuru  - resets
55*d2c9d354SCharan Pedumuru  - reset-names
56*d2c9d354SCharan Pedumuru
57*d2c9d354SCharan PedumuruallOf:
58*d2c9d354SCharan Pedumuru  - $ref: dma-controller.yaml#
59*d2c9d354SCharan Pedumuru
60*d2c9d354SCharan PedumuruunevaluatedProperties: false
61*d2c9d354SCharan Pedumuru
62*d2c9d354SCharan Pedumuruexamples:
63*d2c9d354SCharan Pedumuru  - |
64*d2c9d354SCharan Pedumuru    #include <dt-bindings/interrupt-controller/arm-gic.h>
65*d2c9d354SCharan Pedumuru    #include <dt-bindings/reset/tegra186-reset.h>
66*d2c9d354SCharan Pedumuru    dma-controller@6000a000 {
67*d2c9d354SCharan Pedumuru        compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
68*d2c9d354SCharan Pedumuru        reg = <0x6000a000 0x1200>;
69*d2c9d354SCharan Pedumuru        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
70*d2c9d354SCharan Pedumuru                     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
71*d2c9d354SCharan Pedumuru                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
72*d2c9d354SCharan Pedumuru                     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
73*d2c9d354SCharan Pedumuru                     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
74*d2c9d354SCharan Pedumuru                     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
75*d2c9d354SCharan Pedumuru                     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
76*d2c9d354SCharan Pedumuru                     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
77*d2c9d354SCharan Pedumuru                     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
78*d2c9d354SCharan Pedumuru                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
79*d2c9d354SCharan Pedumuru                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
80*d2c9d354SCharan Pedumuru                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
81*d2c9d354SCharan Pedumuru                     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
82*d2c9d354SCharan Pedumuru                     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
83*d2c9d354SCharan Pedumuru                     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
84*d2c9d354SCharan Pedumuru                     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
85*d2c9d354SCharan Pedumuru        clocks = <&tegra_car 34>;
86*d2c9d354SCharan Pedumuru        resets = <&tegra_car 34>;
87*d2c9d354SCharan Pedumuru        reset-names = "dma";
88*d2c9d354SCharan Pedumuru        #dma-cells = <1>;
89*d2c9d354SCharan Pedumuru    };
90*d2c9d354SCharan Pedumuru...
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