Lines Matching +full:dma +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
11 memory-mapped registers. channels are split into two groups, called
12 DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
26 - fsl,imx93-edma3
27 - fsl,imx93-edma4
28 - fsl,imx95-edma5
29 - nxp,s32g2-edma
30 - items:
31 - enum:
32 - fsl,imx94-edma3
33 - const: fsl,imx93-edma3
34 - items:
35 - enum:
36 - fsl,imx94-edma5
37 - const: fsl,imx95-edma5
38 - items:
39 - const: fsl,ls1028a-edma
40 - const: fsl,vf610-edma
41 - items:
42 - const: nxp,s32g3-edma
43 - const: nxp,s32g2-edma
53 interrupt-names:
57 "#dma-cells":
59 Specifies the number of cells needed to encode an DMA channel.
62 cell 0: index of dma channel mux instance.
63 cell 1: peripheral dma request id.
66 cell 0: peripheral dma request id.
67 cell 1: dma channel priority.
68 cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
70 - 2
71 - 3
73 dma-channels:
81 clock-names:
85 power-domains:
88 in ascending order according to their associated DMA channels.
92 big-endian:
99 - "#dma-cells"
100 - compatible
101 - reg
102 - interrupts
103 - dma-channels
106 - $ref: dma-controller.yaml#
107 - if:
112 - fsl,imx8qm-edma
113 - fsl,imx93-edma3
114 - fsl,imx93-edma4
115 - fsl,imx95-edma5
118 "#dma-cells":
122 # defined for the DMA channels.
123 interrupt-names: false
124 clock-names:
126 - const: dma
130 - if:
134 const: fsl,vf610-edma
140 clock-names:
142 - const: dmamux0
143 - const: dmamux1
147 interrupt-names:
149 - const: edma-tx
150 - const: edma-err
154 "#dma-cells":
156 dma-channels:
159 - if:
163 const: fsl,imx7ulp-edma
169 clock-names:
171 - const: dma
172 - const: dmamux0
179 "#dma-cells":
181 dma-channels:
184 - if:
188 const: fsl,imx8ulp-edma
193 clock-names:
197 - const: dma
198 - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
200 interrupt-names: false
203 "#dma-cells":
206 - if:
211 - fsl,vf610-edma
212 - fsl,imx7ulp-edma
213 - fsl,imx93-edma3
214 - fsl,imx93-edma4
215 - fsl,imx95-edma5
216 - fsl,imx8ulp-edma
217 - fsl,ls1028a-edma
220 - clocks
222 - if:
227 - fsl,imx8qm-adma
228 - fsl,imx8qm-edma
231 - power-domains
234 power-domains: false
236 - if:
240 const: nxp,s32g2-edma
246 clock-names:
248 - const: dmamux0
249 - const: dmamux1
253 interrupt-names:
255 - const: tx-0-15
256 - const: tx-16-31
257 - const: err
261 "#dma-cells":
263 dma-channels:
269 - |
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
271 #include <dt-bindings/clock/vf610-clock.h>
273 edma0: dma-controller@40018000 {
274 #dma-cells = <2>;
275 compatible = "fsl,vf610-edma";
281 interrupt-names = "edma-tx", "edma-err";
282 dma-channels = <32>;
283 clock-names = "dmamux0", "dmamux1";
287 - |
288 #include <dt-bindings/interrupt-controller/arm-gic.h>
289 #include <dt-bindings/clock/imx7ulp-clock.h>
291 edma1: dma-controller@40080000 {
292 #dma-cells = <2>;
293 compatible = "fsl,imx7ulp-edma";
296 dma-channels = <32>;
313 /* last is eDMA2-ERR interrupt */
315 clock-names = "dma", "dmamux0";
319 - |
320 #include <dt-bindings/interrupt-controller/arm-gic.h>
321 #include <dt-bindings/firmware/imx/rsrc.h>
323 dma-controller@5a9f0000 {
324 compatible = "fsl,imx8qm-edma";
326 #dma-cells = <3>;
327 dma-channels = <8>;
336 power-domains = <&pd IMX_SC_R_DMA_3_CH0>,