| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
12 - ranges : describes the mapping between the address space of the
13 DMA channels and the address space of the DMA controller
14 - cell-index : controller index. 0 for controller @ 0x8100
15 - interrupts : interrupt specifier for DMA IRQ
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | fsl,elo-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Elo DMA Controller
10 - J. Neuschäfer <j.ne@posteo.net>
13 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
19 - enum:
20 - fsl,mpc8313-dma
21 - fsl,mpc8315-dma
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| H A D | fsl,eloplus-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale EloPlus DMA Controller
10 - J. Neuschäfer <j.ne@posteo.net>
13 This is a 4-channel DMA controller with extended addresses and chaining,
20 - items:
21 - enum:
22 - fsl,mpc8540-dma
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| H A D | fsl,elo3-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Elo3 DMA Controller
10 - J. Neuschäfer <j.ne@posteo.net>
13 DMA controller which has same function as EloPlus except that Elo3 has 8
19 const: fsl,elo3-dma
23 - description:
24 DMA General Status Registers starting from DGSR0, for channel 1~4
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| H A D | cirrus,ep9301-dma-m2p.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC M2P DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
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| H A D | ste-dma40.txt | 1 * DMA40 DMA Controller
4 - compatible: "stericsson,dma40"
5 - reg: Address range of the DMAC registers
6 - reg-names: Names of the above areas to use during resource look-up
7 - interrupt: Should contain the DMAC interrupt number
8 - #dma-cells: must be <3>
9 - memcpy-channels: Channels to be used for memcpy
12 - dma-channels: Number of channels supported by hardware - if not present
14 - disabled-channels: Channels which can not be used
18 dma: dma-controller@801c0000 {
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| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stericsson,dma40.yaml#
5 $schema: http://devicetree.org/meta-schema
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| H A D | mmp-dma.txt | 1 * MARVELL MMP DMA controller
3 Marvell Peripheral DMA Controller
7 - compatible: Should be "marvell,pdma-1.0"
8 - reg: Should contain DMA registers location and length.
9 - interrupts: Either contain all of the per-channel DMA interrupts
13 - dma-channels: Number of DMA channels supported by the controller (defaults
15 - #dma-channels: deprecated
16 - dma-requests: Number of DMA requestor lines supported by the controller
18 - #dma-requests: deprecated
20 "marvell,pdma-1.0"
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| H A D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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| H A D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| H A D | ingenic,dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/ingeni
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| H A D | cirrus,ep9301-dma-m2m.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2m.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2m
20 - items:
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| H A D | qcom,gpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
10 - Vinod Koul <vkoul@kernel.org>
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
22 - enum:
23 - qcom,sdm845-gpi-dma
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| /freebsd/sys/dev/sound/macio/ |
| H A D | aoa.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
59 dbdma_channel_t *channel; /* DBDMA channel */ member
61 struct pcm_channel *pcm; /* PCM channel */
71 aoa_dma_set_program(struct aoa_dma *dma) in aoa_dma_set_program() argument
76 addr = (u_int32_t)dma->buf->buf_addr; in aoa_dma_set_program()
77 KASSERT(dma->bufsz == dma->buf->bufsize, ("bad size")); in aoa_dma_set_program()
79 dma->slots = dma->bufsz / dma->blksz; in aoa_dma_set_program()
81 for (i = 0; i < dma->slots; ++i) { in aoa_dma_set_program()
82 dbdma_insert_command(dma->channel, in aoa_dma_set_program()
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| /freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7 target devices. It can be configured to have one channel or two channels.
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dm
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | elo3-dma-0.dtsi | 2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x100000 ]
35 dma0: dma@100300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
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| H A D | elo3-dma-1.dtsi | 2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
35 dma1: dma@101300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
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| H A D | elo3-dma-2.dtsi | 2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x102300 ]
35 dma2: dma@102300 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "fsl,elo3-dma";
42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
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| H A D | mpc8641si-post.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
22 mcm-law@0 {
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | fsl,ssi.txt | 4 be programmed in AC97, I2S, left-justified, or right-justified modes.
7 - compatible: Compatible list, should contain one of the following
9 fsl,mpc8610-ssi
10 fsl,imx51-ssi
11 fsl,imx35-ssi
12 fsl,imx21-ssi
13 - cell-index: The SSI, <0> = SSI1, <1> = SSI2, and so on.
14 - reg: Offset and length of the register set for the device.
15 - interrupts: <a b> where a is the interrupt number and b is a
21 - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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| H A D | nvidia,tegra210-admaif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
14 ADMAIF Rx channel.
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
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| H A D | fsl,ssi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
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| /freebsd/sys/arm/ti/ |
| H A D | ti_sdma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 * Kernel functions for using the DMA controller
59 * DMA TRANSFERS:
60 * A DMA transfer block consists of a number of frames (FN). Each frame
73 * Data structure per DMA channel.
79 * The configuration registers for the given channel, these are modified
90 /* Callback function used when an interrupt is tripped on the given channel */
99 * DMA driver context, allocated and stored globally, this driver is not
109 * I guess in theory we should have a mutex per DMA channel for register
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | mpc8610_hpcd.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <32768>; // L1
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| /freebsd/sys/dev/xdma/controller/ |
| H A D | pl330.h | 1 /*-
2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
35 #define DSR 0x000 /* DMA Manager Status */
36 #define DPC 0x004 /* DMA Program Counter */
38 #define INT_EVENT_RIS 0x024 /* Event-Interrupt Raw Status */
41 #define FSRD 0x030 /* Fault Status DMA Manager */
42 #define FSRC 0x034 /* Fault Status DMA Channel */
43 #define FTRD 0x038 /* Fault Type DMA Manager */
44 #define FTR(n) (0x040 + 0x04 * (n)) /* Fault type for DMA channel n */
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