divider\-width (full) in projects: linux

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Searched +full:divider +full:- +full:width (Results 1 – 25 of 301) sorted by relevance

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/linux/drivers/clk/
H A D	clk-divider.c	1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 7 * Adjustable divider clock implementation 10 #include <linux/clk-provider.h> 20 * DOC: basic adjustable divider clock that cannot gate 23 * prepare - clk_prepare only ensures that parents are prepared 24 * enable - clk_enable only ensures that parents are enabled 25 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) 26 * parent - fixed parent. No clk_set_parent support 29 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument [all …]
H A D	clk-milbeaut.c	`1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) 20 #define M10V_PLL1DIV2 "pll1-2" 22 #define M10V_PLL2DIV2 "pll2-2" 24 #define M10V_PLL6DIV2 "pll6-2" 25 #define M10V_PLL6DIV3 "pll6-3" 27 #define M10V_PLL7DIV2 "pll7-2" 28 #define M10V_PLL7DIV5 "pll7-5" 31 #define M10V_PLL10DIV2 "pll10-2" [all …]`
H A D	clk-axm5516.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/clk/clk-axm5516.c 6 * the Axxia device: PLL clock, a clock divider and a clock mux. 16 #include <linux/clk-provider.h> 18 #include <dt-bindings/clock/lsi,axm5516-clks.h> 22 * struct axxia_clk - Common struct to all Axxia clocks. 33 * struct axxia_pllclk - Axxia PLL generated clock. 44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the 55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc() 69 * struct axxia_divclk - Axxia clock divider [all …]
/linux/drivers/clk/qcom/
H A D	clk-regmap-divider.c	1 // SPDX-License-Identifier: GPL-2.0-only 11 #include "clk-regmap-divider.h" 21 struct clk_regmap_div divider = to_clk_regmap_div(hw); in div_round_ro_rate() local 22 struct clk_regmap clkr = &divider->clkr; in div_round_ro_rate() 25 regmap_read(clkr->regmap, divider->reg, &val); in div_round_ro_rate() 26 val >>= divider->shift; in div_round_ro_rate() 27 val &= BIT(divider->width) - 1; in div_round_ro_rate() 29 return divider_ro_round_rate(hw, rate, prate, NULL, divider->width, in div_round_ro_rate() 36 struct clk_regmap_div *divider = to_clk_regmap_div(hw); in div_round_rate() local 38 return divider_round_rate(hw, rate, prate, NULL, divider->width, in div_round_rate() [all …]
/linux/drivers/clk/rockchip/
H A D	clk-half-divider.c	1 // SPDX-License-Identifier: GPL-2.0 6 #include <linux/clk-provider.h> 11 #define div_mask(width) ((1 << (width)) - 1) argument 17 return abs(rate - now) < abs(rate - best); in _is_best_half_div() 25 struct clk_divider divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local 28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate() 29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate() 36 unsigned long best_parent_rate, u8 width, in clk_half_divider_bestdiv() argument 46 maxdiv = div_mask(width); in clk_half_divider_bestdiv() 54 bestdiv = (bestdiv - 3) / 2; in clk_half_divider_bestdiv() [all …]
/linux/drivers/clk/tegra/
H A D	clk-divider.c	1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/clk-provider.h> 14 #define pll_out_override(p) (BIT((p->shift - 6))) 15 #define div_mask(d) ((1 << (d->width)) - 1) 16 #define get_mul(d) (1 << d->frac_width) 21 static int get_div(struct tegra_clk_frac_div divider, unsigned long rate, in get_div() argument 26 div = div_frac_get(rate, parent_rate, divider->width, in get_div() 27 divider->frac_width, divider->flags); in get_div() 38 struct tegra_clk_frac_div divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local 43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate() [all …]
/linux/drivers/clk/hisilicon/
H A D	clkdivider-hi6220.c	`1 // SPDX-License-Identifier: GPL-2.0-only 3 * Hisilicon hi6220 SoC divider clock driver 11 #include <linux/clk-provider.h> 19 #define div_mask(width) ((1 << (width)) - 1) argument 22 * struct hi6220_clk_divider - divider clock for hi6220 24 * @hw: handle between common and hardware-specific interfaces 25 * @reg: register containing divider 26 * @shift: shift to the divider bit field 27 * @width: width of the divider bit field 28 * @mask: mask for setting divider rate [all …]`
/linux/drivers/clk/imx/
H A D	clk-divider-gate.c	1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <linux/clk-provider.h> 15 struct clk_divider divider; member 23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate() 32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro() 33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro() 37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro() 38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro() 49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate() 52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate() [all …]
/linux/drivers/clk/stm32/
H A D	clk-stm32-core.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 17 #include "clk-stm32-core.h" 18 #include "reset-stm32.h" 26 const struct stm32_rcc_match_data data = match->data; in stm32_rcc_clock_init() 27 struct clk_hw_onecell_data clk_data = data->hw_clks; in stm32_rcc_clock_init() 31 max_binding = data->maxbinding; in stm32_rcc_clock_init() 35 return -ENOMEM; in stm32_rcc_clock_init() 37 clk_data->num = max_binding; in stm32_rcc_clock_init() 39 hws = clk_data->hws; in stm32_rcc_clock_init() [all …]
/linux/include/linux/
H A D	clk-provider.h	1 /* SPDX-License-Identifier: GPL-2.0 / 3 Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 14 * top-level framework. custom flags for dealing with hardware specifics 20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent / 26 #define CLK_SET_RATE_NO_REPARENT BIT(7) / don't re-parent on rate change / 31 / parents need enable during gate/ungate, set rate and re-parent / 42 struct clk_rate_request - Structur 717 u8 width; global() member 723 clk_div_mask(width) global() argument 791 clk_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 809 clk_hw_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 827 clk_hw_register_divider_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,lock) global() argument 846 clk_hw_register_divider_parent_data(dev,name,parent_data,flags,reg,shift,width,clk_divider_flags,lock) global() argument 866 clk_hw_register_divider_table(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 886 clk_hw_register_divider_table_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 907 clk_hw_register_divider_table_parent_data(dev,name,parent_data,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 927 devm_clk_hw_register_divider(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,lock) global() argument 944 devm_clk_hw_register_divider_parent_hw(dev,name,parent_hw,flags,reg,shift,width,clk_divider_flags,lock) global() argument 965 devm_clk_hw_register_divider_table(dev,name,parent_name,flags,reg,shift,width,clk_divider_flags,table,lock) global() argument 1046 clk_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1065 clk_hw_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1071 clk_hw_register_mux_hws(dev,name,parent_hws,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1076 clk_hw_register_mux_parent_data(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1083 clk_hw_register_mux_parent_data_table(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,table,lock) global() argument 1089 devm_clk_hw_register_mux(dev,name,parent_names,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1096 devm_clk_hw_register_mux_parent_hws(dev,name,parent_hws,num_parents,flags,reg,shift,width,clk_mux_flags,lock) global() argument 1103 devm_clk_hw_register_mux_parent_data_table(dev,name,parent_data,num_parents,flags,reg,shift,width,clk_mux_flags,table,lock) global() argument 1275 u8 width; global() member 1417 divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags) divider_round_rate() argument 1426 divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val) divider_ro_round_rate() argument [all...]
/linux/drivers/clk/mxs/
H A D	clk-frac.c	`1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk-provider.h> 13 * struct clk_frac - mxs fractional divider clock 14 * @hw: clk_hw for the fractional divider clock 16 * @shift: the divider bit shift 17 * @width: the divider bit width 20 * The clock is an adjustable fractional divider with a busy bit to wait 21 * when the divider is adjusted. 27 u8 width; member 40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate() [all …]`
/linux/drivers/clk/x86/
H A D	clk-cgu.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2020-2022 MaxLinear, Inc. 8 #include <linux/clk-provider.h> 12 #include "clk-cgu.h" 29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed() 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed() 31 list->div_width, list->div_val); in lgm_clk_register_fixed() 33 return clk_hw_register_fixed_rate(NULL, list->name, in lgm_clk_register_fixed() 34 list->parent_data[0].name, in lgm_clk_register_fixed() 35 list->flags, list->mux_flags); in lgm_clk_register_fixed() [all …]
/linux/drivers/clk/bcm/
H A D	clk-kona.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 16 #include <linux/clk-provider.h> 24 #define BAD_CLK_NAME ((const char )-1) 33 #define FLAG_SET(obj, type, flag) ((obj)->flags \|= FLAG(type, flag)) 34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0) 44 #define policy_exists(policy) ((policy)->offset != 0) 55 #define hyst_exists(hyst) ((hyst)->offset != 0) [all …]
H A D	clk-kona.c	1 // SPDX-License-Identifier: GPL-2.0-only 7 #include "clk-kona.h" 12 #include <linux/clk-provider.h> 28 /* Produces a mask of set bits covering a range of a 32-bit value */ 29 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument 31 return ((1 << width) - 1) << shift; in bitfield_mask() 35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument 37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract() 41 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument 43 u32 mask = bitfield_mask(shift, width); in bitfield_replace() [all …]
H A D	clk-kona-setup.c	1 // SPDX-License-Identifier: GPL-2.0-only 10 #include "clk-kona.h" 13 #define selector_clear_exists(sel) ((sel)->width = 0) 20 struct ccu_policy ccu_policy = &ccu->policy; in ccu_data_offsets_valid() 23 limit = ccu->range - sizeof(u32); in ccu_data_offsets_valid() 26 if (ccu_policy->enable.offset > limit) { in ccu_data_offsets_valid() 29 ccu->name, ccu_policy->enable.offset, limit); in ccu_data_offsets_valid() 32 if (ccu_policy->control.offset > limit) { in ccu_data_offsets_valid() 35 ccu->name, ccu_policy->control.offset, limit); in ccu_data_offsets_valid() 45 struct peri_clk_data peri = bcm_clk->u.peri; in clk_requires_trigger() [all …]
/linux/drivers/clk/baikal-t1/
H A D	ccu-div.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 5 Baikal-T1 CCU Dividers interface driver 10 #include <linux/clk-provider.h> 17 * CCU Divider private clock IDs 21 #define CCU_SYS_SATA_CLK -1 22 #define CCU_SYS_XGMAC_CLK -2 25 * CCU Divider private flags 26 * @CCU_DIV_BASIC: Basic divider clock required by the kernel as early as 28 * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1. 30 * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3]. [all …]`
/linux/drivers/clk/sprd/
H A D	div.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 3 // Spreadtrum divider clock driver 14 struct sprd_div_internal - Internal divider description 15 * @shift: Bit offset of the divider in its register 16 * @width: Width of the divider field in its register 18 * That structure represents a single divider, and is meant to be 25 u8 width; member 32 .width = _width, \`
/linux/drivers/media/i2c/cx25840/
H A D	cx25840-ir.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 13 #include <media/drv-intf/cx25840.h> 14 #include <media/rc-core.h> 16 #include "cx25840-core.h" 117 return state ? state->ir_state : NULL; in to_ir_state() 122 * Rx and Tx Clock Divider register computations 124 * Note the largest clock divider value of 0xffff corresponds to: 135 d--; in count_to_clock_divider() 145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() [all …]
/linux/drivers/clk/zynqmp/
H A D	divider.c	`1 // SPDX-License-Identifier: GPL-2.0 3 * Zynq UltraScale+ MPSoC Divider support 5 * Copyright (C) 2016-2019 Xilinx 7 * Adjustable divider clock implementation 11 #include <linux/clk-provider.h> 13 #include "clk-zynqmp.h" 16 * DOC: basic adjustable divider clock that cannot gate 19 * prepare - clk_prepare only ensures that parents are prepared 20 * enable - clk_enable only ensures that parents are enabled 21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor) [all …]`
/linux/drivers/media/pci/cx23885/
H A D	cx23888-ir.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 11 #include "cx23888-ir.h" 16 #include <media/v4l2-device.h> 17 #include <media/rc-core.h> 161 * Rx and Tx Clock Divider register computations 163 * Note the largest clock divider value of 0xffff corresponds to: 174 d--; in count_to_clock_divider() 184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument 186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq() 189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument [all …]
/linux/Documentation/devicetree/bindings/spi/
H A D	spi_oc_tiny.txt	`4 - compatible : should be "opencores,tiny-spi-rtlsvn2". 5 - gpios : should specify GPIOs used for chipselect. 7 - clock-frequency : input clock frequency to the core. 8 - baud-width: width, in bits, of the programmable divider used to scale 11 The clock-frequency and baud-width properties are needed only if the divider 12 is programmable. They are not needed if the divider is fixed.`
/linux/drivers/clk/sunxi-ng/
H A D	ccu_div.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 9 #include <linux/clk-provider.h> 15 struct ccu_div_internal - Internal divider description 16 * @shift: Bit offset of the divider in its register 17 * @width: Width of the divider field in its register 18 * @max: Maximum value allowed for that divider. This is the 21 * @flags: clk_divider flags to apply on this divider 22 * @table: Divider table pointer (if applicable) 24 * That structure represents a single divider, and is meant to be 33 u8 width; member [all …]
/linux/drivers/clk/microchip/
H A D	clk-mpfs-ccc.c	1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 12 #include <dt-bindings/clock/microchip,mpfs-clock.h> 49 u32 width; member 76 void __iomem mult_addr = ccc_hw->base + ccc_hw->reg_offset; in mpfs_ccc_pll_recalc_rate() 77 void __iomem ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR; in mpfs_ccc_pll_recalc_rate() 91 void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR; in mpfs_ccc_pll_get_parent() 104 .width = _width, \ 118 struct clk_divider divider; member 126 .divider.shift = _shift, \ [all …]
/linux/drivers/clk/nxp/
H A D	clk-lpc32xx.c	1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #include <linux/clk-provider.h> 12 #include <dt-bindings/clock/lpc32xx-clock.h> 253 * divider register does not contain information about selected rate. 354 u8 width; member 393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable() 395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable() 396 return -EBUSY; in clk_mask_enable() 398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable() 399 clk->enable_mask, clk->enable); in clk_mask_enable() [all …]
/linux/drivers/clk/actions/
H A D	owl-divider.c	1 // SPDX-License-Identifier: GPL-2.0+ 3 // OWL divider clock driver 6 // Author: David Liu <liuwei@actions-semi.com> 11 #include <linux/clk-provider.h> 14 #include "owl-divider.h" 21 return divider_round_rate(&common->hw, rate, parent_rate, in owl_divider_helper_round_rate() 22 div_hw->table, div_hw->width, in owl_divider_helper_round_rate() 23 div_hw->div_flags); in owl_divider_helper_round_rate() 31 return owl_divider_helper_round_rate(&div->common, &div->div_hw, in owl_divider_round_rate() 42 regmap_read(common->regmap, div_hw->reg, &reg); in owl_divider_helper_recalc_rate() [all …]

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