| /linux/drivers/clk/ |
| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7 * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
21 * DOC: basic adjustable divider clock that cannot gate
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
27 * parent - fixed parent. No clk_set_parent support
30 static inline u32 clk_div_readl(struct clk_divider *divider) in clk_div_readl() argument
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| H A D | clk-milbeaut.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
20 #define M10V_PLL1DIV2 "pll1-2"
22 #define M10V_PLL2DIV2 "pll2-2"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
31 #define M10V_PLL10DIV2 "pll10-2"
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-half-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #define div_mask(width) ((1 << (width)) - 1) argument
17 return abs(rate - now) < abs(rate - best); in _is_best_half_div()
25 struct clk_divider *divider = to_clk_divider(hw); in clk_half_divider_recalc_rate() local
28 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
36 unsigned long *best_parent_rate, u8 width, in clk_half_divider_bestdiv() argument
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
54 bestdiv = (bestdiv - 3) / 2; in clk_half_divider_bestdiv()
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| /linux/drivers/clk/hisilicon/ |
| H A D | clkdivider-hi6220.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hisilicon hi6220 SoC divider clock driver
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1) argument
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
25 * @reg: register containing divider
26 * @shift: shift to the divider bit field
27 * @width: width of the divider bit field
28 * @mask: mask for setting divider rate
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| /linux/drivers/clk/imx/ |
| H A D | clk-divider-gate.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
15 struct clk_divider divider; member
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
52 val = div_gate->cached_val; in clk_divider_gate_recalc_rate()
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| H A D | clk-composite-8m.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
31 struct clk_divider *divider = to_clk_divider(hw); in imx8m_clk_composite_divider_recalc_rate() local
36 prediv_value = readl(divider->reg) >> divider->shift; in imx8m_clk_composite_divider_recalc_rate()
37 prediv_value &= clk_div_mask(divider->width); in imx8m_clk_composite_divider_recalc_rate()
40 NULL, divider->flags, in imx8m_clk_composite_divider_recalc_rate()
41 divider->width); in imx8m_clk_composite_divider_recalc_rate()
43 div_value = readl(divider->reg) >> PCG_DIV_SHIFT; in imx8m_clk_composite_divider_recalc_rate()
47 divider->flags, PCG_DIV_WIDTH); in imx8m_clk_composite_divider_recalc_rate()
56 int ret = -EINVAL; in imx8m_clk_composite_compute_dividers()
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| H A D | clk-fixup-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
12 #define div_mask(d) ((1 << (d->width)) - 1)
15 * struct clk_fixup_div - imx integer fixup divider clock
16 * @divider: the parent class
20 * The imx fixup divider clock is a subclass of basic clk_divider
24 struct clk_divider divider; member
31 struct clk_divider *divider = to_clk_divider(hw); in to_clk_fixup_div() local
33 return container_of(divider, struct clk_fixup_div, divider); in to_clk_fixup_div()
41 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate); in clk_fixup_div_recalc_rate()
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| H A D | clk-composite-93.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
52 if (gate->lock) in imx93_clk_composite_gate_endisable()
53 spin_lock_irqsave(gate->lock, flags); in imx93_clk_composite_gate_endisable()
55 reg = readl(gate->reg); in imx93_clk_composite_gate_endisable()
58 reg &= ~BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
60 reg |= BIT(gate->bit_idx); in imx93_clk_composite_gate_endisable()
62 writel(reg, gate->reg); in imx93_clk_composite_gate_endisable()
64 imx93_clk_composite_wait_ready(hw, gate->reg); in imx93_clk_composite_gate_endisable()
66 if (gate->lock) in imx93_clk_composite_gate_endisable()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
21 static int get_div(struct tegra_clk_frac_div *divider, unsigned long rate, in get_div() argument
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
38 struct tegra_clk_frac_div *divider = to_clk_frac_div(hw); in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
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| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
100 * @shift: shift to the divider bit field
101 * @width: width of the divider bit field
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| /linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #include <dt-bindings/clock/clock.h>
17 * top-level framework. Custom flags for dealing with hardware specifics
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
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| /linux/drivers/clk/xilinx/ |
| H A D | clk-xlnx-clock-wizard.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2021 Xilinx
14 #include <linux/clk-provider.h>
96 /* Divider limits, from UG572 Table 3-4 for Ultrascale+ */
118 /* Get the mask from width */
119 #define div_mask(width) ((1 << (width)) - 1) argument
121 /* Extract divider instance from clock hardware instance */
132 * struct clk_wzrd - Clock wizard private data structure
155 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
157 * @hw: handle between common and hardware-specific interfaces
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| /linux/drivers/clk/mxs/ |
| H A D | clk-frac.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
13 * struct clk_frac - mxs fractional divider clock
14 * @hw: clk_hw for the fractional divider clock
16 * @shift: the divider bit shift
17 * @width: the divider bit width
20 * The clock is an adjustable fractional divider with a busy bit to wait
21 * when the divider is adjusted.
27 u8 width; member
40 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
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| H A D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
12 * struct clk_div - mxs integer divider clock
13 * @divider: the parent class
18 * The mxs divider clock is a subclass of basic clk_divider with an
22 struct clk_divider divider; member
30 struct clk_divider *divider = to_clk_divider(hw); in to_clk_div() local
32 return container_of(divider, struct clk_div, divider); in to_clk_div()
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
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| /linux/drivers/clk/ultrarisc/ |
| H A D | clk-ultrarisc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-ultrarisc.h"
22 struct clk_divider divider; member
32 struct clk_divider *divider = to_clk_divider(hw); in to_ultrarisc_divider_clk() local
34 return container_of(divider, struct ultrarisc_divider_clk, divider); in to_ultrarisc_divider_clk()
41 const struct ultrarisc_pll_layout *layout = pll->layout; in ultrarisc_pll_recalc_rate()
47 cfg1 = readl_relaxed(pll->base + layout->cfg1_offset); in ultrarisc_pll_recalc_rate()
48 cfg2 = readl_relaxed(pll->base + layout->cfg2_offset); in ultrarisc_pll_recalc_rate()
50 frac = field_get(layout->frac_mask, cfg1); in ultrarisc_pll_recalc_rate()
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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| H A D | clk-kona.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
29 static inline u32 bitfield_mask(u32 shift, u32 width) in bitfield_mask() argument
31 return ((1 << width) - 1) << shift; in bitfield_mask()
35 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
37 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
41 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument
43 u32 mask = bitfield_mask(shift, width); in bitfield_replace()
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| /linux/drivers/clk/sprd/ |
| H A D | div.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Spreadtrum divider clock driver
14 * struct sprd_div_internal - Internal divider description
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
18 * That structure represents a single divider, and is meant to be
25 u8 width; member
32 .width = _width, \
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| /linux/drivers/media/i2c/cx25840/ |
| H A D | cx25840-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
135 d--; in count_to_clock_divider()
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
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| /linux/drivers/clk/cix/ |
| H A D | clk-sky1-audss.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/cix,sky1-audss-cru.h>
150 u8 width; member
198 -1, 0, 0, 0,
206 -1, 0, 0, 0,
208 -1, 0, 0,
214 -1, 0, 0, 0,
216 -1, 0, 0,
223 -1, 0, 0, 0,
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi_oc_tiny.txt | 4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
11 The clock-frequency and baud-width properties are needed only if the divider
12 is programmable. They are not needed if the divider is fixed.
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| /linux/drivers/clk/renesas/ |
| H A D | rzv2h-cpg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct pll - Structure for PLL configuration
43 * struct ddiv - Structure for dynamic switching divider
46 * @shift: position of the divider bit
47 * @width: width of the divider
49 * @no_rmw: flag to indicate if the register is read-modify-write
55 unsigned int width:4; member
61 * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits,
63 * `0x1f` to indicate that monitor bits are not supported for static divider
72 .width = _width, \
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| /linux/drivers/media/pci/cx23885/ |
| H A D | cx23888-ir.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
174 d--; in count_to_clock_divider()
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) in clock_divider_to_carrier_freq() argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16); in clock_divider_to_carrier_freq()
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, in clock_divider_to_freq() argument
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| /linux/drivers/clk/zynqmp/ |
| H A D | divider.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC Divider support
5 * Copyright (C) 2016-2019 Xilinx
7 * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16 * DOC: basic adjustable divider clock that cannot gate
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
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| /linux/drivers/clk/meson/ |
| H A D | clk-regmap.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
15 * struct clk_regmap - regmap backed clock
17 * @hw: handle between common and hardware-specific interfaces
39 * struct clk_regmap_gate_data - regmap backed gate specific data
43 * @flags: hardware-specific flags
57 return (struct clk_regmap_gate_data *)clk->data; in clk_get_regmap_gate_data()
64 * struct clk_regmap_div_data - regmap backed adjustable divider specific data
66 * @offset: offset of the register controlling the divider
67 * @shift: shift to the divider bit field
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