1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #define div_mask(width)	((1 << (width)) - 1)  argument
17 		return abs(rate - now) < abs(rate - best);  in _is_best_half_div()
25 	struct clk_divider *divider = to_clk_divider(hw);  in clk_half_divider_recalc_rate()  local
28 	val = readl(divider->reg) >> divider->shift;  in clk_half_divider_recalc_rate()
29 	val &= div_mask(divider->width);  in clk_half_divider_recalc_rate()
36 				    unsigned long *best_parent_rate, u8 width,  in clk_half_divider_bestdiv()  argument
46 	maxdiv = div_mask(width);  in clk_half_divider_bestdiv()
54 			bestdiv = (bestdiv - 3) / 2;  in clk_half_divider_bestdiv()
60 	 * The maximum divider we can use without overflowing  in clk_half_divider_bestdiv()
70 			 * parent rate, so return the divider immediately.  in clk_half_divider_bestdiv()
88 		bestdiv = div_mask(width);  in clk_half_divider_bestdiv()
98 	struct clk_divider *divider = to_clk_divider(hw);  in clk_half_divider_round_rate()  local
102 				       divider->width,  in clk_half_divider_round_rate()
103 				       divider->flags);  in clk_half_divider_round_rate()
111 	struct clk_divider *divider = to_clk_divider(hw);  in clk_half_divider_set_rate()  local
117 	value = (value - 3) / 2;  in clk_half_divider_set_rate()
118 	value =  min_t(unsigned int, value, div_mask(divider->width));  in clk_half_divider_set_rate()
120 	if (divider->lock)  in clk_half_divider_set_rate()
121 		spin_lock_irqsave(divider->lock, flags);  in clk_half_divider_set_rate()
123 		__acquire(divider->lock);  in clk_half_divider_set_rate()
125 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_half_divider_set_rate()
126 		val = div_mask(divider->width) << (divider->shift + 16);  in clk_half_divider_set_rate()
128 		val = readl(divider->reg);  in clk_half_divider_set_rate()
129 		val &= ~(div_mask(divider->width) << divider->shift);  in clk_half_divider_set_rate()
131 	val |= value << divider->shift;  in clk_half_divider_set_rate()
132 	writel(val, divider->reg);  in clk_half_divider_set_rate()
134 	if (divider->lock)  in clk_half_divider_set_rate()
135 		spin_unlock_irqrestore(divider->lock, flags);  in clk_half_divider_set_rate()
137 		__release(divider->lock);  in clk_half_divider_set_rate()
152  * src1 --|--\
153  *        |M |--[GATE]-[DIV]-
154  * src2 --|--/
169 	struct clk_hw *hw = ERR_PTR(-ENOMEM);  in rockchip_clk_register_halfdiv()
179 			return ERR_PTR(-ENOMEM);  in rockchip_clk_register_halfdiv()
181 		mux->reg = base + muxdiv_offset;  in rockchip_clk_register_halfdiv()
182 		mux->shift = mux_shift;  in rockchip_clk_register_halfdiv()
183 		mux->mask = BIT(mux_width) - 1;  in rockchip_clk_register_halfdiv()
184 		mux->flags = mux_flags;  in rockchip_clk_register_halfdiv()
185 		mux->lock = lock;  in rockchip_clk_register_halfdiv()
195 		gate->flags = gate_flags;  in rockchip_clk_register_halfdiv()
196 		gate->reg = base + gate_offset;  in rockchip_clk_register_halfdiv()
197 		gate->bit_idx = gate_shift;  in rockchip_clk_register_halfdiv()
198 		gate->lock = lock;  in rockchip_clk_register_halfdiv()
207 		div->flags = div_flags;  in rockchip_clk_register_halfdiv()
208 		div->reg = base + muxdiv_offset;  in rockchip_clk_register_halfdiv()
209 		div->shift = div_shift;  in rockchip_clk_register_halfdiv()
210 		div->width = div_width;  in rockchip_clk_register_halfdiv()
211 		div->lock = lock;  in rockchip_clk_register_halfdiv()
216 				       mux ? &mux->hw : NULL, mux_ops,  in rockchip_clk_register_halfdiv()
217 				       div ? &div->hw : NULL, div_ops,  in rockchip_clk_register_halfdiv()
218 				       gate ? &gate->hw : NULL, gate_ops,  in rockchip_clk_register_halfdiv()
223 	return hw->clk;  in rockchip_clk_register_halfdiv()