1 // SPDX-License-Identifier: GPL-2.0
7  * Based on rzg2l-cpg.c
16 #include <linux/clk-provider.h>
27 #include <linux/reset-controller.h>
30 #include <dt-bindings/clock/renesas-cpg-mssr.h>
32 #include "rzv2h-cpg.h"
46 #define CPG_BUS_MSTOP(m)	(CPG_BUS_1_MSTOP + ((m) - 1) * 4)
69  * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
78  * @num_resets: Number of Module Resets in info->resets[]
114  * struct mod_clock - Module clock
118  * @hw: handle between common and hardware-specific interfaces
124  * @ext_clk_mux_index: mux index for external clock source, or -1 if internal
141  * struct ddiv_clk - DDIV clock
144  * @div: divider clk
156  * struct rzv2h_ff_mod_status_clk - Fixed Factor Module Status Clock
174 	struct rzv2h_cpg_priv *priv = pll_clk->priv;  in rzv2h_cpg_pll_clk_is_enabled()
175 	u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset));  in rzv2h_cpg_pll_clk_is_enabled()
185 	struct rzv2h_cpg_priv *priv = pll_clk->priv;  in rzv2h_cpg_pll_clk_enable()
186 	struct pll pll = pll_clk->pll;  in rzv2h_cpg_pll_clk_enable()
199 	       priv->base + stby_offset);  in rzv2h_cpg_pll_clk_enable()
209 	ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,  in rzv2h_cpg_pll_clk_enable()
213 		dev_err(priv->dev, "Failed to enable PLL 0x%x/%pC\n",  in rzv2h_cpg_pll_clk_enable()
214 			stby_offset, hw->clk);  in rzv2h_cpg_pll_clk_enable()
223 	struct rzv2h_cpg_priv *priv = pll_clk->priv;  in rzv2h_cpg_pll_clk_recalc_rate()
224 	struct pll pll = pll_clk->pll;  in rzv2h_cpg_pll_clk_recalc_rate()
231 	clk1 = readl(priv->base + CPG_PLL_CLK1(pll.offset));  in rzv2h_cpg_pll_clk_recalc_rate()
232 	clk2 = readl(priv->base + CPG_PLL_CLK2(pll.offset));  in rzv2h_cpg_pll_clk_recalc_rate()
251 	struct device *dev = priv->dev;  in rzv2h_cpg_pll_clk_register()
258 	parent = priv->clks[core->parent];  in rzv2h_cpg_pll_clk_register()
264 		return ERR_PTR(-ENOMEM);  in rzv2h_cpg_pll_clk_register()
267 	init.name = core->name;  in rzv2h_cpg_pll_clk_register()
273 	pll_clk->hw.init = &init;  in rzv2h_cpg_pll_clk_register()
274 	pll_clk->pll = core->cfg.pll;  in rzv2h_cpg_pll_clk_register()
275 	pll_clk->priv = priv;  in rzv2h_cpg_pll_clk_register()
277 	ret = devm_clk_hw_register(dev, &pll_clk->hw);  in rzv2h_cpg_pll_clk_register()
281 	return pll_clk->hw.clk;  in rzv2h_cpg_pll_clk_register()
287 	struct clk_divider *divider = to_clk_divider(hw);  in rzv2h_ddiv_recalc_rate()  local
290 	val = readl(divider->reg) >> divider->shift;  in rzv2h_ddiv_recalc_rate()
291 	val &= clk_div_mask(divider->width);  in rzv2h_ddiv_recalc_rate()
293 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in rzv2h_ddiv_recalc_rate()
294 				   divider->flags, divider->width);  in rzv2h_ddiv_recalc_rate()
300 	struct clk_divider *divider = to_clk_divider(hw);  in rzv2h_ddiv_determine_rate()  local
302 	return divider_determine_rate(hw, req, divider->table, divider->width,  in rzv2h_ddiv_determine_rate()
303 				      divider->flags);  in rzv2h_ddiv_determine_rate()
320 	struct clk_divider *divider = to_clk_divider(hw);  in rzv2h_ddiv_set_rate()  local
321 	struct ddiv_clk *ddiv = to_ddiv_clock(divider);  in rzv2h_ddiv_set_rate()
322 	struct rzv2h_cpg_priv *priv = ddiv->priv;  in rzv2h_ddiv_set_rate()
328 	value = divider_get_val(rate, parent_rate, divider->table,  in rzv2h_ddiv_set_rate()
329 				divider->width, divider->flags);  in rzv2h_ddiv_set_rate()
333 	spin_lock_irqsave(divider->lock, flags);  in rzv2h_ddiv_set_rate()
335 	ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);  in rzv2h_ddiv_set_rate()
339 	val = readl(divider->reg) | DDIV_DIVCTL_WEN(divider->shift);  in rzv2h_ddiv_set_rate()
340 	val &= ~(clk_div_mask(divider->width) << divider->shift);  in rzv2h_ddiv_set_rate()
341 	val |= (u32)value << divider->shift;  in rzv2h_ddiv_set_rate()
342 	writel(val, divider->reg);  in rzv2h_ddiv_set_rate()
344 	ret = rzv2h_cpg_wait_ddiv_clk_update_done(priv->base, ddiv->mon);  in rzv2h_ddiv_set_rate()
347 	spin_unlock_irqrestore(divider->lock, flags);  in rzv2h_ddiv_set_rate()
361 	struct ddiv cfg_ddiv = core->cfg.ddiv;  in rzv2h_cpg_ddiv_clk_register()
363 	struct device *dev = priv->dev;  in rzv2h_cpg_ddiv_clk_register()
365 	u8 width = cfg_ddiv.width;  in rzv2h_cpg_ddiv_clk_register()  local
372 	parent = priv->clks[core->parent];  in rzv2h_cpg_ddiv_clk_register()
378 	if ((shift + width) > 16)  in rzv2h_cpg_ddiv_clk_register()
379 		return ERR_PTR(-EINVAL);  in rzv2h_cpg_ddiv_clk_register()
381 	ddiv = devm_kzalloc(priv->dev, sizeof(*ddiv), GFP_KERNEL);  in rzv2h_cpg_ddiv_clk_register()
383 		return ERR_PTR(-ENOMEM);  in rzv2h_cpg_ddiv_clk_register()
385 	init.name = core->name;  in rzv2h_cpg_ddiv_clk_register()
394 	ddiv->priv = priv;  in rzv2h_cpg_ddiv_clk_register()
395 	ddiv->mon = cfg_ddiv.monbit;  in rzv2h_cpg_ddiv_clk_register()
396 	div = &ddiv->div;  in rzv2h_cpg_ddiv_clk_register()
397 	div->reg = priv->base + cfg_ddiv.offset;  in rzv2h_cpg_ddiv_clk_register()
398 	div->shift = shift;  in rzv2h_cpg_ddiv_clk_register()
399 	div->width = width;  in rzv2h_cpg_ddiv_clk_register()
400 	div->flags = core->flag;  in rzv2h_cpg_ddiv_clk_register()
401 	div->lock = &priv->rmw_lock;  in rzv2h_cpg_ddiv_clk_register()
402 	div->hw.init = &init;  in rzv2h_cpg_ddiv_clk_register()
403 	div->table = core->dtable;  in rzv2h_cpg_ddiv_clk_register()
405 	ret = devm_clk_hw_register(dev, &div->hw);  in rzv2h_cpg_ddiv_clk_register()
409 	return div->hw.clk;  in rzv2h_cpg_ddiv_clk_register()
416 	struct smuxed mux = core->cfg.smux;  in rzv2h_cpg_mux_clk_register()
419 	clk_hw = devm_clk_hw_register_mux(priv->dev, core->name,  in rzv2h_cpg_mux_clk_register()
420 					  core->parent_names, core->num_parents,  in rzv2h_cpg_mux_clk_register()
421 					  core->flag, priv->base + mux.offset,  in rzv2h_cpg_mux_clk_register()
422 					  mux.shift, mux.width,  in rzv2h_cpg_mux_clk_register()
423 					  core->mux_flags, &priv->rmw_lock);  in rzv2h_cpg_mux_clk_register()
427 	return clk_hw->clk;  in rzv2h_cpg_mux_clk_register()
434 	struct rzv2h_cpg_priv *priv = fix->priv;  in rzv2h_clk_ff_mod_status_is_enabled()
435 	u32 offset = GET_CLK_MON_OFFSET(fix->conf.mon_index);  in rzv2h_clk_ff_mod_status_is_enabled()
436 	u32 bitmask = BIT(fix->conf.mon_bit);  in rzv2h_clk_ff_mod_status_is_enabled()
439 	val = readl(priv->base + offset);  in rzv2h_clk_ff_mod_status_is_enabled()
454 	WARN_DEBUG(core->parent >= priv->num_core_clks);  in rzv2h_cpg_fixed_mod_status_clk_register()
455 	parent = priv->clks[core->parent];  in rzv2h_cpg_fixed_mod_status_clk_register()
460 	parent = priv->clks[core->parent];  in rzv2h_cpg_fixed_mod_status_clk_register()
464 	clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);  in rzv2h_cpg_fixed_mod_status_clk_register()
466 		return ERR_PTR(-ENOMEM);  in rzv2h_cpg_fixed_mod_status_clk_register()
468 	clk_hw_data->priv = priv;  in rzv2h_cpg_fixed_mod_status_clk_register()
469 	clk_hw_data->conf = core->cfg.fixed_mod;  in rzv2h_cpg_fixed_mod_status_clk_register()
471 	init.name = core->name;  in rzv2h_cpg_fixed_mod_status_clk_register()
472 	init.ops = priv->ff_mod_status_ops;  in rzv2h_cpg_fixed_mod_status_clk_register()
477 	fix = &clk_hw_data->fix;  in rzv2h_cpg_fixed_mod_status_clk_register()
478 	fix->hw.init = &init;  in rzv2h_cpg_fixed_mod_status_clk_register()
479 	fix->mult = core->mult;  in rzv2h_cpg_fixed_mod_status_clk_register()
480 	fix->div = core->div;  in rzv2h_cpg_fixed_mod_status_clk_register()
482 	ret = devm_clk_hw_register(priv->dev, &clk_hw_data->fix.hw);  in rzv2h_cpg_fixed_mod_status_clk_register()
486 	return clk_hw_data->fix.hw.clk;  in rzv2h_cpg_fixed_mod_status_clk_register()
493 	unsigned int clkidx = clkspec->args[1];  in rzv2h_cpg_clk_src_twocell_get()
495 	struct device *dev = priv->dev;  in rzv2h_cpg_clk_src_twocell_get()
499 	switch (clkspec->args[0]) {  in rzv2h_cpg_clk_src_twocell_get()
502 		if (clkidx > priv->last_dt_core_clk) {  in rzv2h_cpg_clk_src_twocell_get()
504 			return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
506 		clk = priv->clks[clkidx];  in rzv2h_cpg_clk_src_twocell_get()
511 		if (clkidx >= priv->num_mod_clks) {  in rzv2h_cpg_clk_src_twocell_get()
513 			return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
515 		clk = priv->clks[priv->num_core_clks + clkidx];  in rzv2h_cpg_clk_src_twocell_get()
519 		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);  in rzv2h_cpg_clk_src_twocell_get()
520 		return ERR_PTR(-EINVAL);  in rzv2h_cpg_clk_src_twocell_get()
528 			clkspec->args[0], clkspec->args[1], clk,  in rzv2h_cpg_clk_src_twocell_get()
537 	struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;  in rzv2h_cpg_register_core_clk()
538 	unsigned int id = core->id, div = core->div;  in rzv2h_cpg_register_core_clk()
539 	struct device *dev = priv->dev;  in rzv2h_cpg_register_core_clk()
543 	WARN_DEBUG(id >= priv->num_core_clks);  in rzv2h_cpg_register_core_clk()
544 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in rzv2h_cpg_register_core_clk()
546 	switch (core->type) {  in rzv2h_cpg_register_core_clk()
548 		clk = of_clk_get_by_name(priv->dev->of_node, core->name);  in rzv2h_cpg_register_core_clk()
551 		WARN_DEBUG(core->parent >= priv->num_core_clks);  in rzv2h_cpg_register_core_clk()
552 		parent = priv->clks[core->parent];  in rzv2h_cpg_register_core_clk()
559 		clk_hw = devm_clk_hw_register_fixed_factor(dev, core->name,  in rzv2h_cpg_register_core_clk()
561 							   core->mult, div);  in rzv2h_cpg_register_core_clk()
565 			clk = clk_hw->clk;  in rzv2h_cpg_register_core_clk()
568 		if (!priv->ff_mod_status_ops) {  in rzv2h_cpg_register_core_clk()
569 			priv->ff_mod_status_ops =  in rzv2h_cpg_register_core_clk()
570 				devm_kzalloc(dev, sizeof(*priv->ff_mod_status_ops), GFP_KERNEL);  in rzv2h_cpg_register_core_clk()
571 			if (!priv->ff_mod_status_ops) {  in rzv2h_cpg_register_core_clk()
572 				clk = ERR_PTR(-ENOMEM);  in rzv2h_cpg_register_core_clk()
575 			memcpy(priv->ff_mod_status_ops, &clk_fixed_factor_ops,  in rzv2h_cpg_register_core_clk()
577 			priv->ff_mod_status_ops->is_enabled = rzv2h_clk_ff_mod_status_is_enabled;  in rzv2h_cpg_register_core_clk()
598 	priv->clks[id] = clk;  in rzv2h_cpg_register_core_clk()
603 		core->name, PTR_ERR(clk));  in rzv2h_cpg_register_core_clk()
611 	atomic_t *mstop = &priv->mstop_count[mstop_index * 16];  in rzv2h_mod_clock_mstop_enable()
616 	spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_enable()
623 		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_mod_clock_mstop_enable()
624 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_enable()
632 	atomic_t *mstop = &priv->mstop_count[mstop_index * 16];  in rzv2h_mod_clock_mstop_disable()
637 	spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_disable()
644 		writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_mod_clock_mstop_disable()
645 	spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_mod_clock_mstop_disable()
656 	parent_clk = clk_get_parent(hw->clk);  in rzv2h_parent_clk_mux_to_index()
661 	val = readl(mux->reg) >> mux->shift;  in rzv2h_parent_clk_mux_to_index()
662 	val &= mux->mask;  in rzv2h_parent_clk_mux_to_index()
663 	return clk_mux_val_to_index(parent_hw, mux->table, 0, val);  in rzv2h_parent_clk_mux_to_index()
669 	struct rzv2h_cpg_priv *priv = clock->priv;  in rzv2h_mod_clock_is_enabled()
670 	int mon_index = clock->mon_index;  in rzv2h_mod_clock_is_enabled()
674 	if (clock->ext_clk_mux_index >= 0 &&  in rzv2h_mod_clock_is_enabled()
675 	    rzv2h_parent_clk_mux_to_index(hw) == clock->ext_clk_mux_index)  in rzv2h_mod_clock_is_enabled()
676 		mon_index = -1;  in rzv2h_mod_clock_is_enabled()
680 		bitmask = BIT(clock->mon_bit);  in rzv2h_mod_clock_is_enabled()
682 		if (!(readl(priv->base + offset) & bitmask))  in rzv2h_mod_clock_is_enabled()
686 	offset = GET_CLK_ON_OFFSET(clock->on_index);  in rzv2h_mod_clock_is_enabled()
687 	bitmask = BIT(clock->on_bit);  in rzv2h_mod_clock_is_enabled()
689 	return readl(priv->base + offset) & bitmask;  in rzv2h_mod_clock_is_enabled()
696 	unsigned int reg = GET_CLK_ON_OFFSET(clock->on_index);  in rzv2h_mod_clock_endisable()
697 	struct rzv2h_cpg_priv *priv = clock->priv;  in rzv2h_mod_clock_endisable()
698 	u32 bitmask = BIT(clock->on_bit);  in rzv2h_mod_clock_endisable()
699 	struct device *dev = priv->dev;  in rzv2h_mod_clock_endisable()
703 	dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,  in rzv2h_mod_clock_endisable()
712 		writel(value, priv->base + reg);  in rzv2h_mod_clock_endisable()
713 		if (clock->mstop_data != BUS_MSTOP_NONE)  in rzv2h_mod_clock_endisable()
714 			rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);  in rzv2h_mod_clock_endisable()
716 		if (clock->mstop_data != BUS_MSTOP_NONE)  in rzv2h_mod_clock_endisable()
717 			rzv2h_mod_clock_mstop_disable(priv, clock->mstop_data);  in rzv2h_mod_clock_endisable()
718 		writel(value, priv->base + reg);  in rzv2h_mod_clock_endisable()
721 	if (!enable || clock->mon_index < 0)  in rzv2h_mod_clock_endisable()
724 	reg = GET_CLK_MON_OFFSET(clock->mon_index);  in rzv2h_mod_clock_endisable()
725 	bitmask = BIT(clock->mon_bit);  in rzv2h_mod_clock_endisable()
726 	error = readl_poll_timeout_atomic(priv->base + reg, value,  in rzv2h_mod_clock_endisable()
730 			GET_CLK_ON_OFFSET(clock->on_index), hw->clk);  in rzv2h_mod_clock_endisable()
756 	struct device *dev = priv->dev;  in rzv2h_cpg_register_mod_clk()
763 	id = GET_MOD_CLK_ID(priv->num_core_clks, mod->on_index, mod->on_bit);  in rzv2h_cpg_register_mod_clk()
764 	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);  in rzv2h_cpg_register_mod_clk()
765 	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);  in rzv2h_cpg_register_mod_clk()
766 	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);  in rzv2h_cpg_register_mod_clk()
768 	parent = priv->clks[mod->parent];  in rzv2h_cpg_register_mod_clk()
776 		clk = ERR_PTR(-ENOMEM);  in rzv2h_cpg_register_mod_clk()
780 	init.name = mod->name;  in rzv2h_cpg_register_mod_clk()
783 	if (mod->critical)  in rzv2h_cpg_register_mod_clk()
790 	clock->on_index = mod->on_index;  in rzv2h_cpg_register_mod_clk()
791 	clock->on_bit = mod->on_bit;  in rzv2h_cpg_register_mod_clk()
792 	clock->mon_index = mod->mon_index;  in rzv2h_cpg_register_mod_clk()
793 	clock->mon_bit = mod->mon_bit;  in rzv2h_cpg_register_mod_clk()
794 	clock->no_pm = mod->no_pm;  in rzv2h_cpg_register_mod_clk()
795 	clock->ext_clk_mux_index = mod->ext_clk_mux_index;  in rzv2h_cpg_register_mod_clk()
796 	clock->priv = priv;  in rzv2h_cpg_register_mod_clk()
797 	clock->hw.init = &init;  in rzv2h_cpg_register_mod_clk()
798 	clock->mstop_data = mod->mstop_data;  in rzv2h_cpg_register_mod_clk()
800 	ret = devm_clk_hw_register(dev, &clock->hw);  in rzv2h_cpg_register_mod_clk()
806 	priv->clks[id] = clock->hw.clk;  in rzv2h_cpg_register_mod_clk()
813 	if (clock->mstop_data != BUS_MSTOP_NONE &&  in rzv2h_cpg_register_mod_clk()
814 	    !mod->critical && rzv2h_mod_clock_is_enabled(&clock->hw)) {  in rzv2h_cpg_register_mod_clk()
815 		rzv2h_mod_clock_mstop_enable(priv, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
816 	} else if (clock->mstop_data != BUS_MSTOP_NONE && mod->critical) {  in rzv2h_cpg_register_mod_clk()
817 		unsigned long mstop_mask = FIELD_GET(BUS_MSTOP_BITS_MASK, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
818 		u16 mstop_index = FIELD_GET(BUS_MSTOP_IDX_MASK, clock->mstop_data);  in rzv2h_cpg_register_mod_clk()
819 		atomic_t *mstop = &priv->mstop_count[mstop_index * 16];  in rzv2h_cpg_register_mod_clk()
830 		spin_lock_irqsave(&priv->rmw_lock, flags);  in rzv2h_cpg_register_mod_clk()
838 			writel(val, priv->base + CPG_BUS_MSTOP(mstop_index));  in rzv2h_cpg_register_mod_clk()
839 		spin_unlock_irqrestore(&priv->rmw_lock, flags);  in rzv2h_cpg_register_mod_clk()
846 		mod->name, PTR_ERR(clk));  in rzv2h_cpg_register_mod_clk()
853 	unsigned int reg = GET_RST_OFFSET(priv->resets[id].reset_index);  in __rzv2h_cpg_assert()
854 	u32 mask = BIT(priv->resets[id].reset_bit);  in __rzv2h_cpg_assert()
855 	u8 monbit = priv->resets[id].mon_bit;  in __rzv2h_cpg_assert()
859 	dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",  in __rzv2h_cpg_assert()
864 	writel(value, priv->base + reg);  in __rzv2h_cpg_assert()
866 	reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);  in __rzv2h_cpg_assert()
869 	ret = readl_poll_timeout_atomic(priv->base + reg, value,  in __rzv2h_cpg_assert()
873 		writel(value, priv->base + GET_RST_OFFSET(priv->resets[id].reset_index));  in __rzv2h_cpg_assert()
907 	unsigned int reg = GET_RST_MON_OFFSET(priv->resets[id].mon_index);  in rzv2h_cpg_status()
908 	u8 monbit = priv->resets[id].mon_bit;  in rzv2h_cpg_status()
910 	return !!(readl(priv->base + reg) & BIT(monbit));  in rzv2h_cpg_status()
924 	unsigned int id = reset_spec->args[0];  in rzv2h_cpg_reset_xlate()
929 	for (i = 0; i < rcdev->nr_resets; i++) {  in rzv2h_cpg_reset_xlate()
930 		if (rst_index == priv->resets[i].reset_index &&  in rzv2h_cpg_reset_xlate()
931 		    rst_bit == priv->resets[i].reset_bit)  in rzv2h_cpg_reset_xlate()
935 	return -EINVAL;  in rzv2h_cpg_reset_xlate()
940 	priv->rcdev.ops = &rzv2h_cpg_reset_ops;  in rzv2h_cpg_reset_controller_register()
941 	priv->rcdev.of_node = priv->dev->of_node;  in rzv2h_cpg_reset_controller_register()
942 	priv->rcdev.dev = priv->dev;  in rzv2h_cpg_reset_controller_register()
943 	priv->rcdev.of_reset_n_cells = 1;  in rzv2h_cpg_reset_controller_register()
944 	priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;  in rzv2h_cpg_reset_controller_register()
945 	priv->rcdev.nr_resets = priv->num_resets;  in rzv2h_cpg_reset_controller_register()
947 	return devm_reset_controller_register(priv->dev, &priv->rcdev);  in rzv2h_cpg_reset_controller_register()
951  * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
963 	if (clkspec->np != pd->genpd.dev.of_node || clkspec->args_count != 2)  in rzv2h_cpg_is_pm_clk()
966 	switch (clkspec->args[0]) {  in rzv2h_cpg_is_pm_clk()
968 		struct rzv2h_cpg_priv *priv = pd->priv;  in rzv2h_cpg_is_pm_clk()
969 		unsigned int id = clkspec->args[1];  in rzv2h_cpg_is_pm_clk()
972 		if (id >= priv->num_mod_clks)  in rzv2h_cpg_is_pm_clk()
975 		if (priv->clks[priv->num_core_clks + id] == ERR_PTR(-ENOENT))  in rzv2h_cpg_is_pm_clk()
978 		clock = to_mod_clock(__clk_get_hw(priv->clks[priv->num_core_clks + id]));  in rzv2h_cpg_is_pm_clk()
980 		return !clock->no_pm;  in rzv2h_cpg_is_pm_clk()
992 	struct device_node *np = dev->of_node;  in rzv2h_cpg_attach_dev()
999 	for (i = 0; !of_parse_phandle_with_args(np, "clocks", "#clock-cells", i, &clkspec); i++) {  in rzv2h_cpg_attach_dev()
1052 	struct device *dev = priv->dev;  in rzv2h_cpg_add_pm_domains()
1053 	struct device_node *np = dev->of_node;  in rzv2h_cpg_add_pm_domains()
1059 		return -ENOMEM;  in rzv2h_cpg_add_pm_domains()
1061 	pd->genpd.name = np->name;  in rzv2h_cpg_add_pm_domains()
1062 	pd->priv = priv;  in rzv2h_cpg_add_pm_domains()
1063 	pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;  in rzv2h_cpg_add_pm_domains()
1064 	pd->genpd.attach_dev = rzv2h_cpg_attach_dev;  in rzv2h_cpg_add_pm_domains()
1065 	pd->genpd.detach_dev = rzv2h_cpg_detach_dev;  in rzv2h_cpg_add_pm_domains()
1066 	ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);  in rzv2h_cpg_add_pm_domains()
1070 	ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);  in rzv2h_cpg_add_pm_domains()
1074 	return of_genpd_add_provider_simple(np, &pd->genpd);  in rzv2h_cpg_add_pm_domains()
1084 	struct device *dev = &pdev->dev;  in rzv2h_cpg_probe()
1085 	struct device_node *np = dev->of_node;  in rzv2h_cpg_probe()
1096 		return -ENOMEM;  in rzv2h_cpg_probe()
1098 	spin_lock_init(&priv->rmw_lock);  in rzv2h_cpg_probe()
1100 	priv->dev = dev;  in rzv2h_cpg_probe()
1102 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in rzv2h_cpg_probe()
1103 	if (IS_ERR(priv->base))  in rzv2h_cpg_probe()
1104 		return PTR_ERR(priv->base);  in rzv2h_cpg_probe()
1106 	nclks = info->num_total_core_clks + info->num_hw_mod_clks;  in rzv2h_cpg_probe()
1109 		return -ENOMEM;  in rzv2h_cpg_probe()
1111 	priv->mstop_count = devm_kcalloc(dev, info->num_mstop_bits,  in rzv2h_cpg_probe()
1112 					 sizeof(*priv->mstop_count), GFP_KERNEL);  in rzv2h_cpg_probe()
1113 	if (!priv->mstop_count)  in rzv2h_cpg_probe()
1114 		return -ENOMEM;  in rzv2h_cpg_probe()
1117 	priv->mstop_count -= 16;  in rzv2h_cpg_probe()
1119 	priv->resets = devm_kmemdup_array(dev, info->resets, info->num_resets,  in rzv2h_cpg_probe()
1120 					  sizeof(*info->resets), GFP_KERNEL);  in rzv2h_cpg_probe()
1121 	if (!priv->resets)  in rzv2h_cpg_probe()
1122 		return -ENOMEM;  in rzv2h_cpg_probe()
1125 	priv->clks = clks;  in rzv2h_cpg_probe()
1126 	priv->num_core_clks = info->num_total_core_clks;  in rzv2h_cpg_probe()
1127 	priv->num_mod_clks = info->num_hw_mod_clks;  in rzv2h_cpg_probe()
1128 	priv->last_dt_core_clk = info->last_dt_core_clk;  in rzv2h_cpg_probe()
1129 	priv->num_resets = info->num_resets;  in rzv2h_cpg_probe()
1132 		clks[i] = ERR_PTR(-ENOENT);  in rzv2h_cpg_probe()
1134 	for (i = 0; i < info->num_core_clks; i++)  in rzv2h_cpg_probe()
1135 		rzv2h_cpg_register_core_clk(&info->core_clks[i], priv);  in rzv2h_cpg_probe()
1137 	for (i = 0; i < info->num_mod_clks; i++)  in rzv2h_cpg_probe()
1138 		rzv2h_cpg_register_mod_clk(&info->mod_clks[i], priv);  in rzv2h_cpg_probe()
1162 		.compatible = "renesas,r9a09g047-cpg",
1168 		.compatible = "renesas,r9a09g056-cpg",
1174 		.compatible = "renesas,r9a09g057-cpg",
1183 		.name	= "rzv2h-cpg",