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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddivider.txt1 Binding for TI divider clock
4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
42 The binding must also provide the register to control the divider and
43 unless the divider array is provided, min and max dividers. Optionally
44 the number of bits to shift that mask, if necessary. If the shift value
45 is missing it is the same as supplying a zero shift.
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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H A Dti,divider-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments divider clock
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
[all …]
H A Dautoidle.txt6 clock, it is always a derivative of some basic clock like a gate, divider,
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
21 ti,max-div = <31>;
22 ti,autoidle-shift = <8>;
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H A Dcomposite.txt4 register-mapped composite clock with multiple different sub-types;
9 an adjustable clock rate divider, this behaves exactly as [3]
16 "ti,*composite*-clock" types.
18 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
19 [2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
20 [3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
24 - compatible : shall be: "ti,composite-clock"
25 - clocks : link phandles of component clocks
26 - #clock-cells : from common clock binding; shall be set to 0.
29 - clock-output-names : from common clock binding.
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H A Dti,composite-clock.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,composite-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
15 This binding assumes a register-mapped composite clock with multiple
16 different sub-types:
21 an adjustable clock rate divider, this behaves exactly as [2].
28 "ti,*composite*-clock" types.
30 [1] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
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H A Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
17 - reg : shall be the physical PLL register address for the pll clock.
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H A Dapm,xgene-device-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: APM X-Gene SoC device clocks
10 - Khuong Dinh <khuong@os.amperecomputing.com>
14 const: apm,xgene-device-clock
20 reg-names:
22 - enum: [ csr-reg, div-reg ]
23 - const: div-reg
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H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap44xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "extalt_clkin_ck";
12 clock-frequency = <59000000>;
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-output-names = "pad_clks_src_ck";
19 clock-frequency = <12000000>;
23 #clock-cells = <0>;
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H A Domap54xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
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H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
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H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
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H A Ddm816x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #clock-cells = <1>;
6 compatible = "ti,dm816-fapll-clock";
9 clock-indices = <1>, <2>, <3>, <4>, <5>,
11 clock-output-names = "main_pll_clk1",
21 #clock-cells = <1>;
22 compatible = "ti,dm816-fapll-clock";
25 clock-indices = <1>, <2>, <3>, <4>;
26 clock-output-names = "ddr_pll_clk1",
33 #clock-cells = <1>;
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H A Domap24xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "ti,composite-mux-clock";
12 ti,bit-shift = <2>;
17 #clock-cells = <0>;
18 compatible = "ti,composite-clock";
23 #clock-cells = <0>;
24 compatible = "ti,composite-mux-clock";
26 ti,bit-shift = <6>;
31 #clock-cells = <0>;
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H A Domap2420-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <0>;
11 compatible = "ti,composite-no-wait-gate-clock";
13 ti,bit-shift = <15>;
18 #clock-cells = <0>;
19 compatible = "ti,composite-mux-clock";
21 ti,bit-shift = <8>;
26 #clock-cells = <0>;
27 compatible = "ti,composite-clock";
32 #clock-cells = <0>;
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H A Domap3xxx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <16800000>;
15 #clock-cells = <0>;
16 compatible = "ti,mux-clock";
22 #clock-cells = <0>;
23 compatible = "ti,divider-clock";
25 ti,bit-shift = <6>;
26 ti,max-div = <3>;
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
[all …]
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - enum:
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
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/freebsd/sys/dev/clk/allwinner/
H A Daw_clk.h1 /*-
46 Clock Source/Divider N/Divider M
47 Clock Source/Divider N/Divider M/2
48 Clock Source*N/(Divider M+1)/(Divider P+1)
77 uint32_t shift; /* Shift bits for the factor */ member
106 if (factor->flags & AW_CLK_FACTOR_HAS_COND) { in aw_clk_get_factor()
107 cond = (val & factor->cond_mask) >> factor->cond_shift; in aw_clk_get_factor()
108 if (cond != factor->cond_value) in aw_clk_get_factor()
112 if (factor->flags & AW_CLK_FACTOR_FIXED) in aw_clk_get_factor()
113 return (factor->value); in aw_clk_get_factor()
[all …]
H A Dccu_a13.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/reset/sun5i-ccu.h>
50 /* Non-exported clocks */
101 CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0)
103 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0)
104 CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1)
105 CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2)
106 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5)
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/freebsd/sys/dev/clk/rockchip/
H A Drk_cru.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
56 .shift = _s, \
73 /* Fixed factor multipier/divider. */
123 /* Fractional rate multipier/divider. */
157 /* Composite clock without mux (divider only). */
174 /* Complex clock without divider (multiplexer only). */
185 .shift = _ms, \
194 /* Complex clock without divider (multiplexer only in GRF). */
205 .shift = _ms, \
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/freebsd/sys/arm/ti/clk/
H A Dti_divider_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
53 * Documentation/devicetree/bindings/clock/ti/divider.txt
74 { "ti,divider-clock", TI_DIVIDER_CLOCK },
75 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },
83 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
84 if (sc->clkdom == NULL) { in register_clk()
85 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
89 err = clknode_div_register(sc->clkdom, &sc->div_def); in register_clk()
91 DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err); in register_clk()
[all …]
/freebsd/sys/arm/mv/clk/
H A Dperiph.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
68 .clk_def.full_dd.tbg_mux.shift = _tbg_mux_shift, \
89 .clk_def.full_dd.clk_mux.shift = _clk_mux_shift, \
94 .clk_def.full_dd.gate.shift = _gate_shift, \
110 .clk_def.full_d.tbg_mux.shift = _tbg_mux_shift, \
123 .clk_def.full_d.clk_mux.shift = _clk_mux_shift, \
128 .clk_def.full_d.gate.shift = _gate_shift, \
143 .clk_def.cpu.tbg_mux.shift = _tbg_mux_shift, \
156 .clk_def.cpu.clk_mux.shift = _clk_mux_shift, \
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
42 #include <dt-bindings/clock/tegra210-car.h>
71 #define PLL_FLAG_PDIV_POWER2 0x01 /* P Divider is 2^n */
113 /* Post divider <-> register value mapping. */
115 uint32_t divider; /* real divider */ member
160 .shift = s, \
164 /* Fractional divider (7.1) for PLL branch. */
179 /* P divider (2^n). for PLL branch. */
192 /* P divider (2^n). for PLL branch. */
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